Si5382E-E-GM [SILICON]
Multi-DSPLL Wireless Jitter Attenuating Clocks;型号: | Si5382E-E-GM |
厂家: | SILICON |
描述: | Multi-DSPLL Wireless Jitter Attenuating Clocks 无线 |
文件: | 总51页 (文件大小:818K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si5381/82 Data Sheet
Multi-DSPLL Wireless Jitter Attenuating Clocks
KEY FEATURES
The Si5381/82 is a wireless multi-PLL, jitter-attenuating clock that leverages Silicon
Labs’ latest fourth-generation DSPLL technology to address the form factor, power, and
performance requirements demanded by radio area network equipment, such as small
cells, baseband units, and distributed antenna systems (DAS). The Si538x is the indus-
try’s first multi-PLL wireless clock generator family capable of replacing discrete, high-
performance, VCXO-based clocks with a fully integrated CMOS IC solution. The
Si5381/82 features a multi-PLL architecture that supports independent timing paths for
JESD wireless clocks with less than 85 fs typical phase jitter as well as Ethernet and oth-
er low-jitter, general-purpose clocks. DSPLL technology also supports free-run and hold-
over operation as well as automatic and hitless input clock switching. This unparalleled
integration reduces power and size without compromising the stringent performance and
reliability demanded in wireless applications.
• Supports simultaneous wireless and
general-purpose clocking in a single
device
• Jitter performance: 85 fs RMS typ (12
kHz–20 MHz)
• Input frequency range:
• Differential: 8 kHz – 750 MHz
• LVCMOS: 8 kHz – 250 MHz
• Output frequency range:
• JESD204B: 480 kHz - 2.94912 GHz
• Differential: 1 Hz – 712.5 MHz
• LVCMOS: 480 kHz – 250 MHz
Applications
• Pico cells, small cells
• Mobile backhaul
• Multiservice Distributed Access Systems (MDAS)
Si5381/82
Integrated XO Circuit
OSC
÷INT
OUT0A
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
DSPLL
C
IN0
IN1
IN2
IN3
÷INT
÷INT
÷INT
÷INT
DSPLL
D
DSPLL
A
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT9A
DSPLL
B
Si5381
Si5382
NVM
I2C/SPI
Control/
Status
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.9
Si5381/82 Data Sheet
Feature List
1. Feature List
The Si5381/82 highlighted features are listed below.
• Digital frequency synthesis eliminates external VCXO and an-
alog loop filter components
• Independent output supply pins: 3.3, 2.5, or 1.8 V
• Core voltage:
• DSPLL_B supports high-frequency, wireless clocking. Re-
maining three DSPLLs support general-purposing clocking
• VDD = 1.8 V ±5%
• VDDA = 3.3 V ±5%
• Integrated crystal option (Grade E)
• Input frequency range:
• Automatic free-run, lock, and holdover modes
• Digitally selectable loop bandwidth: DSPLL_B: 1 Hz to 4 kHz
• Hitless switching between input clocks
• Status monitoring (LOS, OOF, LOL)
• Differential: 7.68 MHz–750 MHz
• LVCMOS: 10 MHz–250 MHz
• Output frequency range (DSPLL_B):
• Differential: up to 2.94912 GHz
• LVCMOS: up to 250 MHz
Serial interface: I2C or SPI in-circuit programmable with non-
volatile OTP memory
•
ClockBuilderTM Pro software tool simplifies device configura-
tion
•
• Output frequency range (DSPLL_A/C/D):
• Differential: up to 735 MHz
• 4 input, 12 output, 64QFN
• LVCMOS: up to 250 MHz
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
• Excellent jitter performance:
• DSPLL_B: 85 fs typ (12 kHz - 20 MHz)
• DSPLL_A/C/D: 150 fs typ (12 kHz - 20 MHz)
• Phase noise floor: –165 dBc/Hz
• Spur performance: –95 dBc max (relative to a 122.88 MHz
carrier)
• Flexible crosspoints route any input to any output clock
• Configurable outputs:
• Compatible with LVDS, LVPECL, LVCMOS, CML, HCSL
• Programmable signal amplitude
• Adjustable output-output delay: 68 ps/step, ±128 steps
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Preliminary Rev. 0.9 | 2
Si5381/82 Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Ordering Guide
Maximum Output Frequency
Number of
Ordering Part
Number
Refer-
ence
#
Clock In-
puts/
Outputs
RoHS-6,
Pb-Free
Temperature
Range
4G/LTE
JESD204B
Clocks
General
Purpose
Clocks
Package
DSPLL
Si5381A-E-GM
Si5382A-E-GM
External
External
4
2
4 / 12
4 / 12
2.94912 GHz
2.94912 GHz
735 MHz
735 MHz
64-Lead
9x9 mm
QFN
Internal
Crystal
Yes
–40 to +85 °C
Si5381E-E-GM
Si5382E-E-GM
4
2
4 / 12
4 / 12
2.94912 GHz
2.94912 GHz
735 MHz
735 MHz
64-Lead
9x9 mm
LGA
Internal
Crystal
Si5381E-E-EVB
Si5382E-E-EVB
Note:
Evaluation Board
Evaluation Board
1. Add an “R” at the end of the device to denote tape and reel options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by ClockBuilder Pro. Part number
format is: Si5381E-Exxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration.
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Preliminary Rev. 0.9 | 3
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1 Si5381/82 4G/LTE Frequency Configuration . . . . . . . . . . . . . . . . . 6
3.1.2 Si5381/82 Configuration for Wireless Clock Generation . . . . . . . . . . . . . . 7
3.1.3 DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.4 Fastlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.6 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.7 Free-run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.8 Lock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.9 Locked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.10 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 External Reference (XA/XB) (Grade A Only) . . . . . . . . . . . . . . . . . . .10
3.3 Inputs (IN0, IN1, IN2, IN3). . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3.1 Input Configuration and Terminations . . . . . . . . . . . . . . . . . . . .12
3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . .12
3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . .13
3.3.4 Hitless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . .13
3.3.5 Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . .13
3.3.6 Zero Delay Mode (ZDM) . . . . . . . . . . . . . . . . . . . . . . . .14
3.4 Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.4.1 Input LOS Detection. . . . . . . . . . . . . . . . . . . . . . . . . .15
3.4.2 Reference LOS Detection . . . . . . . . . . . . . . . . . . . . . . . .15
3.4.3 OOF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.4.4 Precision OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . .16
3.4.5 Fast OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.4.6 LOL Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.4.7 Interrupt Pin INTRb . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.5 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.5.1 Output Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.5.2 Output Signal Format . . . . . . . . . . . . . . . . . . . . . . . . .18
3.5.3 Output Terminations. . . . . . . . . . . . . . . . . . . . . . . . . .19
3.5.4 Programmable Common Mode Voltage for Differential Outputs . . . . . . . . . . .19
3.5.5 LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . .20
3.5.6 LVCMOS Output Impedance and Drive Strength Selection. . . . . . . . . . . . .20
3.5.7 LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . .20
3.5.8 LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . .20
3.5.9 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . .21
3.5.10 Output Disable During LOL . . . . . . . . . . . . . . . . . . . . . . .21
3.5.11 Output Disable During Reference LOS (XAXB, Internal Crystal) . . . . . . . . . .21
3.5.12 Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . .21
3.5.13 Synchronous Enable/Disable Feature . . . . . . . . . . . . . . . . . . .21
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Preliminary Rev. 0.9 | 4
3.5.14 Output Divider (R) Synchronization . . . . . . . . . . . . . . . . . . . .21
3.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.6.1 Power Down Pin (PDNb) . . . . . . . . . . . . . . . . . . . . . . . .21
3.7 In-Circuit Programming. . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.8 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.9 Custom Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . .22
3.10 How to Enable Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory
Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Register Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Typical Application Diagram
. . . . . . . . . . . . . . . . . . . . . . . .38
. . . . . . . . . . . . . . . . . . . . . . . . . . 39
7. Detailed Block Diagram
8. Typical Operating Characteristics (Phase Noise and Jitter) . . . . . . . . . . . . . 40
9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10. Packages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.1 64-LGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
10.2 64-QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14.1 Revision 0.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
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Preliminary Rev. 0.9 | 5
Si5381/82 Data Sheet
Functional Description
3. Functional Description
The Si5381/82 integrates four/two independent any-frequency DSPLLs in a monolithic IC for applications that require a combination of
4G/LTE and general-purpose clocking. Any clock input can be routed to any DSPLL. The output of any DSPLL can be routed to any of
the device clock outputs. Based on 4th generation DSPLL technology, the Si5381/82 provides a clock-tree-on-a-chip solution for appli-
cations that need a mix of 4G/LTE and general-purpose frequencies.
3.1 Frequency Configuration
The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile
memory. DSPLL_B generates 4G/LTE frequencies. For DSPLL_A/C/D, fractional frequency multiplication (Mn/Md) allows each of the
DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a specific frequency plan are
easily determined using the ClockBuilder Pro utility.The Si5382 supports one general-purpose DSPLL (DSPLL_A).
3.1.1 Si5381/82 4G/LTE Frequency Configuration
The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory.
The combination of flexible integer dividers and a high frequency VCO allows the device to generate multiple output clock frequencies
for applications that require ultra-low phase noise and spurious performance. The table below shows a list of possible output frequen-
cies for LTE applications. Note that these 4G/LTE frequencies may be generated with an Ethernet input clock to DSPLL_B. These fre-
quencies are distributed to the output dividers using a configurable crosspoint mux. The R dividers allow further division for up to 10
unique integer-ratio related frequencies on the Si5381/82. The ClockBuilder Pro software utility provides a simple means of automati-
cally calculating the optimum divider values (P, M, N and R) for the frequencies listed in the table below.
Table 3.1. Example of Possible 4G/LTE Clock Frequencies
4G/LTE Device Clock Frequencies Fout (MHz)
15.36
19.20
30.72
38.40
61.44
76.80
122.88
153.60
184.32
245.76
307.20
368.64
491.52
614.40
737.28
983.04
1228.80
1474.56
2949.12
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Preliminary Rev. 0.9 | 6
Si5381/82 Data Sheet
Functional Description
3.1.2 Si5381/82 Configuration for Wireless Clock Generation
The Si5381/82 can be used as a high performance, fully integrated wireless jitter cleaner while eliminating the need for discrete VCXO
and loop filter components. The Si5381/82 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks
(DCLK) and system reference clocks (SYSREF). The clock outputs can be independently configured as device clocks or SYSREF
clocks to drive JESD204B converters, FPGAs, or other logic devices. An example frequency configuration is shown in the figure below.
In this case, the N dividers determine the device clock frequency and the R dividers provide the divided SYSREF clock which is used as
the lower frequency frame clock. The SYSREF clock is always periodic and can be controlled (on/off) without glitches by enabling or
disabling its output through register writes.
Si5381
VDDO3
OUT3
OUT3b
÷R3
VDDO4
OUT4
OUT4b
÷R4
Device
Clocks
&
SYSREF
(Group 1)
÷N1
VDDO5
OUT5
OUT5b
÷R5
÷R6
÷R7
÷R8
VDDO6
OUT6
OUT6b
From
DSPLL B
VDDO7
OUT7
OUT7b
VDDO8
OUT8
OUT8b
Device
Clocks
&
÷N4
SYSREF
(Group 2)
OUT9
OUT9b
÷R9
OUT9A
OUT9Ab
÷R9A
VDDO9
VDDO1
OUT1
OUT1b
÷R1
÷R2
VDDO2
OUT2
OUT2b
From DSPLL
A/C/D
Ethernet,
Processor
Clocks
VDDO0
OUT0A
OUT0Ab
÷R0A
÷R0
OUT0
OUT0b
Figure 3.1. Example Divider Configuration for Generating JESD204B Subclass 1 Clocks
3.1.3 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and support a digitally selectable loop bandwidth
ranging from 1 Hz to 4000 Hz. DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the DSPLL loop band-
width selection.
3.1.4 Fastlock
Selecting a low DSPLL loop bandwidth (e.g., 1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a
temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable
the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 1 Hz to 4 kHz are available for selection. Once lock acquis-
ition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting as described in section
3.1.3 DSPLL Loop Bandwidth. The fastlock feature can be enabled or disabled independently for each of the DSPLLs.
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Preliminary Rev. 0.9 | 7
Si5381/82 Data Sheet
Functional Description
3.1.5 Modes of Operation
Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition
Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following
sections describe each of these modes in greater detail.
Power-Up
Reset and
Initialization
No valid
input clocks
selected
Free-run
Valid input clock
selected
An input is qualified
and available for
selection
Lock Acquisition
(Fast Lock)
Phase lock on
selected input
clock is achieved
Holdover
Mode
No
Selected input
clock fails
Is holdover
history valid?
Locked
Mode
Figure 3.2. Modes of Operation
3.1.6 Initialization and Reset
When power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard
reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be re-
stored to their initial state including the serial interface. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A
soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all DSPLLs,
while a soft reset can either affect all or each DSPLL individually.
3.1.7 Free-run Mode
Once power is applied to the Si5381/82 and initialization is complete, all DSPLLs will automatically enter Free-run Mode. The frequency
accuracy of the reference clock (internal crystal or external reference on XA/XB pins). Any drift of the crystal frequency will be tracked
at the output clock frequencies. A TCXO or OCXO is recommended for applications that require better frequency accuracy and stability
while in Free-run Mode or Holdover Mode.
3.1.8 Lock Acquisition
Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchroni-
zation, a DSPLL will automatically start the lock acquisition process. If the fastlock feature is enabled, a DSPLL will acquire lock using
the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. Dur-
ing lock acquisition, the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.
3.1.9 Locked Mode
Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point,
any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own status bit to indicate when lock is achieved. See
3.4.6 LOL Detection for more details on the operation of the loss of lock circuit.
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Preliminary Rev. 0.9 | 8
Si5381/82 Data Sheet
Functional Description
3.1.10 Holdover Mode
Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input
clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the
disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores up
to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calcula-
ted from a programmable window within the stored historical frequency data. Both the window size and delay are programmable as
shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring
frequency data that may be corrupt just before the input clock failure.
Figure 3.3. Programmable Holdover Window
Clock Failure
and Entry into
Holdover
Historical Frequency Data Collected
time
Programmable historical data window
Programmable delay
used to determine the final holdover value
120s
0s
30ms, 60ms, 1s,10s, 30s, 60s
1s,10s, 30s, 60s
When entering Holdover Mode, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in
Holdover Mode, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the
XA/XB pins. If the clock input becomes valid, a DSPLL will automatically exit the Holdover Mode and reacquire lock to the new input
clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in
process is glitchless, and its rate is controlled by the DSPLL bandwidth or the fastlock bandwidth. These options are register program-
mable.
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Preliminary Rev. 0.9 | 9
Si5381/82 Data Sheet
Functional Description
3.2 External Reference (XA/XB) (Grade A Only)
An external crystal (XTAL) can be used on Grade A parts in combination with the internal oscillator (OSC) to produce an ultra-low
phase noise reference clock for the DSPLLs and for providing a stable reference for the free-run and holdover modes. A simplified dia-
gram is shown in the figure below. The Si5381/82 includes internal XTAL loading capacitors which eliminates the need for external ca-
pacitors and also has the benefit of reduced noise coupling from external sources. Refer to the Si5381/82 Datasheet for crystal specifi-
cations. A crystal frequency of 54 MHz is required, with a total accuracy of ±100 ppm* recommended for best performance. The
Si5381/82 includes built-in XTAL load capacitors (CL) of 8 pF, which are switched out of the circuit when using an external XO. The
Si5381/82 Family Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum
jitter performance. The Si5381/82 can also accommodate an external reference clock (REFCLK) instead of a crystal. Selection between
the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in this
mode. It is important to note that when using the REFCLK option the close-in phase noise of the outputs is directly affected by the
phase noise of the external XO reference. Refer to the Si5381/82 Datasheet for REFCLK signal requirements when using this mode.
Note: Including initial frequency tolerance and frequency variation over the full operating temperature range, voltage range, load condi-
tions, and aging.
Differential Connection
Single-ended XO Connection
X1
nc
X1
nc
X2
nc
X2
nc
0.1 uf
Note: 2.0 Vpp_se max
2xCL
2xCL
0.1 uf
XA
XA
0.1 uf
OSC
OSC
XB
XO with Clipped Sine
Wave Output
XB
0.1 uf
2xCL
2xCL
Si5381/82
Si5381/82
0.1 uf
Note: 2.5 Vpp diff max
Crystal Connection
Single-ended Connection
X1
nc
X2
nc
Note: 2.0 Vpp_se max
X1
2xCL
CMOS/XO
Output
2xCL
XA
0.1 uf
XA
R1
XTAL
OSC
OSC
R2
0.1 uf
XB
0.1 uf
XB
X2
2xCL
2xCL
Si5381/82
Si5381/82
Figure 3.4. XAXB Crystal Resonator and External Reference Clock Connection Options
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Preliminary Rev. 0.9 | 10
Si5381/82 Data Sheet
Functional Description
3.3 Inputs (IN0, IN1, IN2, IN3)
There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both differential and single-ended clocks.
A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of the DSPLLs as shown in the figure
below.
Input Crosspoint
IN0
0
÷P0
IN0b
DSPLL
1
2
A
3
0
IN1
1
2
3
DSPLL
B
÷P1
÷P2
÷P3
IN1b
0
1
2
3
DSPLL
C
IN2
IN2b
0
1
2
3
DSPLL
D
IN3/FB_IN
IN3b/FB_INb
Figure 3.5. DSPLL Input Selection Crosspoint
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Preliminary Rev. 0.9 | 11
Si5381/82 Data Sheet
Functional Description
3.3.1 Input Configuration and Terminations
Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown
in the figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle pulsed CMOS signals can be dc-cou-
pled. Unused inputs can be disabled and left unconnected when not in use.
Standard AC-coupled Differential LVDS
Si5381/82
Standard
50
INx
100
3.3 V, 2.5 V
LVDS or
CML
INxb
50
Pulsed CMOS
Standard AC-coupled Differential LVPECL
Si5381/82
Standard
50
INx
100
INxb
50
3.3 V, 2.5 V
LVPECL
Pulsed CMOS
Standard AC-coupled Single-ended
Si5381/82
50
Standard
INx
3.3 V, 2.5 V, 1.8 V
LVCMOS
INxb
Pulsed CMOS
Pulsed CMOS DC-coupled Single-ended
Si5381/82
R1
Standard
INx
50
R2
INxb
3.3 V, 2.5 V, 1.8 V
LVCMOS
R1
R2
Pulsed CMOS
VDD
1.8V
2.5V
3.3V
(Ohms) (Ohms)
Resistor values for
fIN_PULSED < 1 MHz
324
511
634
665
475
365
Figure 3.6. Termination of Differential and LVCMOS Input Signals
3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3)
Input clock selection can be made manually using the IN_SEL[1:0] pins for DSPLL_B or through a register for all DSPLLs. A register bit
determines input selection as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal
on the selected input, the device will automatically enter free-run or holdover mode.
Table 3.2. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0]
Selected Input to DSPLL_B
0
0
1
1
0
1
0
1
IN0
IN1
IN2
IN3
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Preliminary Rev. 0.9 | 12
Si5381/82 Data Sheet
Functional Description
3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3)
An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection
criteria is based on reference qualification, input priority, and the revertive option. Only references which are valid can be selected by
the automatic state machine. If there are no valid references available, the DSPLL will enter the Holdover Mode. With revertive switch-
ing enabled, the highest priority input with a valid reference is always selected. If an input with a higher priority becomes valid, then an
automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected while it is
valid. If it becomes invalid, an automatic switchover to a valid input with the highest priority will be initiated.
3.3.4 Hitless Input Switching
Hitless switching is a feature that prevents a phase transient from propagating to the output when switching between two frequency
locked clock inputs that have a fixed phase difference between them. A hitless switch can only occur when the two input frequencies
are frequency locked meaning that they have to be exactly at the same frequency, or have an integer frequency relationship to each
other. When this feature is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during an input
switch. When disabled (normal switching), the phase difference between the two inputs is propagated to the output at a rate determined
by the DSPLL loop bandwidth.
3.3.5 Glitchless Input Switching
Each DSPLL has the ability of switching between two input clocks that are up to ±20 ppm apart in frequency. The DSPLL will pull-in to
the new frequency using the DSPLL loop bandwidth or using the Fastlock loop bandwidth if it is enabled. The loss of lock (LOL) indica-
tor will be asserted while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the out-
put. Glitchless input switching is available regardless of whether the hitless switching feature is enabled or disabled.
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Preliminary Rev. 0.9 | 13
Si5381/82 Data Sheet
Functional Description
3.3.6 Zero Delay Mode (ZDM)
Zero delay mode is configured for DSPLL B by opening the internal feedback loop through software configuration and closing the loop
externally around as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the
input, and the output drivers. Any output generated by DSPLL B can be fed back to the IN3/FB_IN pins, although using the output driver
that achieves the shortest trace length will help to minimize the input-to-output delay. The OUT9A and IN3/FB_IN pins are recommen-
ded for the external feedback connection. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A
differential external feedback path connection is necessary for best performance. The order of the OUT9A and FB_IN polarities is such
that they may be routed on the device side of the PCB without requiring vias or needing to cross each other. Zero delay mode is not
available on Si5381/82 A, C, or D DSPLLs.
IN0
Si5381
÷P0
IN0b
IN1
DSPLL B
÷P1
IN1b
PD LPF
IN2
÷P2
IN2b
÷M
÷5
IN3/FB_IN
÷P3
VDDO0
IN3b/FB_INb
OUT0A
OUT0Ab
÷R0A
÷R0
OUT0
OUT0b
VDDO2
OUT2
OUT2b
t1
÷N1
÷R2
VDDO8
OUT8
OUT8b
÷R8
t4
÷N4
OUT9
OUT9b
÷R9
OUT9A
÷R9A
OUT9Ab
VDDO9
External Feedback Path
Figure 3.7. Zero Delay Mode (ZDM) Setup
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Preliminary Rev. 0.9 | 14
Si5381/82 Data Sheet
Functional Description
3.4 Fault Monitoring
All four input clocks (IN0, IN1, IN2, IN3) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the figure be-
low. The reference at the XA/XB pins is also monitored for LOS since it provides a critical clock for the DSPLLs (external XA/XB pins on
grade A only). Each DSPLL also has a Loss Of Lock (LOL) indicator, which is asserted when the DSPLL has lost synchronization with
the selected input clock.
XA XB
OSC
LOS
DSPLL A
LOL
PD
LPF
÷M
IN0
Precision
Fast
LOS
LOS
LOS
LOS
OOF
OOF
OOF
OOF
÷P0
÷P1
÷P2
÷P3
DSPLL B
IN0b
LOL
PD
LPF
÷M
IN1
Precision
Fast
IN1b
Precision
Fast
IN2
DSPLL C
LOL
PD
IN2b
LPF
÷M
IN3
Precision
Fast
IN3b
DSPLL D
LOL
PD
LPF
÷M
Figure 3.8. Si5381/82 Fault Monitors (Grade A Shown)
3.4.1 Input LOS Detection
The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of
the input LOS circuits have their own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal
sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status
register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option
to disable any of the LOS monitors is also available.
Sticky
Monitor
LOS
LOS
en
Live
Figure 3.9. LOS Status Indicators
3.4.2 Reference LOS Detection
An LOS monitor is available to ensure that the reference clock (REFCLK) XA/XB external reference (grade A) or internal crystal (grade
E) is valid. By default, the output clocks are disabled when reference LOS is detected. This feature can be disabled such that the device
will continue to produce output clocks when reference LOS is detected. See the 3.5.11 Output Disable During Reference LOS (XAXB,
Internal Crystal) section for details.
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Preliminary Rev. 0.9 | 15
Si5381/82 Data Sheet
Functional Description
3.4.3 OOF Detection
Each input clock is monitored for frequency accuracy with respect to an OOF reference which it considers as its “0_ppm” reference.
This OOF reference can be selected as either: XA/XB/internal crystal, IN0, IN1, IN2 or IN3. The final OOF status is determined by the
combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure below. An option to disable either monitor is
also available. The live OOF register always displays the current OOF state, and its sticky register bit stays asserted until cleared.
Sticky
Monitor
Precision
Fast
en
en
OOF
OOF
Live
Figure 3.10. OOF Status Indicator
3.4.4 Precision OOF Monitor
The Precision OOF monitor circuit measures the frequency of all input clocks to within ±1 ppm accuracy with respect to the reference
clock (XA/XB on Grade A and internal crystal on Grade E). The OOF monitor considers the frequency at the reference pins as its 0 ppm
OOF reference. A valid input frequency is one that remains within the OOF frequency range which is register configurable from ±2 ppm
to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the
failure boundary. An example is shown in the figure below. In this case the OOF monitor is configured with a valid frequency range of
±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of the
XA/XB pins is available. This option is register configurable.
OOF Declared
OOF Cleared
fIN
Hysteresis
Hysteresis
-4 ppm
(Clear)
-6 ppm
(Set)
+4 ppm
(Clear)
+6 ppm
(Set)
0 ppm
OOF
Reference
Figure 3.11. Example of Precise OOF Monitor Assertion and De-assertion Triggers
3.4.5 Fast OOF Monitor
Because the precision OOF monitor needs to provide 1 ppm of frequency measurement accuracy, it must measure the monitored input
clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequen-
cy. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect
a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by 1,000 to 16,000 ppm.
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Preliminary Rev. 0.9 | 16
Si5381/82 Data Sheet
Functional Description
3.4.6 LOL Detection
There is an LOL monitor for each of the DSPLLs. The LOL monitor asserts an LOL register bit when a DSPLL has lost synchronization
with its selected input clock. The LOL monitor functions by measuring the frequency difference between the input and feedback clocks
at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the
indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to com-
pletely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes
lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The live LOL register always displays the current LOL
state and a sticky register always stays asserted until cleared.
Sticky
Si5381/82
LOL Status Registers
Live
DSPLL D
DSPLL C
DSPLL B
DSPLL A
LOL Monitor
LOL
Clear
t
LOL
Set
DSPLL A
fIN
PD
LPF
÷M
Figure 3.12. LOL Status Indicators
Each of the frequency monitors have adjustable sensitivity which is register configurable from 0.1 ppm to 10000 ppm. Having two sepa-
rate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indica-
ted when there is less than 0.2 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is more
than 2 ppm frequency difference is shown in the figure below.
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
LOL
Hysteresis
Lost Lock
LOCKED
0
0.2
2
20000
Phase Detector Frequency Difference (ppm)
Figure 3.13. LOL Set and Clear Thresholds
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely phase lock to
the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisi-
tion. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calcula-
ted using the ClockBuilder Pro utility.
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Preliminary Rev. 0.9 | 17
Si5381/82 Data Sheet
Functional Description
3.4.7 Interrupt Pin INTRb
An interrupt pin (INTRb) indicates a change in state with any of the status indicators for any of the DSPLLs. All status indicators are
maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the sticky status registers.
mask
IN0_LOS_FLG
IN0
mask
IN0_OOF_FLG
mask
IN1_LOS_FLG
IN1
mask
IN1_OOF_FLG
mask
IN2_LOS_FLG
IN2
mask
IN2_OOF_FLG
INTRb
mask
IN3_LOS_FLG
IN3
mask
IN3_OOF_FLG
mask
XAXB_LOS_FLG
mask
LOLA_FLG
mask
LOLB_FLG
mask
LOL
LOLC_FLG
mask
LOLD_FLG
mask
HOLDA_FLG
mask
HOLDB_FLG
mask
HOLD
HOLDC_FLG
mask
HOLDD_FLG
Figure 3.14. Interrupt Triggers and Masks
3.5 Outputs
The Si5381/82 supports up to twelve differential output drivers. Each driver has a configurable voltage amplitude and common mode
voltage covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differ-
ential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 24 single-ended
outputs, or any combination of differential and single-ended outputs.
3.5.1 Output Crosspoint
A crosspoint allows any of the output drivers to connect with any of the DSPLLs. The crosspoint configuration is programmable and can
be stored in NVM so that the desired output configuration is ready at power-up.
3.5.2 Output Signal Format
The differential output amplitude and common mode voltage are both fully programmable covering a wide variety of signal formats in-
cluding LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as
LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 24 single-ended outputs, or any combination of differential and single-ended
outputs.
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Preliminary Rev. 0.9 | 18
Si5381/82 Data Sheet
Functional Description
3.5.3 Output Terminations
The output drivers support both ac-coupled and dc-coupled terminations as shown in the following figure.
AC-coupled LVDS/LVPECL
DC-coupled LVDS
VDDO = 3.3 V, 2.5 V, 1.8 V
VDDO = 3.3 V, 2.5 V
50
50
50
50
OUTx
OUTx
100
OUTxb
100
OUTxb
Internally
self-biased
Si5381/82
Si5381/82
AC-coupled LVPECL / CML
DC-coupled LVCMOS
3.3 V, 2.5 V, 1.8 V
LVCMOS
VDD – 1.3 V
VDDO = 3.3 V, 2.5 V, 1.8 V
VDDO = 3.3 V, 2.5 V
50
50
50
50
Rs
Rs
OUTx
50
50
OUTx
OUTxb
OUTxb
Si5381/82
Si5381/82
AC-coupled HCSL
VDDRX
VDDO = 3.3 V, 2.5 V, 1.8 V
R1
R1
OUTx
OUTxb
50
50
Standard
HCSL
Receiver
Si5381/82
R2
R2
For VCM = 0.35 V
VDDRX
R1
R2
442 Ω
56.2 Ω
59 Ω
3.3 V
2.5 V
1.8 V
332 Ω
243 Ω
63.4 Ω
Figure 3.15. Supported Output Terminations
3.5.4 Programmable Common Mode Voltage for Differential Outputs
The common mode voltage (VCM) for the differential normal and low power modes is programmable in 100 mV increments from 0.7 V
to 2.3 V depending on the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when dc-coupling the
output drivers.
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Preliminary Rev. 0.9 | 19
Si5381/82 Data Sheet
Functional Description
3.5.5 LVCMOS Output Terminations
LVCMOS outputs are dc-coupled with source-side series termination as shown in the figure below.
DC-coupled LVCMOS
3.3 V, 2.5 V, 1.8 V
LVCMOS
V
DDO = 3.3V, 2.5V, 1.8V
50
50
Rs
Rs
OUTx
OUTxb
Figure 3.16. LVCMOS Output Terminations
3.5.6 LVCMOS Output Impedance and Drive Strength Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source
termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programma-
ble output impedance selections for each VDDO options as shown in the table below.
Table 3.3. LVCMOS Output Impedance and Drive Strength Selections
VDDO
OUTx_CMOS_DRV
Source Impedance (Zs)
Drive Strength (Iol/Ioh)
3.3 V
0x01
0x02
0x03*
0x01
0x02
0x03*
0x03*
38 Ω
30 Ω
22 Ω
43 Ω
35 Ω
24 Ω
31 Ω
10 mA
12 mA
17 mA
6 mA
2.5 V
1.8 V
8 mA
11 mA
5 mA
Note: Use of the lowest impedance setting is recommended for all supply voltages for best edge rates.
3.5.7 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. OUT0 and OUT0A share the same VDDO pin.
OUT9 and OUT9A also share the VDDO pin. All other outputs have their own individual VDDO pins. Each output driver automatically
detects the voltage on the VDDO pin to properly determine the correct output voltage. By default, both output pins carry the output clock
signal, generating two CMOS output signals for each output driver. It is possible to configure the device to have only one of the output
pins active to reduce power consumption.
3.5.8 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on
the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configura-
ble enabling complimentary clock generation and/or inverted polarity with respect to other output drivers.
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Preliminary Rev. 0.9 | 20
Si5381/82 Data Sheet
Functional Description
3.5.9 Output Enable/Disable
The OEb pin provides a convenient method of disabling or enabling all of the output drivers at the same time. When the OEb pin is held
high all outputs will be disabled. When held low, the outputs will all be enabled. Outputs in the enabled state can still be individually
disabled through register control.
3.5.10 Output Disable During LOL
By default, a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option
to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover.
3.5.11 Output Disable During Reference LOS (XAXB, Internal Crystal)
The internal oscillator circuit (OSC) in combination with the external XA/XB reference (Grade A) internal crystal (Grade E) provides a
critical function for the operation of the DSPLLs. In the event of a crystal failure, the device will assert an XAXB_LOS alarm. By default,
all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an
XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault condition. The internal oscillator circuit
(OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the DSPLLs.
3.5.12 Output Driver State When Disabled
The disabled state of an output driver is configurable as either disable low or disable high.
3.5.13 Synchronous Enable/Disable Feature
The output drivers provide a selectable synchronous enable/disable feature. Output drivers with this feature active will wait until a clock
period has completed before the driver is disabled or enabled. This prevents unwanted runt pulses from occurring when enabling or
disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the period to complete.
3.5.14 Output Divider (R) Synchronization
All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable
phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the reset bit will have the same result.
Asserting the sync register bit provides another method of realigning the R dividers without resetting the device.
3.6 Power Management
Unused inputs and output drivers can be powered down when unused. Consult the ClockBuilder Pro configuration utility for details.
3.6.1 Power Down Pin (PDNb)
A power down pin is provided to force the device in a low power mode. The device’s configuration will be maintained but no output
clocks will be generated. Most of the internal blocks will be shut down but device communication via the serial interface will still be
available. When the PDNb pin is pulled low the outputs will shut down without glitching (the clock’s complete period will be generated
before shutting down). When PDNb is released the device will start generating clocks without glitches. The device will generate free-
running clocks until each DSPLL has acquired lock to the selected input clock source.
3.7 In-Circuit Programming
The Si5381/82 is fully configurable using the serial interface (I2C or SPI). At power-up, the device downloads its default register values
from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to gen-
erate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power sup-
ply voltages applied to its VDD and VDDA pins. The NVM is writable two times. Once a new configuration has been written to NVM, the
old configuration is no longer accessible. Refer to the Si5381/82 Family Reference Manual for a detailed procedure for writing registers
to NVM.
3.8 Serial Interface
Configuration and operation of the Si5381/82 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL
pin selects I2C or SPI operation. The Si5381/82 supports communication with a 3.3 V or 1.8 V host by setting the IO_VDD_SEL config-
uration bit. The SPI mode supports 4-wire or 3-wire by setting the SPI_3WIRE configuration bit.
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Preliminary Rev. 0.9 | 21
Si5381/82 Data Sheet
Functional Description
3.9 Custom Factory Preprogrammed Devices
For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered
with a specific configuration written into NVM. A factory pre-programmed device will generate clocks at power-up. Custom, factory-pre-
programmed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly
and easily request and generate a custom part number for your configuration.
In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your
design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local
Silicon Labs sales representative. Samples of your pre-programmed device will ship to you typically within two weeks.
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Preliminary Rev. 0.9 | 22
Si5381/82 Data Sheet
Functional Description
3.10 How to Enable Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed
Devices
As with essentially all software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.silabs.com and
opting in for updates to software, you will be notified whenever changes are made and what the impact of those changes are. This
update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented in this data
sheet.
However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register
setting, but the feature or register setting is NOT yet available in CBPro, you must contact a Silicon Labs applications engineer for as-
sistance. Examples of this type of feature or custom setting are the customizable output amplitude and common voltages for the clock
outputs. After careful review of your project file and custom requirements, a Silicon Labs applications engineer will email back your
CBPro project file with your specific features and register settings enabled, using what is referred to as the manual "settings override"
feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in
a CBPro design report are shown below:
Table 3.4. Setting Overrides
Location
Customer Name
FORCE_HOLD_PLLA
OOF_DIV_CLK_DIS
Engineering Name
OLA_HO_FORCE
OOF_DIV_CLK_DIS
Type
No NVM
User
Target
N/A
Dec Value
Hex Value
0x1
0x0435[0]
0x0B48[0:4]
1
0
OPN and EVB
0x00
Once you receive the updated design file, simply open it in CBPro. After you create a custom OPN, the device will begin operation after
startup with the values in the NVM file, including the Silicon Labs-supplied override settings.
Place sample
Start
order
Do I need a
pre-programmed device
with a feature or setting
which is unavailable in
ClockBuilder Pro?
Generate
Custom OPN
in CBPro
Configure device
using CBPro
No
Yes
Contact Silicon Labs
Technical Support
to submit & review
your
Yes
non-standard
configuration
request & CBPro
project file
Receive
updated CBPro
project file
from
Silicon Labs
with “Settings
Override”
Does the updated
CBPro Project file
match your
Load project file
into CBPro and test
requirements?
Figure 3.17. Flowchart to Order Custom Parts with Features not Available in CBPro
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Preliminary Rev. 0.9 | 23
Si5381/82 Data Sheet
Register Map
4. Register Map
The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessed
registers, such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such as
frequency configuration and general device settings. Refer to the Si5381/82 Family Reference Manual for a complete list of register
descriptions and settings.
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Preliminary Rev. 0.9 | 24
Si5381/82 Data Sheet
Electrical Specifications
5. Electrical Specifications
Table 5.1. Recommended Operating Conditions
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
TA
Min
–40
—
Typ
25
Max
85
Unit
°C
°C
V
Ambient Temperature
Maximum Junction Temperature
TJMAX
VDD
—
125
1.89
3.47
3.47
2.62
1.89
1.71
3.14
3.14
2.38
1.71
1.80
3.30
3.30
2.50
1.80
Core Supply Voltage
VDDA
V
V
VDDO
Output Driver Supply Voltage
V
V
Note:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-
ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 5.2. DC Characteristics
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
IDD
Test Condition
Si5381
Min
—
Typ
175
120
Max
—
Unit
mA
mA
Core Supply Current
IDDA
Notes 1, 2
—
—
LVPECL Output3
@ 156.25 MHz
LVDS Output3
@ 156.25 MHz
3.3 V LVCMOS4
Output
—
—
21
15
25
18
mA
mA
—
—
21
16
25
18
mA
mA
IDDO
Output Buffer Supply Current
@ 156.25 MHz
2.5 V LVCMOS4
Output
@ 156.25 MHz
1.8 V LVCMOS4
Output
—
—
12
13
—
mA
@ 156.25 MHz
Note 1,5
Pd
Total Power Dissipation
1125
mW
silabs.com | Building a more connected world.
Preliminary Rev. 0.9 | 25
Si5381/82 Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Si5381 test configuration: 8 clock outputs enabled (2 x 983.04 MHz, 2 x 491.52 MHz, 1 x 245.76 MHz, 3 x 122.88 MHz; 2.5
LVDS). Excludes power in termination resistors.
2. VDDO0 supplies power to both OUT0 and OUT0A buffers. Similarly, VDDO9 supplies power to both OUT9 and OUT9A buffers.
3. Differential outputs terminated into an AC coupled 100 Ω load.
4. LVCMOS outputs measured into a 6-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV
= 3, which is the strongest driver setting.
5. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is
not available. All EVBs support detailed current measurements for any configuration.
LVCMOS Output Test Configuration
Differential Output Test Configuration
Trace length 5
inches
IDDO
0.1 uF
0.1 uF
56 Ω
0.1 uF
56 Ω
499 Ω
4.7 pF
50
IDDO
50 Ω Scope Input
50 Ω Scope Input
50
50
OUT
100
OUT
OUTb
OUTb
50
499 Ω
4.7 pF
0.1 uF
Table 5.3. Input Clock Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Standard Differential or Single-Ended/LVCMOS — AC-coupled (IN0, IN1, IN2, IN3)
fIN_DIFF
fIN_SE
Differential
0.008
0.008
100
—
—
—
—
750
250
Input Frequency Range
MHz
Single-ended/
LVCMOS
fIN_DIFF < 250 MHz
1800
1800
mVpp_se
mVpp_se
VIN_DIFF
Input Voltage Amplitude
Single-Ended Input Swing
250 MHz < fIN_DIFF
750 MHz
<
225
VIN_SE
fIN_SE< 250 MHz
100
400
40
—
—
—
2
3600
—
mVpp_se
V/µs
%
Slew Rate1, 2
Duty Cycle
SR
DC
CIN
60
Capacitance
—
—
pF
Pulsed CMOS — DC-coupled (IN0, IN1, IN2, IN3)3
fIN_CMOS
VIL
Input Frequency
0.008
–0.2
0.49
400
40
—
—
—
—
—
—
250
0.33
—
MHz
V
Input Voltage
VIH
V
Slew Rate1, 2
SR
DC
PW
—
V/µs
%
Duty Cycle
Clock Input
Pulse Input
60
Minimum Pulse Width
1.6
—
ns
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Preliminary Rev. 0.9 | 26
Si5381/82 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
RIN
Input Resistance
—
8
—
kΩ
REFCLK (Applied to XA/XB) (Grade A Only)
fIN_REF
fRANGE
VIN_SE
REFCLK
4G/LTE
—
54
—
—
—
—
MHz
ppm
Total Frequency Tolerance
-100
365
365
+100
2000
2500
mVpp_se
mVpp_diff
Input Voltage Swing
Slew Rate1, 2
VIN_DIFF
Imposed for phase
noise performance
SR
DC
400
40
—
—
—
V/µs
%
Input Duty Cycle
60
Integrated Crystal REFCLK (Grade E)
Crystal Frequency
fIN_XTAL
fSTABLE
fPERT
—
—
—
48.0231
TBD
—
—
MHz
ppm
ppm
10 years of aging
at 70 °C
Frequency Stability
Frequency Perturbation
—
TBD
Note:
1. Imposed for phase noise performance.
2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) * VIN_Vpp_se) / SR.
3. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks <1 MHz, which must be dc-coupled, having a
duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since the input
thresholds (VIL, VIH) of this buffer are non-standard, refer to the input attenuator circuit for dc-coupled Pulsed LVCMOS in the
Si5381/82 Family Reference Manual. Otherwise, for standard LVCMOS input clocks, use the “AC-coupled Singled-Ended” mode
as shown in Figure 3.6 Termination of Differential and LVCMOS Input Signals on page 12.
Table 5.4. Serial and Control Input Pin Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Serial and Control Input Pins (IN_SEL[1:0], RSTb, OEb, PDNb, I2C_SEL, A1/SDO, SCLK, A0/CSb, SDA/SDIO)
1
VIL
—
—
0.3 x VDDIO
V
Input Voltage Thresholds
1
VIH
CIN
IL
0.7 x VDDIO
—
2
—
—
—
—
V
Input Capacitance
Input Resistance
Minimum Pulse Width
Note:
—
—
pF
kΩ
ns
20
—
PW
RSTb, PDNb
100
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5381/82 Family Reference Manual for
more details on the register settings.
silabs.com | Building a more connected world.
Preliminary Rev. 0.9 | 27
Si5381/82 Data Sheet
Electrical Specifications
Table 5.5. Differential Clock Output Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Outputs connected to DSPLL_B
Outputs connected to DSPLL_A/C/D
fOUT < 400 MHz
Min
0.48
0.0001
48
Typ
—
Max
2949.12
735
52
Unit
MHz
MHz
%
fOUT
Output Frequency
—
—
400 MHz < fOUT < 800 MHz
800 MHz < fOUT < 1474.56 MHz
f > 1474.56 MHz
45
—
55
%
Duty Cycle
DC
40
—
60
%
35
—
65
Differential Outputs
—
20
50
ps
TSK
Output-Output Skew
OUT-OUTb Skew
Normal Mode
Differential Outputs
—
—
20
0
100
100
ps
ps
Measured from the positive to negative
output pins
TSK_OUT
VDDO = 3.3 V,
LVDS
350
660
470
810
550
2.5 V, or 1.8 V
Output Voltage Amplitude1
Common Mode Voltage 1,2
VOUT
mVpp_se
VDDO = 3.3 V,
LVPECL
2.5 V
1000
LVDS
VDDO = 3.3 V
1.10
1.90
1.15
1.25
2.05
1.25
1.35
2.15
1.35
LVPECL
VCM
V
V
DDO = 2.5 V
LVPECL, LVDS
sub-LVDS
VDDO = 1.8 V 5
0.87
—
0.93
170
1.00
240
Rise and Fall Times
(20% to 80%)
tR/tF
Normal Mode
ps
Ω
Differential Output Impe-
dance2
ZO
Normal Mode
—
100
—
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
—
—
—
—
—
–93
–93
–84
–79
–75
—
—
—
—
—
Power Supply Noise Rejection
Output-Output Crosstalk4
PSRR
dBc
dB
XTALK
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Preliminary Rev. 0.9 | 28
Si5381/82 Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output
driver can be programmed independently. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV)
higher than the TIA/EIA-644 maximum. Refer to the Si5381/82 Family Reference Manual for recommended output settings.
2. Not all combinations of voltage amplitude and common mode voltages settings are possible.
3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and
noise spur amplitude measured.
4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25
MHz. Refer to application note, http://www.silabs.com/Support%20Documents/TechnicalDocs/AN862.pdf, guidance on crosstalk
minimization. Note that all active outputs must be terminated when measuring crosstalk.
5. VDDO = 2.5 V or 3.3V required for fOUT > 1474.56 MHz.
OUTx
Vpp_se
Vpp_se
Vcm
Vcm
Vpp_diff = 2*Vpp_se
OUTxb
Table 5.6. LVCMOS Clock Output Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Outputs connected to DSPLL_B
Outputs connected to DSPLL_A/C/D
fOUT <100 MHz
Min
0.48
0.0001
47
Typ
—
Max
250
250
53
Unit
MHz
MHz
fOUT
Output Frequency
—
—
Duty Cycle
DC
%
100 MHz < fOUT < 250 MHz
44
—
55
LVCMOS, integer related from the same Multi-
Synth
TSK
Output-to-Output
—
—
100
ps
VDDO = 3.3 V
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOH = –10 mA
IOH = –12 mA
IOH = –17 mA
—
—
—
—
—
—
VDDO x
0.75
V
VDDO = 2.5 V
Output Voltage High1, 2, 3
VOH
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOH = –6 mA
IOH = –8 mA
IOH = –11 mA
—
—
—
—
—
—
VDDO x
0.75
V
V
VDDO = 1.8 V
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOH = –4 mA
IOH = –5 mA
—
—
—
—
VDDO x
0.75
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Preliminary Rev. 0.9 | 29
Si5381/82 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDDO = 3.3 V
IOL = 10 mA
OUTx_CMOS_DRV=1
—
—
—
—
—
—
VDDO x
0.15
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOL = 12 mA
IOL = 17 mA
V
VDDO = 2.5 V
Output Voltage Low1, 2, 3
VOL
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOL = 6 mA
IOL = 8 mA
IOL = 11 mA
—
—
—
—
—
—
VDDO x
0.15
V
V
VDDO = 1.8 V
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOL = 4 mA
IOL = 5 mA
—
—
—
—
—
—
VDDO x
0.15
—
VDDO = 3.3 V
420
475
525
550
625
705
ps
ps
ps
LVCMOS Rise and Fall
Times3
tr/tf
VDDO = 2.5 V
VDDO = 1.8 V
(20% to 80%)
Note:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the
Si5381/82 Family Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.
3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
AC Output Test Configuration
DC Test Configuration
Trace length 5 inches
0.1 uF
499 Ω
4.7 pF
IDDO
50
50
IOL/IOH
50 Ω Scope Input
50 Ω Scope Input
OUT
56 Ω
0.1 uF
Zs
OUTb
VOL/VOH
499 Ω
4.7 pF
56 Ω
Table 5.7. Output Serial and Status Pin Specifications
silabs.com | Building a more connected world.
Preliminary Rev. 0.9 | 30
Si5381/82 Data Sheet
Electrical Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Serial and Status Output Pins (INTRb, SDA/SDIO2, A1/SDO)
VDDIO1 x 0.75
—
—
—
—
V
V
VOH
VOL
IOH = –2 mA
IOL = 2 mA
Output Voltage
VDDIO1 x 0.15
Note:
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Users normally select this option in the Clock-
Builder Pro GUI. Alternatively, refer to the Si5381/82 Family Reference Manual for more details on register settings.
2. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused
with I2C_SEL pulled high internally. VOL remains valid in all cases.
Table 5.8. Performance Characteristics
(VDD = 1.8 V ±5%, or 3.3 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
PLL Loop Bandwidth
fBW
1
—
4000
Hz
Programming Range1
Time from power-up or de-as-
sertion of PDNb to when the
device generates free-running
clocks
tSTART
Initial Start-Up Time
—
—
385
500
—
ms
ms
Fastlock enabled,
fIN = 19.44 MHz2
tACQ
PLL Lock Time
600
POR to Serial Interface Ready3
Jitter Peaking
tRDY
JPK
—
—
—
—
15
ms
dB
25 MHz input, 25 MHz output,
loop bandwidth of 4 Hz
0.1
Compliant with G.8262 Op-
tions 1&2
Carrier Frequency = 10.3125
GHz
JTOL
Jitter Tolerance
—
3180
—
UI pk-pk
Jitter Modulation Frequency =
10 Hz
Only valid for a single auto-
matic switch between two in-
put clocks at the same fre-
quency.
—
—
—
—
2.0
1.3
ns
ns
Maximum Phase Transient
During a Hitless Switch
tSWITCH
Only valid for a single manual
switch between two input
clocks at the same frequency.
ωP
tIODELAY
tZDELAY
Pull-in Range
–20
—
—
—
+20
1.8
—
ppm
ns
Through a given DSPLL, for
DSPLLs A/C/D only.
4
Input-to-Output Delay Variation
—
110
ps
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Preliminary Rev. 0.9 | 31
Si5381/82 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DSPLL_B, 12 kHz to 20 MHz
—
85
—
fs RMS
5
RMS Jitter Generation6
JGEN
DSPLL_A/C/D,
—
150
—
fs RMS
12 kHz to 20 MHz
10 Hz
100 Hz
—
—
—
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-103
-95
—
—
—
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
1 kHz
Phase Noise Performance (122.88
MHz Carrier Frequency)
PN
10 kHz
100 kHz
1 MHz
10 MHz
Up to 1 MHz offset
From 1 MHz to 30 MHz offset
Spur Performance (122.88 MHz Carri-
er Frequency)
SPUR
dBc
Note:
1. Actual loop bandwidth may be lower; please refer to CBPro for actual value on your frequency plan.
2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock
time was measured with nominal and fastlock bandwidths, both set to 100 Hz, LOL set/clear thresholds of 3/0.3 ppm respectively,
using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first
rising edge of the clock reference and the LOL indicator de-assertion.
3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands.
4. Measured between a common 2 MHz input and 2 MHz output with different N-dividers on the same unit and a loop bandwidth of
4 kHz. These output frequencies are generated using non-production engineering modes only for test.
5. Delay between reference and feedback input both clocks at 10 MHz and same slew rate. Ref clock rise time must be <200 ps.
These output frequencies are generated using non-production engineering modes only for test.
6. Jitter generation test conditions: fIN = 30.72 MHz, 3.3V LVPECL, DSPLL LBW = 100 Hz. Jitter integrated from 12 kHz to 20 MHz
offset. Does not include jitter from PLL input reference.
Table 5.9. I2C Timing Specifications (SCL,SDA)
Parameter
Symbol
Test Condition
Min
Max
Min
Fast Mode
400 kbps
Max
Unit
Standard Mode
100 kbps
fSCL
—
SCL Clock Frequency
SMBus Timeout
—
100
—
400
35
kHz
ms
When Timeout is Enabled
25
35
—
25
Hold Time (Repeated)
START Condition
tHD:STA
4.0
4.7
4.0
4.7
0.6
—
—
—
—
µs
µs
µs
µs
Low Period of the SCL
Clock
tLOW
—
—
—
1.3
0.6
0.6
HIGH Period of the SCL
Clock
tHIGH
Set-up Time for a Repea-
ted START Condition
tSU:STA
tHD:DAT
tSU:DAT
Data Hold Time
100
250
—
—
100
100
—
—
ns
ns
Data Set-up Time
silabs.com | Building a more connected world.
Preliminary Rev. 0.9 | 32
Si5381/82 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Max
Min
Max
Unit
Rise Time of Both SDA
and SCL Signals
tr
—
1000
20
300
ns
Fall Time of Both SDA and
SCL Signals
tf
—
300
—
—
300
—
ns
µs
Set-up Time for STOP
Condition
tSU:STO
4.0
0.6
Bus Free Time between a
STOP and START Condi-
tion
tBUF
4.7
—
1.3
—
µs
tVD:DAT
tVD:ACK
Data Valid Time
—
—
3.45
3.45
—
—
0.9
0.9
µs
µs
Data Valid Acknowledge
Time
Figure 5.1. I2C Serial Port Timing Standard and Fast Modes
Table 5.10. SPI Timing Specifications (4-Wire)
Parameter
Symbol
fSPI
Min
—
Typ
—
Max
20
Unit
MHz
%
SCLK Frequency
SCLK Duty Cycle
SCLK Period
TDC
40
—
60
TC
50
—
—
ns
Delay Time, SCLK Fall to SDO
Active
TD1
TD2
TD3
—
—
—
—
—
—
18
15
15
ns
ns
ns
Delay Time, SCLK Fall to SDO
Delay Time, CSb Rise to SDO
Tri-State
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Preliminary Rev. 0.9 | 33
Si5381/82 Data Sheet
Electrical Specifications
Parameter
Symbol
TSU1
TH1
Min
5
Typ
—
Max
—
Unit
ns
Setup Time, CSb to SCLK
Hold Time, SCLK Fall to CSb
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
5
—
—
ns
TSU2
TH2
5
—
—
ns
5
—
—
ns
Delay Time Between Chip Selects
(CSb)
TCS
Tc
2
—
—
TD1
TC
TSU1
SCLK
TH1
CSb
TSU2
TH2
TCS
SDI
TD2
TD3
SDO
Figure 5.2. 4-Wire SPI Serial Interface Timing
Table 5.11. SPI Timing Specifications (3-Wire)
Parameter
Symbol
fSPI
Min
—
40
50
—
—
—
5
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
20
60
—
Unit
MHz
%
SCLK Frequency
TDC
TC
SCLK Duty Cycle
SCLK Period
ns
TD1
Delay Time, SCLK Fall to SDIO Turn-on
Delay Time, SCLK Fall to SDIO Next-bit
Delay Time, CSb Rise to SDIO Tri-State
Setup Time, CSb to SCLK
Hold Time, SCLK Fall to CSb
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CSb)
20
15
15
—
ns
TD2
ns
TD3
ns
TSU1
TH1
TSU2
TH2
ns
5
—
ns
5
—
ns
5
—
ns
TCS
Tc
2
—
silabs.com | Building a more connected world.
Preliminary Rev. 0.9 | 34
Si5381/82 Data Sheet
Electrical Specifications
TSU1
TC
SCLK
TH1
TD1
TD2
CSb
TSU2
TH2
TCS
SDIO
TD3
Figure 5.3. 3-Wire SPI Serial Interface Timing
Table 5.12. External Crystal Specifications (Grade A Only)
Parameter
Symbol
fXTAL
fRANGE
CL
Test Condition
Min
—
Typ
54
—
8
Max
—
Unit
MHz
ppm
pF
Internal Crystal Frequency1
Total Frequency Tolerance2
Load Capacitance
–100
—
+100
—
CO
Crystal Output Capacitance
Crystal Drive Level
—
—
—
—
2
pF
dL
—
300
23
µW
Ω
RESR
Equivalent Series Resistance
Note:
—
1. The Si5381/82 is designed to work with crystals that meet the frequencies and specifications in Table 12.
2. Includes initial tolerance, drift after reflow, change over temperature (–40 °C to +85 °C), VDD variation, load pulling and aging.
Table 5.13. Thermal Characteristics (Grade A, QFN-64)
Test Condition1
Still Air
Parameter
Symbol
Value
22
Unit
Thermal Resistance
Junction to Ambient
θJA
Air Flow 1 m/s
Air Flow 2 m/s
19.4
18.3
Thermal Resistance
Junction to Case
Thermal Resistance
Junction to Board
Thermal Resistance
Junction to Top Center
Note:
θJC
9.5
°C/W
θJB
9.4
9.3
ΨJB
ΨJT
0.2
1. Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via under GNP pad: 36, Number of Cu Layers: 4
silabs.com | Building a more connected world.
Preliminary Rev. 0.9 | 35
Si5381/82 Data Sheet
Electrical Specifications
Table 5.14. Thermal Characteristics (Grade E, LGA-64)
Test Condition1
Still Air
Parameter
Symbol
Value
TBD
TBD
TBD
Unit
Thermal Resistance
Junction to Ambient
θJA
Air Flow 1 m/s
Air Flow 2 m/s
Thermal Resistance
Junction to Case
Thermal Resistance
Junction to Board
Thermal Resistance
Junction to Top Center
Note:
θJC
TBD
°C/W
θJB
v
ΨJB
TBD
ΨJT
TBD
1. Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via under GNP pad: 36, Number of Cu Layers: 4
Table 5.15. Absolute Maximum Ratings1, 2, 3
Parameter
Symbol
VDD
Test Condition
Value
Unit
V
–0.5 to 3.8
–0.5 to 3.8
–0.5 to 3.8
–0.85 to 3.8
DC Supply Voltage
VDDA
VDDO
VI1
V
V
IN0 – IN3
V
IN_SEL[1:0], RSTb, PDNb,
OEb, I2C_SEL,
Input Voltage Range
VI2
–0.5 to 3.8
–0.5 to 2.7
V
V
SDA/SDIO, A1/SDO, SCLK,
A0/CSb
VI3
LU
XA/XB (Grade A only)
Latch-up Tolerance
JESD78 Compliant
ESD Tolerance
HBM
TJCT
TSTG
100 pF, 1.5 kΩ
2.0
kV
°C
°C
Junction Temperature
Storage Temperature Range
Soldering Temperature
–55 to 125
–55 to 150
TPEAK
260
°C
(Pb-free profile)3
Soldering Temperature Time at TPEAK(Pb-
free profile)4
TP
20–40
sec
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Preliminary Rev. 0.9 | 36
Si5381/82 Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Value
Unit
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
2. 64-QFN is RoHS-6 compliant.
3. For detailed MSL and packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.
4. The device is compliant with JEDEC J-STD-020.
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Preliminary Rev. 0.9 | 37
Si5381/82 Data Sheet
Typical Application Diagram
6. Typical Application Diagram
DCO control
via SPI / I2C
SysClk
PHY1
PHY2
Si5381/
Si5382
RX1
TX1
PCIe
SerDes
RFFE
RFFE
RF
JESD204B
Transceiver
RX2
TX2
DFE
ASIC/
FPGA
Baseband
Processor
RX1
TX1
RFFE
RFFE
RF
JESD204B
Transceiver
RX2
TX2
Figure 6.1. Si5381/82 Typical Application
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Preliminary Rev. 0.9 | 38
Si5381/82 Data Sheet
Detailed Block Diagram
7. Detailed Block Diagram
3
XTAL
Si5381/82
OSC
VDDO0
Si5381
IN_SEL[1:0]
OUT0A
OUT0Ab
÷R0A
÷R0
Si5382
OUT0
OUT0b
PD LPF
Mn_A
VDDO1
OUT1
OUT1b
÷
Md_A
÷R1
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
÷R8
DSPLL A
VDDO2
OUT2
OUT2b
IN0
÷P0
÷P1
IN0b
PD LPF
÷N1
÷N4
VDDO3
OUT3
OUT3b
Mn_B
Md_B
÷5
IN1
÷
DSPLL B
IN1b
VDDO4
OUT4
OUT4b
IN2
÷P2
÷P3
IN2b
PD LPF
Mn_C
VDDO5
OUT5
OUT5b
IN3/FB_IN
÷
IN3b/FB_INb
Md_C
DSPLL C
VDDO6
OUT6
OUT6b
VDDO7
OUT7
OUT7b
PD LPF
Mn_D
÷
Md_D
VDDO8
OUT8
OUT8b
DSPLL D
I2C_SEL
OUT9
OUT9b
SDA/SDIO
÷R9
SPI/
NVM
I2C
OUT9A
OUT9Ab
SCLK
÷R9A
A0/CSb
VDDO9
Status
Monitors
INTRb
Figure 7.1. Si5381/82 Block Diagram (Grade E Shown)
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Preliminary Rev. 0.9 | 39
Si5381/82 Data Sheet
Typical Operating Characteristics (Phase Noise and Jitter)
8. Typical Operating Characteristics (Phase Noise and Jitter)
Figure 8.1. Typical Phase Noise (156.25 MHz)
Figure 8.2. Typical Phase Noise (245.76 MHz)
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Preliminary Rev. 0.9 | 40
Si5381/82 Data Sheet
Pin Descriptions
9. Pin Descriptions
Top View (Grade A)
Top View (Grade E)
48
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IN1
IN1b
1
2
IN1
IN1b
SYNCb
SYNCb
LOLb
47
LOLb
46
3
3
IN_SEL0
IN_SEL1
PDNb
VDD18
IN_SEL0
IN_SEL1
PDNb
RSTb
X1
VDD18
OUT6
45
4
OUT6
4
44
5
OUT6b
5
OUT6b
VDDO6
OUT5
43
6
RSTb
VDDO6
6
42
7
RSVD
RSVD
RSVD
RSVD
OEb
OUT5
7
41
40
39
38
37
36
35
34
33
8
OUT5b
VDDO5
I2C_SEL
OUT4
8
OUT5b
VDDO5
I2C_SEL
OUT4
GND
Pad
XA
GND
Pad
9
9
XB
10
11
10
11
X2
OEb
INTRb 12
OUT4b
VDDO4
OUT3
INTRb 12
OUT4b
VDDO4
OUT3
13
14
15
16
VDD33
IN2
13
14
15
16
VDD33
IN2
IN2b
OUT3b
VDDO3
IN2b
OUT3b
VDDO3
SCLK
SCLK
Figure 9.1. Si5381/82 64-QFN Top View
Table 9.1. Pin Descriptions
Pin Type1
Pin Name
Pin Number
Function
XA
8
I
Crystal Input (Grade A Only)
Input pin for external crystal (XTAL). Alternatively
these pins can be driven with an external refer-
ence clock (REFCLK). An internal register bit se-
lects XTAL or REFCLK mode. Default is XTAL
mode. Single-ended inputs must be connected to
the XA pin, with the XB pin appropriately termina-
ted. For Grade E (integrated crystal) these pins
are reserved and should be left unconnected).
XB
9
I
X1
X2
7
I
I
XTAL Shield (Grade A Only)
Connect these pins directly to the crystal ground
pins. Both the X1/X2 pins and Crystal ground pins
should be separated from the PCB ground plane.
Refer to the Si5381/82 Family Reference Manual
for layout guidelines. For Grade E (integrated
crystal) these pins are reserved and should be
left unconnected).
10
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Preliminary Rev. 0.9 | 41
Si5381/82 Data Sheet
Pin Descriptions
Pin Type1
Pin Name
IN0
Pin Number
Function
63
64
1
I
I
I
I
I
I
I
I
Clock Inputs.
IN0b
IN1
These pins accept an input clock for synchronizing
the device. They support both differential and sin-
gle-ended clock signals. Refer to section 3.3.1 In-
put Configuration and Terminations for input termi-
nation options. These pins are high-impedance
and must be terminated externally, when being
used. The negative side of the differential input
must be ac-grounded when accepting a single-
ended clock. Unused inputs may be left unconnec-
ted.
IN1b
IN2
2
14
15
61
62
IN2b
IN3
IN3b
Outputs
OUT0A
OUT0Ab
OUT0
21
20
24
23
28
27
31
30
35
34
38
37
42
41
45
44
51
50
54
53
56
55
59
58
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
OUT0b
OUT1
OUT1b
OUT2
OUT2b
OUT3
OUT3b
OUT4
Output Clocks.
These output clocks support programmable signal
amplitude and common mode voltage. Desired
output signal format is configurable using register
control. Termination recommendations are provi-
ded in the sections, and 3.5.5 LVCMOS Output
Terminations. Unused outputs should be left un-
connected.
OUT4b
OUT5
OUT5b
OUT6
OUT6b
OUT7
OUT7b
OUT8
OUT8b
OUT9
OUT9b
OUT9A
OUT9Ab
Serial Interface
I2C Select.
This pin selects the serial interface mode as I2C
(I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is
internally pulled high.
I2C_SEL
39
I
silabs.com | Building a more connected world.
Preliminary Rev. 0.9 | 42
Si5381/82 Data Sheet
Pin Descriptions
Pin Type1
Pin Name
Pin Number
Function
Serial Data Interface.
This is the bidirectional data pin (SDA) for the I2C
mode, the bidirectional data pin (SDIO) in the 3-
wire SPI mode, or the input data pin (SDI) in 4-
wire SPI mode. When in I2C mode or unused, this
pin must be pulled-up using an external resistor of
at least 1 kΩ. No pull-up resistor is needed when
in SPI mode. This pin is 3.3 V tolerant.
SDA/SDIO
18
I/O
Address Select 1/Serial Data Output.
In I2C mode this pin functions as the A1 address
input pin. In 4-wire SPI mode, this is the serial da-
ta output (SDO) pin. This pin is 3.3 V tolerant. This
pin must be pulled-up externally when unused.
A1/SDO
SCLK
17
16
19
I/O
Serial Clock Input.
This pin functions as the serial clock input for both
I2C and SPI modes. When in I2C mode or unused,
this pin must be pulled-up using an external resis-
tor of at least 1 kΩ. No pull-up resistor is needed
when in SPI mode. This pin is 3.3 V tolerant.
I
I
Address Select 0/Chip Select.
This pin functions as the hardware controlled ad-
dress A0 in I2C mode. In SPI mode, this pin func-
tions as the chip select input (active low). This pin
is internally pulled-up. This pin is 3.3 V tolerant.
A0/CSb
Control/Status
Interrupt. 2
This pin is asserted low when a change in device
status has occurred. This pin must be pulled-up
externally using a resistor of at least 1 kΩ. It
should be left unconnected when not in use.
INTRb
PDNb
12
5
O
Power Down. 2
The device enters into a low power mode when
this pin is pulled low. This pin is internally pulled-
up. This pin is 3.3 V tolerant. It can be left uncon-
nected when not in use.
I
Device Reset. 2
Active low input that performs power-on reset
(POR) of the device. Resets all internal logic to a
known state and forces the device registers to
their default values. Clock outputs are disabled
during reset. This pin is internally pulled-up. This
pin is 3.3 V tolerant.
RSTb
6
I
I
Output Enable. 2
This pin disables all outputs when held high. This
pin is internally pulled low and can be left uncon-
nected when not in use. This pin is 3.3 V tolerant.
OEb
11
Reserved.
Leave disconnected.
RSVD
47, 48
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Preliminary Rev. 0.9 | 43
Si5381/82 Data Sheet
Pin Descriptions
Pin Type1
Pin Name
Pin Number
Function
Input Reference Select. 2
IN_SEL0
3
I
The IN_SEL[1:0] pins are used in manual pin con-
trolled mode to select the active clock input as
shown in Table 3.2 Manual Input Selection Using
IN_SEL[1:0] Pins on page 12. These pins are in-
ternally pulled-down and may be left unconnected
when unused.
IN_SEL1
RSVD
4
I
Reserved.
Leave disconnected.
7, 8, 9, 10, 25
Power
VDD
VDD
VDD
32
46
60
P
P
P
Core Supply Voltage.
The device operates from a 1.8 V supply. A 1 uF
bypass capacitor should be placed very close to
each pin.
Core Supply Voltage 3.3 V.
This core supply pin requires a 3.3 V power
source. A 1 uF bypass capacitor should be placed
very close to this pin.
VDDA
13
P
VDDO0
VDDO1
VDDO2
VDDO3
VDDO4
VDDO5
VDDO6
VDDO7
VDDO8
VDDO9
22
26
29
33
36
40
43
49
52
57
P
P
P
P
P
P
P
P
P
P
Output Clock Supply Voltage. Supply voltage
(3.3 V, 2.5 V, 1.8 V) for OUTx, OUTxb Outputs.
Note that VDDO0 supplies power to OUT0 and
OUT0A; VDDO9 supplies power to OUT9 and
OUT9A. Leave VDDO pins of unused output driv-
ers unconnected. An alternative option is to con-
nect the VDDO pin to a power supply and disable
the output driver to minimize current consumption.
A 1 µF bypass capacitor should be placed very
close to each connected VDDO pin.
Ground Pad.
GND PAD
P
This pad provides connection to ground and must
be connected for proper operation.
Note:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
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Preliminary Rev. 0.9 | 44
Si5381/82 Data Sheet
Packages
10. Packages
10.1 64-LGA Package
Figure 10.1. Si5381/82 9x9 mm 64-LGA Package Diagram
Table 10.1. Package Dimensions
Dimension
Min
Nom
1.10
Max
A
1.00
1.30
A1
0.26 REF
0.25
b
0.20
5.40
0.30
5.60
D
9.00 BSC
5.50
D2
e
0.50 BSC
9.00 BSC
5.50
E
E2
5.40
0.35
0.03
—
5.60
0.45
0.13
0.10
0.10
0.15
0.05
0.10
0.08
L
0.363
0.08
L1
aaa
—
bbb
—
—
ccc
—
—
ddd
—
—
ddd
eee
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.9 | 45
Si5381/82 Data Sheet
Packages
10.2 64-QFN Package
Figure 10.2. Si5381/82 9x9 mm 64-QFN Package Diagram
Table 10.2. Package Diagram Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
A
A1
0.02
b
0.25
D
9.00 BSC
5.20
D2
5.10
5.30
e
0.50 BSC
9.00 BSC
5.20
E
E2
5.10
0.30
—
5.30
0.50
0.15
0.10
0.08
0.10
L
0.40
aaa
—
bbb
—
—
ccc
—
—
ddd
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.9 | 46
Si5381/82 Data Sheet
PCB Land Pattern
11. PCB Land Pattern
Figure 11.1. 9x9 mm 64-QFN Land Pattern
Table 11.1. PCB Land Pattern Dimensions
Dimension
Max
8.60
8.60
0.50
0.30
0.50
5.50
5.50
C1
C2
E
X1
Y1
X2
Y2
General
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication
Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 2x2 array of 0.65 mm square openings on a 0.90 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.9 | 47
Si5381/82 Data Sheet
Top Marking
12. Top Marking
Si5381g-
Si5382g-
Rxxxxx-GM
Rxxxxx-GM
YYWWTTTTTT
YYWWTTTTTT
e4
e4
TW
TW
Figure 12.1. Si5381/82 Top Marking
Table 12.1. Top Marking Explanation
Line
Characters
Si5381g
Description
Line 1
g = Grade (internal versus external crystal oscillator option)
Si5381A = Grade A, 4-DSPLL wireless clock with external XO/Crystal
Si5381E = Grade E, 4-DSPLL wireless clock with internal crystal oscillator
Si5382A = Grade A, 2-DSPLL wireless clock with external XO/Crystal
Si5382E = Grade E, 2-DSPLL wireless clock with internal crystal oscillator
R = Product revision. (See 2. Ordering Guide for current ordering revision).
Si5382g
Line 2
Rxxxxx-GM
xxxxx = Customer specific NVM sequence number. Optional NVM code as-
signed for custom, factory pre-programmed devices.
Characters are not included for standard, factory default configured devices.
See Ordering Guide for more information.
-GM = Package (QFN) type and temperature range (–40 to +85 °C).
Line 3
Line 4
YYWWTTTTTT
YYWW = Characters correspond to the year (YY) and work week (WW) of
package assembly.
TTTTTT = Manufacturing trace code.
Circle w/ 1.6 mm diame- Pin 1 indicator; left-justified
ter
e4
Pb-free symbol; Center-Justified
TW
TW = Taiwan; Country of Origin (ISO Abbreviation)
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Preliminary Rev. 0.9 | 48
Si5381/82 Data Sheet
Device Errata
13. Device Errata
Please log in or register at www.silabs.com to access the device errata document.
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Preliminary Rev. 0.9 | 49
Si5381/82 Data Sheet
Revision History
14. Revision History
14.1 Revision 0.9
September 25, 2017
• Initial Public Release.
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Preliminary Rev. 0.9 | 50
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