STK14CC8-RF25 [SIMTEK]
Non-Volatile SRAM, 512KX8, 25ns, CMOS, PDSO48, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SSOP-48;
| 型号： | STK14CC8-RF25 |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | Non-Volatile SRAM, 512KX8, 25ns, CMOS, PDSO48, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SSOP-48 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK14CC8
512K x 8 AutoStoreTM nvSRAM
QuantumTrapTM CMOS
Nonvolatile Static RAM
Advanced Information
FEATURES
DESCRIPTION
• 25ns Time
The Simtek STK14CC8 is a fast static RAM with a
nonvolatile element in each memory cell. The
embedded nonvolatile elements incorporate
• “Hands-off” Automatic STORE on Power Down
with only a small capacitor
Simtek’s QuantumTrapTM technology producing the
world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles,
while independent, nonvolatile data resides in the
highly reliable QuantumTrapTM cell. Data transfers
from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at
power down. On power up, data is restored to the
SRAM (the RECALL operation) from the nonvolatile
memory. Both the STORE and RECALL operations
are also available under software control.
• STORE to QuantumTrap™ Nonvolatile
Elements is Initiated by Software , device pin
or AutoStore™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Up
• Unlimited READ, WRITE and RECALL Cycles
• 10mA Typical ICC at 200ns Cycle Time
• 500,000 STORE Cycles to QuantumTrap™
• 100-Year Data Retention to QuantumTrap™
• Single 3V +20%, -10% Operation
• Commercial and Industrial Temperatures
• SSOP package
• RoHS Compliance
BLOCK DIAGRAM
VCC
VCAP
Quantum Trap
2048 X 2048
A8
A9
POWER
A10
A11
A12
A13
A14
A15
A16
A17
A18
CONTROL
STORE
RECALL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
2048 X 2048
HSB
SOFTWARE
DETECT
A18 – A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A5 A6 A7
G
E
W
Figure 1. Block Diagram
September 2005
1
Document Control #ML0034 rev 0.0
STK14CC8
PACKAGES
VCAP
A16
A14
1
2
3
4
5
6
VCC
A15
HSB
48
47
46
45
44
43
A12
A7
A6
W
A13
A8
A5
7
8
9
10
11
12
13
14
15
16
A9
42
41
40
39
38
37
36
35
34
33
A4
A11
A18
A17
VSS
VSS
DQ0
A3
A2
A1
A0
DQ6
G
A10
E
DQ7
17
18
32
31
30
29
28
27
26
25
19
20
21
22
23
24
DQ1
DQ2
DQ5
DQ4
DQ3
VCC
48 Pin SSOP
Relative PCB area usage.
See website for detailed
package size specifications.
PIN DESCRIPTIONS
Pin Name
I/O
Description
A18 – A0
Input
Address: The 19 address inputs select one of 524,288 bytes in the nvSRAM array.
Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
DQ7 –DQ0
E
I/O
Input
Chip Enable: The active low
Write Enable: The active low
E
input selects the device.
W
enables data on the DQ pins to be written to the address location latched by
W
Input
the falling edge of E
.
Output Enable: The active low
G
input enables the data output buffers during read cycles. De-asserting G
G
Input
high causes the DQ pins to tri-state.
VCC
Power Supply
Power 3.0V +20%, -10%
Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external
HSB
I/O
to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not
connected. (Connection Optional)
Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile
VCAP
Power Supply
elements.
VSS
Power Supply
No Connect
Ground
(Blank)
Unlabeled pins have no internal connection.
September 2005
2
Document Control #ML0034 rev 0.0
STK14CC8
ABSOLUTE MAXIMUM RATINGSa
Notes
-0.5V to +4.1V
Power Supply Voltage
Voltage on Input Relative to VSS
Voltage on Outputs
a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
-0.5V to (VCC + 0.5V)
-0.5V to (VCC + 0.5V)
–55°C to 125°C
–55°C to 140°C
–65°C to 150°C
1W
Temperature under Bias
Junction Temperature
Storage Temperature
Power Dissipation
DC Output Current (1 output at a time, 1s duration)
15mA
Package Thermal Characteristics see website: http://www.simtek.com/
DC CHARACTERISTICS
Commercial
Industrial
Symbol
Parameter
Units
mA
mA
mA
Notes
MIN
MAX
45
35
30
MIN
MAX
50
40
35
tAVAV = 25ns
tAVAV = 35ns
tAVAV = 45ns
Average VCC Current
ICC1
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care, VCC = max
Average current for duration of STORE
cycle (tSTORE).
Average VCC Current during STORE
Average VCC Current at tAVAV = 200ns
3V, 25°C, Typical
ICC2
ICC3
ICC4
ISB
2
2
mA
W
≥ (VCC – 0.2V)
All Others Inputs Cycling, at CMOS Levels.
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care
Average current for duration of STORE
cycle (tSTORE).
10
2
10
2
mA
mA
Average VCAP Current during
AutoStore™ Cycle
VCC Standby Current
E
≥ (VCC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
Standby current level after nonvolatile
cycle is complete.
(Standby, Stable CMOS Input Levels)
3
3
mA
µA
VCC = max
Input Leakage Current
IILK
±1
±1
±1
VIN = VSS to VCC
VCC = max
Off-State Output Leakage Current
IOLK
VIN = VSS to VCC, E or G ≥ VIH
±1
VCC + 0.3
0.8
µA
V
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
VIH
VIL
2.0
V
CC + 0.3
0.8
2.0
VSS – 0.5
2.4
All Inputs
All Inputs
V
SS – 0.5
2.4
V
VOH
VOL
TA
V
IOUT = –2mA
0.4
70
0.4
85
V
IOUT = 4mA
0
–40
2.7
44
oC
VCC
VCAP
2.7
44
3.6
100
3.6
100
V
3.0V +20%, -10%
Between Vcap pin and Vss, 5V rated.
Storage Capacitor
µF
September 2005
3
Document Control #ML0034 rev 0.0
STK14CC8
AC TEST CONDITIONS
0V to 3V
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
≤ 5ns
1.5V
Output Load
See Figure 2 and Figure 3
CAPACITANCEb
(TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX
UNITS
pF
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
CIN
Input Capacitance
Output Capacitance
7
7
COUT
pF
Notes
b: These parameters are guaranteed but not tested
3.0V
3.0V
577 Ohms
577 Ohms
OUTPUT
OUTPUT
5 pF
30 pF
INCLUDING
SCOPE AND
FIXTURE
789 Ohms
789 Ohms
INCLUDING
SCOPE AND
FIXTURE
Figure 2. AC Output Loading
Figure 3. AC Output Loading,
for tristate specs (
tHZ, tLZ, tWLQZ, tWHQZ
tGLQX, tGHQZ
,
)
September 2005
4
Document Control #ML0034 rev 0.0
STK14CC8
SRAM READ CYCLES #1 & #2
SYMBOLS
STK14CC8-25
NO.
PARAMETER
UNITS
#1
#2
Alt.
tACS
MIN
MAX
tELQV
1
2
Chip Enable Access Time
Read Cycle Time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c
c
tAVAV
tAVAV
tRC
tAA
tOE
tOH
tLZ
25
d
tAVQV
3
Address Access Time
25
12
tGLQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
d
tAXQX
5
3
3
tELQX
tEHQZ
tGLQX
6
e
tHZ
tOLZ
tOHZ
tPA
tPS
7
10
10
25
8
0
0
e
tGHQZ
9
b
tELICC
10
b
tEHICC
11
Notes
c:
W
must be high during SRAM READ cycles
and
d: Device is continuously selected with
E
G
both low
e: Measured ± 200mV from steady state output voltage
f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
2
tAVAV
ADDRESS
3
tAVQV
5
tAXQX
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2: E Controlledc,f
2
tAVAV
ADDRESS
1
tELQV
11
tEHICCL
6
tELQX
E
7
tEHQZ
G
9
tGHQZ
4
tGLQV
8
tGLQX
DQ (DATA OUT)
DATA VALID
10
tELICCH
ACTIVE
STANDBY
ICC
September 2005
5
Document Control #ML0034 rev 0.0
STK14CC8
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
STK14CC8-25 UNITS
PARAMETER
#1
#2
Alt.
tWC
tWP
tCW
tDW
tDH
MIN
25
20
20
10
0
MAX
Write Cycle Time
12
13
14
15
16
17
18
19
20
21
tAVAV
tWLWH
tELWH
tDVWH
tWHDX
tAVWH
tAVWL
tWHAX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
tAW
tAS
20
0
tWR
tWZ
tOW
0
e,g
tWLQZ
10
tWHQX
3
Notes
g: If
h:
W
is low when E goes low, the outputs remain in the high-impedance state.
E
or
W
must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledh,f
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
13
tWLWH
tAVWL
W
15
16
tDVWH
tWHDX
DATA VALID
DATA IN
20
tWLQZ
21
tWHQX
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
SRAM WRITE CYCLE #2: E Controlledh,f
12
tAVAV
ADDRESS
September 2005
6
Document Control #ML0034 rev 0.0
STK14CC8
AutoStore™ /POWER-UP RECALL
SYMBOLS
NO.
PARAMETER
STK14CC8
UNITS
NOTES
Standard
Alternate
MIN
MAX
22
23
24
25
tHRECALL
20
ms
ms
V
i
Power-up RECALL Duration
tSTORE
tHLHZ
12.5
2.65
j,k
STORE Cycle Duration
VSWITCH
tVCCRISE
2.55
150
Low Voltage Trigger Level
µs
V
CC Rise Time
Notes
i: tHRECALL starts from the time VCC rises above VSWITCH
j: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
k: Industrial Grade Devices require 15ms MAX.
STORE occurs only if a
SRAM write has
happened.
No STORE occurs
without at least one
SRAM write.
AutoStore™/POWER-UP RECALL
VCC
24
VSWITCH
25
tVCCRISE
AutoStoreTM
23
tSTORE
23
tSTORE
POWER-UP RECALL
22
tHRECALL
22
tHRECALL
Read & Write Inhibited
POWER DOWN
BROWN OUT
POWER-UP
RECALL
POWER-UP
RECALL
AutoStoreTM
AutoStoreTM
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH
September 2005
7
Document Control #ML0034 rev 0.0
STK14CC8
SOFTWARE-CONTROLLED STORE/RECALL CYCLEl,m
SYMBOLS
STK14CC8-25
NO.
PARAMETER
UNITS
NOTES
m
E
G
Alt.
tRC
MIN
MAX
cont
cont
26
27
tAVAV
tAVAV
25
0
ns
ns
ns
ns
µs
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
tAVEL
tAVGL
tAS
28
tELEH
tELAX
tGLGH
tGLAX
tCW
20
20
29
Address Hold Time
30
tRECALL
tRECALL
50
RECALL Duration
Notes
l: The software sequence is clocked with
E
controlled READs or G controlled READs.
m: The six consecutive addresses must be read in the order listed in the Mode Selection Table.
W
must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledm
26
tAVAV
26
tAVAV
ADDRESS #1
ADDRESS #6
ADDRESS
E
27
tAVEL
28
tELEH
29
tELAX
G
23
30
/
tSTORE tRECALL
HIGH IMPEDENCE
DATA VALID
DATA VALID
DQ (DATA)
SOFTWARE STORE/RECALL CYCLE: G Controlledm
26
26
tAVAV
tAVAV
ADDRESS #1
ADDRESS #6
ADDRESS
E
28
tGLGH
27
tAVGL
G
30
tRECALL
23
tSTORE
/
29
tGLAX
HIGH IMPEDENCE
DATA VALID
DATA VALID
DQ (DATA)
September 2005
8
Document Control #ML0000 0.0
STK14CC8
HARDWARE STORE CYCLE
SYMBOLS
NO.
STK14CC8
PARAMETER
UNITS
NOTES
Standard
tDELAY
tHLHX
tHLBL
Alternate
MIN
MAX
tHLQZ
31
32
33
Time Allowed to Complete SRAM Cycle
Hardware STORE Pulse Width
1
µs
ns
ns
p
15
Hardware STORE Low to STORE Busy
300
Notes
n: Read and Write cycles in progress before HSB is asserted are given this amount of time to complete.
HARDWARE STORE CYCLE
32
tHLHX
HSB (IN)
23
tSTORE
33
tHLBL
HSB (OUT)
HIGH IMPEDENCE
DATA VALID
HIGH IMPEDENCE
31
tDELAY
DQ (DATA OUT)
DATA VALID
September 2005
9
Document Control #ML0034 rev 0.0
STK14CC8
ORDERING INFORMATION
STK14CC8 – R F 25 I
Temperature Range
Blank = Commercial (0 to 70ºC)
I = Industrial (-40 to 85ºC)
Access Time
25 = 25ns
Lead Finish
F = 100% Sn (Matte Tin) RoHS Compliant
Package
R = Plastic 48-pin 300 mil SSOP (25 mil pitch)
September 2005
10
Document Control #ML0034 rev 0.0
STK14CC8
Document Revision History
Summary
Revision
Date
Advanced Information
0.0
January 2005
SIMTEK STK14CC8 Data Sheet, September 2005
Copyright 2005, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the express use of Simtek Customers. No part of this datasheet may be reproduced in any
other form or means without express written permission from Simtek Corporation. The information contained in this publication is
believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any
warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its
use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark or other proprietary
right.
September 2005
11
Document Control #ML0034 rev 0.0
相关型号：
STK14D88-3N25
Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO32, 0.300 INCH, 0.50 MM PITCH, PLASTIC, SOIC-32
SIMTEK
STK14D88-3N35
32KX8 NON-VOLATILE SRAM, 35ns, PDSO32, 0.300 INCH, 0.50 MM PITCH, PLASTIC, SOIC-32
SIMTEK
STK14D88-3N35I
Non-Volatile SRAM, 32KX8, 35ns, CMOS, PDSO32, 0.300 INCH, 0.50 MM PITCH, PLASTIC, SOIC-32
SIMTEK
STK14D88-3N45
32KX8 NON-VOLATILE SRAM, 45ns, PDSO32, 0.300 INCH, 0.50 MM PITCH, PLASTIC, SOIC-32
SIMTEK
STK14D88-3N45I
32KX8 NON-VOLATILE SRAM, 45ns, PDSO32, 0.300 INCH, 0.50 MM PITCH, PLASTIC, SOIC-32
SIMTEK
STK14D88-3NF25
32KX8 NON-VOLATILE SRAM, 25ns, PDSO32, 0.300 INCH, 0.50 MM PITCH, LEAD FREE, PLASTIC, SOIC-32
SIMTEK
STK14D88-3NF35I
Non-Volatile SRAM, 32KX8, 35ns, CMOS, PDSO32, 0.300 INCH, 0.50 MM PITCH, LEAD FREE, PLASTIC, SOIC-32
SIMTEK
STK14D88-3NF45I
Non-Volatile SRAM, 32KX8, 45ns, CMOS, PDSO32, 0.300 INCH, 0.50 MM PITCH, LEAD FREE, PLASTIC, SOIC-32
SIMTEK
STK14D88-3R25
32KX8 NON-VOLATILE SRAM, 25ns, PDSO48, 0.300 INCH, 0.25 MM PITCH, PLASTIC, SSOP-48
SIMTEK
©2020 ICPDF网 联系我们和版权申明