STK25C48-WF35 [SIMTEK]
2KX8 NON-VOLATILE SRAM, 35ns, PDIP24, 0.600 INCH, PLASTIC, DIP-24;
| 型号： | STK25C48-WF35 |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | 2KX8 NON-VOLATILE SRAM, 35ns, PDIP24, 0.600 INCH, PLASTIC, DIP-24 静态存储器 光电二极管 |
| 文件： | 总10页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK25C48
2K x 8 AutoStore™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Designs
DESCRIPTION
FEATURES
The STK25C48 is a fast SRAM with a nonvolatile element
incorporated in each static memory cell. The SRAM can
be read and written an unlimited number of times, while
independent nonvolatile data resides in the Nonvolatile
Elements. Data transfers from the SRAM to the Nonvola-
tile Elements (the STORE operation) can take place auto-
matically on power down using charge stored in system
capacitance. Transfers from the Nonvolatile Elements to
the SRAM (the RECALL operation) take place automati-
cally on restoration of power. The nvSRAM can be used in
place of existing 2K x 8 SRAMs and also matches the
pinout of 2K x 8 battery-backed SRAMs, EPROMs and
EEPROMs, allowing direct substitution while enhancing
performance. No support circuitry is required for micro-
processor interfacing.
• Nonvolatile Storage without Battery Problems
• Directly Replaces 2K x 8 Static RAM, Battery-
Backed RAM or EEPROMs
• 25ns, 35ns and 45ns Access Times
• STORE to Nonvolatile Elements Initiated by
AutoStore™ on Power Down
• RECALL to SRAM Initiated by Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Ele-
ments
• 100-Year Data Retention over Full Industrial
Temperature Range
• Commercial and Industrial Temperatures
• 24-Pin 600 PDIP Package
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
24
23
22
21
20
19
18
17
16
15
14
13
V
A
A
W
G
CC
QUANTUM TRAP
32 x 512
2
8
VCC
A
3
7
9
4
A
A
A
A
6
5
4
5
STORE
A5
A6
A7
A8
A9
STORE/
RECALL
CONTROL
6
POWER
CONTROL
A
E
10
STATIC RAM
ARRAY
7
3
2
RECALL
8
A
DQ
7
6
5
32 x 512
9
A
DQ
DQ
DQ
1
10
11
12
A
0
DQ
0
4
3
DQ
24 - 600 PDIP
1
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
PIN NAMES
COLUMN DEC
A
- A
10
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
0
W
DQ - DQ
0
7
A10
A0 A1 A2 A3 A4
G
E
G
E
W
V
V
CC
SS
March 2006
1
Document Control # ML0005 rev 0.2
STK25C48
a
ABSOLUTE MAXIMUM RATINGS
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS
(V = 5.0V 10%)
CC
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V
Current
85
75
65
90
75
65
mA
mA
mA
t
t
t
= 25ns
= 35ns
= 45ns
CC
CC
AVAV
AVAV
AVAV
1
c
I
I
Average V
Average V
Current during STORE
3
3
mA
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
CC
2
3
b
Current at t
AVAV
= 200ns
W ≥ (V
– 0.2V)
CC
10
10
5V, 25°C, Typical
All Others Cycling, CMOS Levels
c
I
I
Average V Current during
All Inputs Don’t Care
CC
CAP
AutoStore™ Cycle
4
2
2
mA
d
d
Average V
Current
25
21
18
26
22
19
mA
mA
mA
t
t
t
= 25ns, E ≥ V
= 35ns, E ≥ V
= 45ns, E ≥ V
SB
SB
CC
(Standby, Cycling TTL Input Levels)
AVAV
AVAV
AVAV
IH
IH
IH
1
2
I
I
I
V
Standby Current
E ≥ (V
– 0.2V)
CC
CC
1.5
1
1.5
1
mA
μA
μA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V = max
CC
ILK
V
= V to V
IN
SS CC
Off-State Output Leakage Current
V = max
CC
OLK
5
5
V
= V to V , E or G ≥ V
IN
SS CC IH
V
V
V
V
T
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.2
V
+ .5
2.2
– .5
V
+ .5
V
V
All Inputs
All Inputs
IH
CC
CC
V
– .5
0.8
V
0.8
IL
SS
SS
2.4
2.4
V
I
I
=–4mA
= 8mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
0
–40
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ).
4
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
5.0V
480 Ohms
e
OUTPUT
CAPACITANCE
(T = 25°C, f = 1.0MHz)
A
30 pF
INCLUDING
SCOPE AND
FIXTURE
255 Ohms
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
ΔV = 0 to 3V
ΔV = 0 to 3V
C
Input Capacitance
Output Capacitance
8
7
pF
IN
C
pF
OUT
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
March 2006
2Document Control # ML0005 rev 0.2
STK25C48
SRAM READ CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK25C48-25 STK25C48-35 STK25C48-45
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
Read Cycle Time
25
35
45
AVAV
RC
AA
g
3
Address Access Time
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
g
5
5
5
5
5
5
5
AXQX
6
ELQX
h
7
10
10
25
13
13
35
15
15
45
EHQZ
HZ
8
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
EHICCL
d, e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
f, g
SRAM READ CYCLE #1: Address Controlled
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
f
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
E
1
11
EHICCL
t
ELQV
t
6
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
March 2006
3
Document Control # ML0005 rev 0.2
STK25C48
SRAM WRITE CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK25C48-25
STK25C48-35
STK25C48-45
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
Write Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
20
0
25
0
30
0
AVWH
AVEH
AW
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
0
WHAX
h, i
EHAX
WR
t
t
10
13
15
WLQZ
WZ
t
t
5
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
j
SRAM WRITE CYCLE #1: W Controlled
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
t
WLWH
W
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
j
SRAM WRITE CYCLE #2: E Controlled
12
AVAV
t
ADDRESS
18
AVEL
19
t
EHAX
14
ELEH
t
t
E
1 7
AVEH
t
13
WLEH
t
W
16
EHDX
15
DVEH
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
March 2006
4Document Control # ML0005 rev 0.2
STK25C48
AutoStore™/POWER-UP RECALL
(V = 5.0V ± 10%)
CC
SYMBOLS
STK25C48
NO.
PARAMETER
UNITS NOTES
Standard
MIN
MAX
550
10
22
23
24
25
26
t
t
t
Power-up RECALL Duration
STORE Cycle Duration
μs
ms
μs
V
k
g
g
RESTORE
STORE
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
1
DELAY
V
4.0
4.5
3.6
SWITCH
RESET
V
Low Voltage Reset Level
V
e
Note k: tRESTORE starts from the time VCC rises above VSWITCH
.
AutoStore™/POWER-UP RECALL
V
CC
5V
25
V
SWITCH
26
RESET
V
AutoStore™
23
STORE
t
POWER-UP RECALL
24
DELAY
22
RESTORE
t
t
W
DQ (DATA OUT)
BROWN OUT
BROWN OUT
POWER-UP
BROWN OUT
AutoStore™
AutoStore™
RECALL
NO STORE DUE TO
NO SRAM WRITES
NO RECALL
(VCC DID NOT GO
RECALL WHEN
RETURNS
NO RECALL
(VCC DID NOT GO
V
CC
BELOW VRESET
)
ABOVE VSWITCH
BELOW VRESET
)
March 2006
5
Document Control # ML0005 rev 0.2
STK25C48
DEVICE OPERATION
The STK25C48 is a versatile memory chip that pro-
vides several modes of operation. The STK25C48
can operate as a standard 8K x 8 SRAM. It has an
8K x 8 Nonvolatile Elements shadow to which the
SRAM information can be copied, or from which the
SRAM can be updated in nonvolatile mode.
AutoStore™ OPERATION
The STK25C48 uses the intrinsic system capaci-
tance to perform an automatic store on power down.
As long as the system power supply takes at least
tSTORE to decay from VSWITCH down to 3.6V, the
STK25C48 will safely and automatically store the
SRAM data in Nonvolatile Elements on power down.
NOISE CONSIDERATIONS
In order to prevent unneeded STORE operations,
automatic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle.
Note that the STK25C48 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
SRAM READ
The STK25C48 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-10 determines which of the 2,048 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high or W is brought low.
If the STK25C48 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
HARDWARE PROTECT
The STK25C48 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs
during low-voltage conditions. When VCC < VSWITCH
,
STORE operations and SRAM WRITEs are inhibited.
SRAM WRITE
LOW AVERAGE ACTIVE POWER
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
The STK25C48 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK25C48 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the VCC level; and 7) I/O loading.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
March 2006
6Document Control # ML0005 rev 0.2
STK25C48
100
80
60
40
20
0
100
80
60
40
20
0
TTL
CMOS
TTL
CMOS
50
100
150
200
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 2: I (max) Reads
Figure 3: I (max) Writes
CC
CC
March 2006
7
Document Control # ML0005 rev 0.2
STK25C48
ORDERING INFORMATION
- W F 45 I
STK25C48
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
W = Plastic 24-pin 600 mil DIP
March 2006
8Document Control # ML0005 rev 0.2
STK25C48
Document Revision History
Revision
0.0
Date
December 2002
September 2003
March 2006
Summary
Removed 20 nsec device.
0.1
Added lead-free lead finish
0.2
Marked as Obsolete, Not recommended for new design.
March 2006
9
Document Control # ML0005 rev 0.2
STK25C48
March 2006
10Document Control # ML0005 rev 0.2
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