UL62H256BSA55G1 [SIMTEK]

Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 0.300 INCH, SOP-28;


型号：	UL62H256BSA55G1
厂家：	SIMTEK CORPORATION
描述：	Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 0.300 INCH, SOP-28 静态存储器光电二极管内存集成电路
文件：	总10页 (文件大小：87K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UL62H256B

Low Voltage Automotive Fast 32K x 8 SRAM

Features

Description

The UL62H256B is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

F 32768 x 8 bit static CMOS RAM

F 35 and 55 ns Access Time

F Common data inputs and

data outputs

address change, the data outputs

go High-Z until the new information

is available. The data outputs have

no preferred state. The Read cycle

is finished by the falling edge of W,

or by the rising edge of E, respec-

tively.

Data retention is guaranteed down

to 1.5 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

F Three-state outputs

F Typ. operating supply current

35 ns: 45 mA

- Read

- Write

- Standby

- Data Retention

The memory array is based on a

6-Transistor cell.

55 ns: 30 mA

F Standby current < 30 µA at 125 °C The circuit is activated by the fal-

F Power supply voltage 2.5 V

F Operating temperature range

-40 °C to 85 °C

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word will be available at the

outputs DQ0-DQ7. After the

-40 °C to 125 °C

F CECC 90000 Quality Standard

F ESD protection > 2000 V

(MIL STD 883C M3015.7)

F Latch-up immunity >100 mA

F Package: SOP28 (300/330 mil)

Pin Description

Pin Configuration

VCC

A14

A12

A13

Signal Name Signal Description

A0 - A14

Address Inputs

Data In/Out

A11

DQ0 - DQ7

Chip Enable

A10

Output Enable

Write Enable

Power Supply Voltage

Ground

SOP

DQ7

VCC

VSS

DQ0

DQ1

DQ2

VSS

DQ6

DQ5

DQ4

DQ3

Top View

November 26, 2002

UL62H256B

Block Diagram

Memory Cell

Array

A10

A11

A12

A13

A14

512 Rows x

64 x 8 Columns

DQ0

DQ1

Sense Amplifier/

Write Control Logic

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Address

Change

Detector

Clock

Generator

V_CC

V_SS

Truth Table

Operating Mode

DQ0 - DQ7

Standby/not selected

Internal Read

Read

High-Z

Data Outputs Low-Z

Data Inputs High-Z

Write

H or L

November 26, 2002

UL62H256B

Characteristics

All voltages are referenced to V_SS= 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.

Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V_I, as well as

input levels of V_IL= 0 V and V_IH= 2.2 V. The timing reference level of all input and output signals is 1.1 V,

with the exception of the t_dis-times and t_en-times, in which cases transition is measured ±200 mV from steady-state voltage.

Absolute Maximum Ratings

Symbol

Min.

Max.

Unit

Power Supply Voltage

Input Voltage

V_CC

V_I

-0.3

V_CC+ 0.3

Output Voltage

V_O

P_D

T_a

Power Dissipation

Operating Temperature

°C

K-Type

A-Type

-40

125

Storage Temperature

T_stg

-65

150

100

°C

Output Short-Circuit Current

at V_CC= 2.5 V and V_O= 0 V ^c

| I_OS

Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating

only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability

Maximum voltage is 4 V

Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

Recommended

Operating Conditions

Symbol

V_CC

Conditions

Min.

2.3

Max.

2.7

Unit

Power Supply Voltage

Input Low Voltage ^d

Input High Voltage

V_IL

-0.2

2.0

0.4

V_IH

V_CC+ 0.2

^d-2 V at Pulse Width 10 ns

November 26, 2002

UL62H256B

Electrical Characteristics

Symbol

Conditions

Min.

Max.

Unit

Supply Current - Operating Mode

I_CC(OP)

V_CC

V_IL

V_IH

t_cW

= 2.7 V

= 0.6 V

= 2.0 V

= 35 ns

= 55 ns

Supply Current - Standby Mode

(CMOS level)

I_CC(SB)

V_CC

V_E

= 2.7 V

= V_CC- 0.2 V

K-Type

A-Type

µA

Supply Current - Standby Mode

(TTL level)

I_CC(SB)1

V_CC

V_E

= 2.7 V

= 2.2 V

K-Type

A-Type

Output High Voltage

Output Low Voltage

V_OH

V_OL

V_CC

I_OH

V_CC

I_OL

= 2.3 V

= -0.5 mA

= 2.3 V

2.0

0.4

= 0.5 mA

Input High Leakage Current

Input Low Leakage Current

I_IH

I_IL

V_CC

V_IH

V_CC

V_IL

= 2.7 V

µA

-2

0 V

Output High Current

Output Low Current

I_OH

I_OL

V_CC

V_OH

V_CC

V_OL

= 2.3 V

= 2.0 V

= 2.3 V

= 0.4 V

-0.5

0.5

Output Leakage Current

High at Three-State Outputs

I_OHZ

I_OLZ

V_CC

V_OH

V_CC

V_OL

= 2.7 V

µA

Low at Three-State Outputs

-2

0 V

November 26, 2002

UL62H256B

Symbol

Alt.

t_RC

t_AA

t_ACE

t_OE

Switching Characteristics

Read Cycle

Unit

IEC

t_cR

Min.

Max.

Min.

Max.

Read Cycle Time

Address Access Time to Data Valid

Chip Enable Access Time to Data Valid

G LOW to Data Valid

t_a(A)

t_a(E)

t_a(G)

t_dis(E)

t_dis(G)

t_en(E)

t_en(G)

t_v(A)

E HIGH to Output in High-Z

G HIGH to Output in High-Z

E LOW to Output in Low-Z

G LOW to Output in Low-Z

Output Hold Time from Address Change

E LOW to Power-Up Time

t_HZCE

t_HZOE

t_LZCE

t_LZOE

t_OH

t_PU

E HIGH to Power-Down Time

t_PD

Symbol

Switching Characteristics

Write Cycle

Unit

Min.

Max.

Min.

Max.

Alt.

t_WC

IEC

t_cW

Write Cycle Time

Write Pulse Width

t_WP

t_w(W)

t_su(W)

t_su(A)

Write Setup Time

t_WP

Address Setup Time

t_AS

Address Valid to End of Write

Chip Enable Setup Time

Pulse Width Chip Enable to End of Write

Data Setup Time

t_AW

su(A-WH)

t_CW

t_su(E)

t_CW

t_w(E)

t_su(D)

t_h(D)

t_DS

Data Hold Time

t_DH

Address Hold from End of Write

W LOW to Output in High-Z

G HIGH to Output in High-Z

W HIGH to Output in Low-Z

G LOW to Output in Low-Z

t_AH

t_h(A)

t_HZWE

t_HZOE

t_LZWE

t_LZOE

t_dis(W)

t_dis(G)

t_en(W)

t_en(G)

November 26, 2002

UL62H256B

Data Retention Mode

E - controlled

V_CC

2.3 V

V_CC(DR)≥ 1.5 V

2.0 V

t_su(DR)

t_rec

Data Retention

0 V

- 0.2 V ≤ V

≤ V

+ 0.3 V

CC(DR)

E(DR)

CC(DR)

Data Retention

Characteristics

Symbol

Alt. IEC

V_CC(DR)

I_CC(DR)V_CC(DR)= 2V

Conditions

Min. Typ. Max.

Unit

Data Retention Supply Voltage

Data Retention Supply Current

1.5

V_E

= V_CC(DR)- 0.2 V

K-Type

A-Type

µA

Data Retention Setup Time

Operating Recovery Time

t_CDR

t_R

t_su(DR)See Data Retention

Waveforms (above)

t_rec

t_cR

Test Configuration for Functional Check

2.5 V

V_CC

DQ0

DQ1

DQ2

DQ3

3332

V_IH

DQ4

DQ5

DQ6

DQ7

A10

A11

A12

A13

A14

V_IL

V_O

30 pF ^e

3077

V_SS

In measurement of t

, t

the capacitance is 5 pF.

dis(E) dis(W) en(E) en(W) en(G)

November 26, 2002

UL62H256B

Capacitance

Conditions

Symbol

Min.

Max.

Unit

Input Capacitance

V_CC= 2.5 V

C_I

V_I

= V_SS

= 1 MHz

= 25 °C

Output Capacitance

C_o

All pins not under test must be connected with ground by capacitors.

IC Code Numbers

UL62H256B S

Internal Code

Type

Access Time

Package

S = SOP28 (300 mil)

S2 = SOP28 (330 mil) Type 2

35 = 35 ns

55 = 55 ns

Operating Temperature Range

K = -40 to 85 °C

A = -40 to 125 °C

The date of manufacture is given by the last 4 digits of the third line of the mark, the first 2 digits indicating the year,

and the last 2 digits the calendar week.

Assembly location and trace code are shown in line 4.

November 26, 2002

UL62H256B

Read Cycle 1: A_i-controlled (during Read Cycle : E = G = V_IL, W = V_IH)

t_cR

Address Valid

t_a(A)

DQi

Output

Previous Data Valid

t_v(A)

Output Data Valid

Read Cycle 2: G-, E-controlled (during Read Cycle: W = V_IH)

t_cR

Address Valid

t_a(E)

t_dis(E)

t_su(A)

t_en(E)

t_dis(G)

t_a(G)

t_en(G)

DQi

Output

High-Z

t_PU

Output Data Valid

t_PD

I_CC(OP)

I_CC(SB)

50 %

November 26, 2002

UL62H256B

Write Cycle1: W-controlled

t_cW

Address Valid

t_su(E)

t_h(A)

t_su(A-WH)

t_w(W)

t_su(A)

t_su(D)

Input Data Valid

t_en(W)

t_h(D)

DQi

Input

t_dis(W)

DQi

High-Z

Output

Write Cycle 2: E-controlled

t_cW

Address Valid

t_w(E)

t_su(A)

t_h(A)

t_su(W)

t_su(D)

t_h(D)

DQi

Input

Input Data Valid

t_dis(W)

t_en(E

)

DQi

High-Z

Output

t_dis(G)

undefined

L- to H-level

H- to L-level

The information describes the type of component and shall not be considered as assured characteristics.Terms of

delivery and rights to change design reserved.

November 26, 2002

UL62H256B

LIFE SUPPORT POLICY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or other applications intended to support or sustain life, or for any other application in which

the failure of the ZMD product could create a situation where personal injury or death may occur.

Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.

LIMITED WARRANTY

The information in this document has been carefully checked and is believed to be reliable. However Zentrum

Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information

and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.

The information in this document describes the type of component and shall not be considered as assured charac-

teristics.

ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-

mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This

document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and

conditions of sale.

ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,

presented in this publication at any time and without notice.

November 26, 2002

Zentrum Mikroelektronik Dresden AG

Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany

Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de

UL62H256BSA55G1 [SIMTEK]

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