SP7514 [SIPEX]
14-Bit Multiplying DACs; 14位乘法DAC型号: | SP7514 |
厂家: | SIPEX CORPORATION |
描述: | 14-Bit Multiplying DACs |
文件: | 总8页 (文件大小:103K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SP7514 and HS3140
Corporation
SIGNAL PROCESSING EXCELLENCE
14-Bit Multiplying DACs
■ Monolithic Construction
■ 14–Bit Resolution
■ 0.003% Non-Linearity
■ Four-Quadrant Multiplication
■ Latch-up Protected
■ Low Power - 30mW
■ Single +15V Power Supply
DESCRIPTION…
The SP7514 and HS3140 are precision 14-bit multiplying DACs, that provide four-quadrant
multiplication. Both parts accept both AC and DC reference voltages. The SP7514 is available
for use in commercial and industrial temperature ranges, packaged in a 20-pin SOIC. The
HS3140 is available in commercial and military temperature ranges, packaged in a 20-pin
side-brazed DIP.
SP7514, HS3140
15 EQUAL
SECTIONS
48k
19
V
2
REF
I
OUT
2
96k
96k
96k
96k
3
GND
I
OUT
1
18
1
V
DD
6k
4 to 16 DECODE
SWITCHES ARE
SHOWN IN THE
HIGH STATE
4
5
6
7
17
20
BIT 1 BIT 2 BIT 3 BIT 4
(MSB)
BIT 14
LSB
R
FEEDBACK
159
Corporation
SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS
(Typical @ 25°C, nominal power supply, VREF = +10V, unipolar unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DIGITAL INPUT
Resolution
14
Bits
2–Quad, Unipolar Coding
4–Quad, Bipolar Coding
Logic Compatibility
Input Current
Binary
Offset Binary
CMOS, TTL
Note 1
±1
µA
REFERENCE INPUT
Voltage Range
±25
V
Note 2
Input Impedance
3.25
75
9.75
KOhms
ANALOG OUTPUT
Scale Factor
Scale Factor Accuracy
Output Leakage
225
±1
10
µA/VREF
%
Note 3
Note 4
nA
Output Capacitance
COUT 1, all inputs high
COUT 1, all inputs low
COUT 2, all inputs high
COUT 2, all inputs low
100
50
50
pF
pF
pF
pF
100
STATIC PERFORMANCE
Integral Linearity
SP7514KN/BN, HS3140–4
SP7514JN/AN, HS3140–3
Differential Linearity
Note 5
Note 6
±0.003
±0.006
±0.006
±0.012
% FSR
% FSR
SP7514KN/BN, HS3140–4
SP7514JN/AN, HS3140–3
Monotonicity
±0.003
±0.006
±0.006
±0.012
%FSR
% FSR
SP7514KN/BN, HS3140–4
SP7514JN/AN, HS3140–3
Guaranteed to 14 bits
Guaranteed to 13 bits
STABILITY
(TMIN to TMAX
)
Scale Factor
4
0.5
0.5
ppm FSR/°C
ppm FSR/°C
ppm FSR/°C
Note 7 and 8
Integral Linearity
Differential Linearity
Monotonicity Temp. Range
SP7514JN/KN, HS3140C
SP7514AN/BN
1.0
1.0
0
–40
–55
+70
+85
+125
°C
°C
°C
HS3140B
DYNAMIC PERFORMANCE
Digital Small Signal Settling
Digital Full Scale Settling
Reference Feedthrough Error
@ 1kHz
1.0
2.0
µS
µS
(VREF = 20Vpp)
200
2
µV
mV
@ 10kHz
Reference Input Bandwidth
1
MHz
POWER SUPPLY (VDD
)
Operating Voltage
Voltage Range
Current
+15 ±5%
V
V
mA
%/%
+8
+18
2.0
Note 9
Rejection Ratio
0.005
160
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SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS (continued)
(Typical @ 25°C, nominal power supply, VREF = +10V, unipolar unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
SP7514JN/KN
SP7514AN/BN
HS3140–C
0
–40
0
–55
–55
–65
+70
+85
+70
+125
+125
+150
°C
°C
°C
°C
°C
°C
HS3140–B
HS3140–B/883
Storage Temperature
Package
SP7514_N
20-pin SOIC
HS3140
20–pin Side–Brazed DIP
Notes:
1.
2.
3.
Digital input voltage must not exceed supply voltage or go below –0.5V ; “0” <0.8V; 2.4V < “1” ≤VDD.
AC or DC; use R6758–1 for fixed reference applications
Using the internal feedback resistor and an external op amp. The Scale Factor can be adjusted externally by variable resistors in series with the
reference input and/or in series to the internal feedback resistor. Please refer to the Applications Information section.
At 25°C; the output leakage current will create an offset voltage at the external op amps output. It doubles every 10°C temperature increase.
Integral Linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from
the theoretical value for any given input combination.
4.
5.
6.
7.
8.
9.
Differential Linearity is the deviation of an output step form the theoretical value of 1LSB for any two adjacent digital input codes.
At 25°C, the output leakage current will create an offset voltage output. It doubles every 10°C temperature increase.
Using the internal feedback resistor and an external op amp.
Use series 470ohm resistor to limit start-up current.
CHARACTERISTIC CURVES
(Typical @ + 25°C, VDD = + 15VDC, VREF = + 10VDC, unless otherwise noted)
50
40
30
20
10
0
0.048
2 LSB
0.024
0.012
1 LSB
0.006
0.003
1/2 LSB @ 16 BITS
0.01
0.1
1
10
V
-VOLTS
REF
Integral Linearity Error vs. Reference Voltage
0
10
20
30
-mV
40
50
V
OS
0.048%
Additional Linearity Error vs. Output-Amplifier
Offset-Voltage (VREF = + 10V)
0.024%
0.012%
0.01
0.006%
0.003%
0.008
4
6
8
10
V
12
14
16
18
0.006
-VOLTS
DD
Linearity vs. Supply Voltage
0.004
0.002
0
2.5
2.0
1.5
1.0
4
6
8
10
V
12
14
16
18
-VOLTS
DD
Gain Change vs. Supply Voltage
4
6
8
10
V
12
14
16
18
10
-VOLTS
DD
Power Supply Current vs. Voltage
161
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SIGNAL PROCESSING EXCELLENCE
PIN ASSIGNMENTS…
PRINCIPLES OF OPERATION
TheSP7514/HS3140achievehighaccuracybyusing
a decoded or segmented DAC scheme to implement
this function. The following is a brief description of
this approach.
Pin 1 – IO1 – Current Output 1.
Pin 2 – IO2 – Current Output 2.
Pin 3 – GND – Ground.
Pin 4 – DB13 – MSB, Data Bit 1.
Pin 5 – DB12 – Data Bit 2.
The most common technique for building a D/A
converterofnbitsistousenswitchestoturnncurrent
or voltage sources on or off. The n switches and n
sourcesaredesignedsothateachswitchorbitcontrib-
utestwiceasmuchtotheD/Aconverter’soutputasthe
preceding bit. This technique is commonly known as
binary weighting and allows an n-bit converter to
generate 2n output levels by turning on the proper
combination of bits.
Pin 6 – DB11 – Data Bit 3.
Pin 7 – DB10 – Data Bit 4.
Pin 8 – DB9 – Data Bit 5.
Pin 9 – DB8 – Data Bit 6.
Pin 10 – DB7 – Data Bit 7.
Pin 11 – DB6 – Data Bit 8.
Pin 12 – DB5 – Data Bit 9.
In such binary-weighted converter, the switch
with the smallest contribution (the LSB) accounts
for only 2-n of the converter’s full-scale value.
Similarly, the switch with the largest contribution
(theMSB)accountsfor2-1orhalfoftheconverter’s
full-scale output. Thus it is easy to see that a given
percent change in the MSB will have a greater
effect on the converter’s output than would a
similar percent change in the LSB. For example, a
1% change in the LSB of a 10 bit converter would
only affect the output by 0.001% of full-scale. A
1% change in the MSB of the same converter
would affect the output by 0.5% of FSR.
Pin 13 – DB4 – Data Bit 10.
Pin 14 – DB3 – Data Bit 11.
Pin 15 – DB2 – Data Bit 12.
Pin 16 – DB1 – Data Bit 13.
Pin 17 – DB0 – LSB, Data Bit 14.
Pin 18 – VDD – Positive Supply Voltage.
Pin 19 – VREF – Reference Voltage Input.
Pin 20 – RFB – Feedback Resistor.
In order to overcome the problem which results from
the large weighting of the MSB, the two MSB’s can
be decoded to three equally weighted sources. Table
1 shows that all combinations of the two MSB’s of a
converter result in four output levels. So by replacing
the two MSB’s with three bits equally weighted at 1/
4 full-scale and decoding the two MSB digital inputs
into three lines which drive the equally weighted bits,
the same functional performance can be obtained.
ThusbyreplacingthetwoMSBswitchesofaconven-
tional converter with three switches properly de-
coded, the contribution ofanyswitchisreducedfrom
1/2to1/4.Thisreductioninsensitivityalsoreducesthe
FEATURES…
The SP7514 and HS3140 are precision 14-bit multi-
plying DACs. The DACs are implemented as a one-
chip CMOS circuit with a resistor ladder network.
ThreeoutputlinesareprovidedontheDACstoallow
unipolar and bipolar output connection with a mini-
mum of external components. The feedback resistor
is internal. The resistor ladder network termination is
externally available, thus eliminating an external re-
sistor for the 1 LSB offset in bipolar mode.
The SP7514 is available for use in commercial and
industrial temperature ranges, packaged in a 20-pin
SOIC. The HS3140 is available in commercial
and military temperature ranges, packaged in a
20–pin side–brazed DIP. For product processed
and screened to the requirements of MIL–M–
38510 and MIL–STD–883C, please consult the
factory (HS3140B only).
C
f
R
f
V
–
REF
E
R
O
C
i
+
O
R
C
p
Figure 1. SP7514/HS3140 Equivalent Output Circuit
162
Corporation
SIGNAL PROCESSING EXCELLENCE
- 1
- 2
2
(MSB)
2
Output
400Ω
470Ω
V
V
REF
DD
0
0
1
1
0
0
200Ω
1
0
1
1/4 Full-Scale
1/2 Full-Scale
3/4 Full-Scale
R
I
FEEDBACK
R
OS
-
O1
DIGITAL
INPUTS
A
+
I
O2
SP7514
HS3140
V
Table 1. Contribution of the two MSB's
OUT
accuracy required of any switch for a given overall
converter accuracy.
GND
With the decoded converter described above, a 1%
change in any of the converter’s switches will affect
the output by no more than 0.25% of full-scale as
compared to 0.5% for a conventional converter. In
other words the conventional D/A converter can be
made less sensitive to the quality of its individual bits
by decoding.
Figure 2. Unipolar Operation
settlingtime,andbandwidth.TheDACoutputequiva-
lent circuit can be represented as shown in Figure 1.
Digitalfeedthroughisthechangeinanalogoutputdue
to the toggling conditions on the converter input data
lines when the analog input VREF is at 0V. The
SP7514/HS3140verylowCOandthereforewillyield
low digital feedthrough. Inputs to the DAC can be
buffered.Thisinputlatchwithmicroprocessorcontrol
is shown in Figure 4.
In the SP7514/HS3140 the first four MSB’s are
decodedinto16levelswhichdrive15equallyweighted
current sources. The sensitivity of each switch on the
output is reduced by a factor of 8. Each of the 15
sources contributes 6.25% output change rather than
an MSB change of 50% for the common approach.
SettlingtimeisdirectlyaffectedbyCO.InFigure1,CO
combines with Rf to add a pole to the open loop
response, reducing bandwidth and causing excessive
phase shift - which could result in ringing and/or
oscillation.Afeedbackcapacitor,Cf mustbeaddedto
restorestability.EvenwithCf,thereisstillazero-pole
mismatchduetoRiCO whichiscodedependent. This
codedependentmismatchisminimizedwhenCORi =
RfCf. However Cf must now be made larger to
compensate for worst case ∆RiCO - resulting in re-
ducedbandwidthandincreasedsettlingtime.Withthe
SP7514/HS3140, small values for Cf must be used.
FollowingthedecodedsectionoftheDACastandard
binary weighted R-2R approach is used. This divides
each of the 16 levels (or 6.25% of F.S.) into 4096
discrete levels (the 12 LSB’s).
Output Capacitance
The SP7514/HS3140 have very low output capaci-
tance(CO).ThisisspecifiedbothwithallswitchesON
andallswitchesOFF.Outputcapacitancevariesfrom
50pF to 100pF over all input codes. This low capaci-
tance is due in part to the decoding technique used.
Smaller switches are used with resulting less capaci-
tance. Three important system characteristics are
affected by CO and∆CO; namely digital feedthrough,
400Ω
470Ω
V
V
REF
DD
200Ω
R
FEEDBACK
R
OS1
-
I
I
O1
A
1
DIGITAL
INPUTS
SP7514
HS3140
TRANSFER FUNCTION (N=14)
+
V
OUT
4KΩ
BINARY INPUT UNIPOLAR OUTPUT BIPOLAR OUTPUT
4KΩ
111...111
100...001
100...000
011...111
000…001
000...000
–VREF (1 - 2–N
)
–VREF (1 – 2 –(N – 1)
–VREF (2 –(N – 1)
0
VREF (2 –(N – 1)
VREF (1 – 2 –(N – 1)
)
O2
–VREF (1/2 + 2–N
)
)
)
R
R
OS2
GND
–VREF /2
–VREF (1/2 – 2–N
R
OS2
)
-
A
2
+
–VREF (2(N – 1)
)
)
V
OUT1
, A
, OP-07
2
A
1
0
VREF
Table 2. Transfer Function
Figure 3. Bipolar Operation
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SIGNAL PROCESSING EXCELLENCE
1. Using LF441A amplifier (low power - 741 pinout)
2. Specified offset: 0.5mV max
3. Temperature coefficient of input offset: 10µV/°C max
VOS max (0°C to 70°C) = 0.5mV + (70µV)10
= 1.2mV
V
DD
470
V
REF
(+ 25V MAX)
400
3
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
V
LSB
15
14
13
12
11
10
9
REF
UNIPOLAR MODE
(2-QUADRANT)
V
+
DD
200
74273
CLK
R
F
2
V
OUT
REF
N
I
01
02
–
6
0 TO - V
(1-2 -
A
1
3
I
+
)
Add'l nonlinearity (max.) = 1.2mV x 0.065mV/mV
SP7514/
HS3140
8
7
6
5
R
D0
D1
D2
D3
D4
D5
D6
D7
0S
=
78µV (1/2 LSB @ 16 Bits)
Where: 78µV = 1/2 LSB @ 16 Bits (10V range)
WR
G2A
74273
74LS138
4
3
2
BDSEL
G2B
C
Via the above configuration, the SP7514/HS3140
can be used to divide an analog signal by digital code
(i.e. for digitally controlled gain). The transfer func-
tion is given in Table 2, where the value of each bit is
0or1.Divisionbyall“0”sisundefinedandcausesthe
op amp to saturate.
A
2
MSB
GND
CLK
A
A
1
0
B
A
ADDRESS DECODER
LATCHES
Figure 4. Microprocessor Interface to SP7514/HS3140
ResistorRp canbeadded,thiswillparallelRj decreas-
ing the effective resistance. If Cf is reduced the
bandwidth will be increased and settling time de-
creased. HoweverasystempenaltyforloweringCf is
to increase noise gain. The trade-off is noise vs.
settling time. If Rp is added then a large value (1µF or
greater) non-polarized capacitor Cp should be added
in series with Rp to eliminate any DC drifts. If settling
time is not important, eliminate Rp and Cp, and adjust
Cf to prevent overshoot.
Applications Information
Unipolar Operation
Figure 2 shows the interconnections for unipolar
operation. ConnectIO1 andFB1 asshownindiagram.
TieIO2 (Pin7),FB3 (Pin3),andFB4 (Pin1)toGround
(Pin8).Asshown,aseriesresistorisrecommendedin
the VDD supply line to limit current during ‘turn-on’.
To maintain specified linearity, external amplifiers
must be zeroed. Apply an ALL “ZEROES” digital
input and adjust ROS for VOUT = 0 ± 1mV. The
SP7514 and HS3140 have been used successfully
with OP-07, OP-27 and LF441A. For high speed
applications the SP2525 is recommended.
Output Offset
Inmostapplications,theoutputoftheDACisfedinto
an amplifier to convert the DAC’s current output to
voltage. A little known and not commonly discussed
parameteristhelinearityerrorversusoffsetvoltageof
theoutputamplifier. AllCMOSDAC’smustoperate
into a virtual ground, i.e., the summing junction of an
opamp.Anyamplifier’soffsetfromtheamplifierwill
appear as an error at the output (which can be related
to LSB’s of error).
Bipolar Operation
Figure 3 shows the interconnections for bipolar op-
eration. Connect IO1, IO2, FB1, FB3, FB4 as shown in
diagram.TieLDTRtoIO2.Asshown,aseriesresistor
isrecommendedintheVDDsupplylinetolimitcurrent
during‘turn-on.Tomaintainspecifiedlinearity,exter-
nal amplifiers must be zeroed. This is best done with
MostallCMOSDAC’scurrentlyavailableareimple-
mented using an R-2R ladder network. The formula
for nonlinearity is typically 0.67mV/mVOS (not de-
rived here). However the SP7516 has a coefficient of
only 0.065mV/mVOS. This is due to the decoding
technique described earlier. CMOS DAC applica-
tions notes (including this one) always show a poten-
tiometer used to null out the amplifier’s offset. If an
amplifierischosenhaving‘pretrimmed’offsetitmay
bepossibletoeliminatethiscomponent.Considerthe
following calculations:
V
REF set to zero and, the DAC register loaded with
10...0 (MSB = 1). Set R0S1 for V01 = 0. Set R0S2 for
OUT = 0. Set VREF to +10V and adjust RB for VOUT
V
to be 0V.
Grounding
Connect all GND pins to system analog ground
and tie this to digital ground. All unused input pins
must be grounded.
164
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SIGNAL PROCESSING EXCELLENCE
ORDERING INFORMATION
Model ................................................................ Monotonicity .................................. Temperature Range .................................... Package
Double-Buffered 12-Bit Multiplying DAC
HS3140C-3Q ............................................................ 13-Bit ............................................... 0°C to +70°C ................... 20-pin, 0.3" Side-Brazed DIP
HS3140B-3Q ............................................................ 13-Bit ......................................... -55°C to +125°C ................... 20-pin, 0.3" Side-Brazed DIP
HS3140B-3/883 ....................................................... 13-Bit ......................................... -55°C to +125°C ................... 20-pin, 0.3" Side-Brazed DIP
HS3140C-4Q ............................................................ 14-Bit ............................................... 0°C to +70°C ................... 20-pin, 0.3" Side-Brazed DIP
HS3140B-4Q ............................................................ 14-Bit ......................................... -55°C to +125°C ................... 20-pin, 0.3" Side-Brazed DIP
HS3140B-4/883 ....................................................... 14-Bit ......................................... -55°C to +125°C ................... 20-pin, 0.3" Side-Brazed DIP
SP7514JN ................................................................ 13-Bit ............................................... 0°C to +70°C ...................................... 20-pin, 0.3" SOIC
SP7514KN ............................................................... 14-Bit ............................................... 0°C to +70°C ...................................... 20-pin, 0.3" SOIC
SP7514AN ............................................................... 13-Bit .......................................... –40°C to +85°C ...................................... 20-pin, 0.3" SOIC
SP7514BN ............................................................... 14-Bit .......................................... –40°C to +85°C ...................................... 20-pin, 0.3" SOIC
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