SP7651 [SIPEX]
Wide Input Voltage Range 3A, 900kHz, Buck Regulator; 宽输入电压范围3A , 900kHz的,降压型稳压器型号: | SP7651 |
厂家: | SIPEX CORPORATION |
描述: | Wide Input Voltage Range 3A, 900kHz, Buck Regulator |
文件: | 总12页 (文件大小:117K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
Advanced
SP7651
Wide Input Voltage Range 3A, 900kHz, Buck Regulator
SP7651
FEATURES
■ 2.5V to 20V Step Down Achieved Using Dual Input
DFN PACKAGE
7mm x 4mm
■ Output Voltage down to 0.8V
P
P
GND
GND
GND
1
2
3
26
25
24
23
LX
LX
LX
TOP VIEW
■ 3A Output Capability (Up to 5A with Air Flow)
■ Built in Low RDSON Power FETs (40 mΩ typ)
■ Highly Integrated Design, Minimal Components
■ 900 kHz Fixed Frequency Operation
■ UVLO Detects Both VCC and VIN
Heatsink Pad 1
Connect to Lx
P
GND
4
5
LX
V
FB
22 V
CC
COMP
UVIN
GND
SS
21 GND
20 GND
6
7
Heatsink pad 2
Connect to GND
■ Over Temperature Protection
■ Short Circuit Protection with Auto-Restart
■ Wide BW Amp Allows Type II or III Compensation
■ Programmable Soft Start
8
9
19
18
GND
BST
V
IN 10
17
16
NC
LX
Heatsink pad 3
■ Fast Transient Response
V
V
V
IN 11
IN 12
Connect to V
IN
■ High Efficiency: Greater than 92% Possible
■ Asynchronous Start-Up into a Pre-Charged Output
■ Small 7mm x 4mm DFN Package
15 LX
14
LX
IN 13
Now Available in Lead Free Packaging
DESCRIPTION
The SP7651 is a high voltage synchronous step-down switching regulator optimized for high efficiency. The part is
designed to be especially attractive for dual supply, 12V step down with 5V used to power the controller. This lower VCC
voltage minimizes power dissipation in the part. The SP7651 is designed to provide a fully integrated buck regulator
solution using a fixed 900kHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal
shutdown and output short circuit protection. The SP7651 is available in the space saving 7mm X 4mm DFN package.
TYPICAL APPLICATION CIRCUIT
U1
SP7651
L1
1
2
26
25
PGND
PGND
LX
LX
VOUT
3.3V
0-3A
4.7uH, Irate=3.87A
RZ2
CZ2
3
24
RZ3
PGND
GND
LX
LX
15k,1%
7.15k,1%
1,000pF
C3
4
5
6
23
22
21
R1
68.1k,1%
22uF
6.3V
CP1
VFB
VCC
GND
CZ3
150pF
22pF
COMP
CVCC
2.2uF
7
8
20
19
CF1
100pF
ENABLE
UVIN
GND
GND
GND
DBST
9
18
RSET
21.5k,1%
(note 2)
SS
BST
NC
10
11
17
16
SD101AWS
VIN
CSS
15nF
VIN
VIN
LX
LX
CBST
6800pF
12
13
15
14
VIN
LX
VIN
+5V VCC
12V
fs=900Khz
Notes:
C1
22uF
1. U1 Bottom-Side Layout should
has three contacts isolated from
one another Vin SWNODE and GND
16V
GND
2. RSET=54.48/(Vout-0.8V)
(KOhm)
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect reliability.
GH ......................................................................... -0.3V to BST+0.3V
GH-SWN ......................................................................................... 7V
All other pins .......................................................... -0.3V to VCC+0.3V
VCC .................................................................................................. 7V
VIN ........................................................................................................................................... 22V
ILX ............................................................................................................................................... 5A
BST ............................................................................................... 35V
BST-SWN ......................................................................... -0.3V to 7V
SWN ................................................................................... -1V to 20V
Storage Temperature .................................................. -65°C to 150°C
Power Dissipation .................................................... Internally Limited
Lead Temperature (Soldering, 10 sec) ...................................... 300°C
ESD Rating .......................................................................... 2kV HBM
Thermal Resistance ϑJC .................................................................................... 5°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C<Tj<125°C, 4.5V < VCC < 5.5V, 3V<Vin<20V, BST=LX + 5V, LX =
GND = 0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.
The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN. TYP. MAX. UNITS
CONDITIONS
QUIESCENT CURRENT
VCC Supply Current (No switching)
VCC Supply Current (switching)
BST Supply Current (No switching)
BST Supply Current (switching)
1.5
16
0.2
8
3
mA
mA
mA
mA
VFB =0.9V
VFB =0.9V
♦
♦
TBD
0.4
TBD
PROTECTION: UVLO
VCC UVLO Start Threshold
VCC UVLO Hysteresis
UVIN Start Threshold
UVIN Hysteresis
4.00
100
2.3
4.25
200
2.5
4.5
300
2.65
400
1
V
mV
V
♦
200
300
mV
µA
UVIN Input Current
UVIN= 3.0V
ERROR AMPLIFIER REFERENCE
2X Gain Config., Measure
VFB; VCC =5 V, T=25ºC
Error Amplifier Reference
0.792
0.788
0.800
0.800
0.808
0.812
V
V
Error Amplifier Reference
Over Line and Temperature
♦
Error Amplifier Transconductance
Error Amplifier Gain
6
60
150
150
50
4
mA/V
dB
No Load
COMP Sink Current
µA
VFB =0.9V, COMP= 0.9V
VFB =0.7V, COMP= 2.2V
VFB = 0.8V
COMP Source Current
VFB Input Bias Current
Internal Pole
µA
200
nA
MHz
V
COMP Clamp
2.5
-2
VFB =0.7V, TA=25ºC
COMP Clamp Temp. Coefficient
mV/ºC
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
2
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C<Tj<125°C, 4.5V < VCC < 5.5V, 3V<Vin<20V, BST=LX + 5V, LX =
GND = 0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.
The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN. TYP. MAX. UNITS
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Amplitude
RAMP Offset
0.92
1.1
1.1
1.28
V
V
TA = 25ºC, RAMP COMP
until GH starts Switching
RAMP Offset Temp. Coefficient
GH Minimum Pulse Width
-2
mV/ºC
ns
♦
♦
90
180
Maximum Duty Ratio
Measured just before
pulsing begins
Maximum Controllable Duty Ratio
92
97
%
Maximum Duty Ratio
100
810
%
Valid for 20 cycles
Internal Oscillator Ratio
900
10
990
0.3
kHz
TIMERS: SOFTSTART
SS Charge Current:
µA
♦
♦
SS Discharge Current:
1
mA
Fault Present, SS = 0.2V
PROTECTION: Short Circuit & Thermal
Measured VREF (0.8V) -
VFB
Short Circuit Threshold Voltage
Hiccup Timeout
0.2
0.25
200
20
V
ms
VFB = 0.5V
Number of Allowable Clock Cycles
at 100% Duty Cycle
Cycles
Minimum GL Pulse After 20 Cycles
Thermal Shutdown Temperature
Thermal Recovery Temperature
Thermal Hysteresis
0.5
145
135
10
Cycles
ºC
VFB = 0.7V
VFB = 0.7V
ºC
ºC
OUTPUT: POWER STAGE
VCC = 5V ; I
= 3A
= 3A
TAMB = 25ºCOUT
High Side RDSON
40
40
mΩ
VCC = 5V ; I
TAMB = 25ºCOUT
Synchronous FET RDSON
Maximum Output Current
mΩ
3
A
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
3
PIN DESCRIPTION
Pin #
Pin Name
Description
1-3
PGND
Ground connection for the synchronous rectifier
Ground Pin. The control circuitry of the IC and lower power driver are
referenced to this pin. Return separately from other ground traces to the (-)
terminal of Cout.
4,8,19-21
5
GND
VFB
Feedback Voltage and Short Circuit Detection pin. It is the inverting input
of the Error Amplifier and serves as the output voltage feedback point for
the Buck Converter. The output voltage is sensed and can be adjusted
through an external resistor divider. Whenever V drops 0.25V below the
positive reference, a short circuit fault is detectedFaBnd the IC enters hiccup
mode.
Output of the Error Amplifier. It is internally connected to the inverting input
of the PWM comparator. An optimal filter combination is chosen and
connected to this pin and either ground or VFB to stabilize the voltage
mode loop.
6
COMP
UVLO input for Vin voltage. Connect a resistor divider between VIN and
UVIN to set minimum operating voltage
7
9
UVIN
SS
Soft Start. Connect an external capacitor between SS and GND to set the
soft start rate based on the 10µA source current. The SS pin is held low
via a 1mA (min) current during all fault conditions.
Input connection to the high side N-channel MOSFET. Place a decoupling
capacitor between this pin and PGND.
10-13
VIN
14-16,23-26
LX
VCC
NC
Connect an inductor between this pin and VOUT
Input for external 5V bias supply
No Connect
22
17
THEORY OF OPERATION
General Overview
The SP7651 is a fixed frequency, voltage mode,
synchronousPWMregulatoroptimizedforhigh
efficiency. The part has been designed to be
especially attractive for split plane applications
utilizing 5V to power the controller and 2.5V to
28V for step down conversion.
The SP7651 contains two unique control fea-
tures that are very powerful in distributed appli-
cations. First, asynchronous driver control is
enabled during start up, to prohibit the low side
NFET from pulling down the output until the
high side NFET has attempted to turn on. Sec-
ond, a 100% duty cycle timeout ensures that the
low side NFET is periodically enhanced during
extended periods at 100% duty cycle. This guar-
antees the synchronized refreshing of the BST
capacitor during very large duty ratios.
The heart of the SP7651 is a wide bandwidth
transconductance amplifier designed to accom-
modate Type II and Type III compensation
schemes. Aprecision0.8Vreference, presenton
the positive terminal of the error amplifier per-
mits the programming of the output voltage
down to 0.8V via the VFB pin. The output of the
error amplifier, COMP, which is compared to a
1.1V peak-to-peak ramp is responsible for trail-
ing edge PWM control. This voltage ramp, and
PWM control logic are governed by the internal
oscillator that accurately sets the PWM fre-
quency to 900kHz.
The SP7651 also contains a number of valuable
protection features. Programmable UVLO al-
lows the user to set the exact VIN value at which
the conversion voltage can safely begin down
conversion, and an internal VCC UVLO ensures
that the controller itself has enough voltage to
properly operate. Other protection features in-
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
4
THEORY OF OPERATION
Thermal and Short-Circuit
Protection
clude thermal shutdown and short-circuit detec-
tion. In the event that either a thermal, short-
circuit, orUVLOfaultisdetected, theSP7651is
forced into an idle state where the output drivers
are held off for a finite period before a re-start is
attempted.
Because the SP7651 is designed to drive large
output current, there is a chance that the power
converter will become too hot. Therefore, an
internal thermal shutdown (145°C) has been
included to prevent the IC from malfunctioning
at extreme temperatures.
Soft Start
“Soft Start” is achieved when a power converter
ramps up the output voltage while controlling
the magnitude of the input supply source cur-
rent. In a modern step down converter, ramping
up the positive terminal of the error amplifier
controls soft start. As a result, excess source
current can be defined as the current required to
charge the output capacitor.
A short-circuit detection comparator has also
been included in the SP7651 to protect against
an accidental short at the output of the power
converter. This comparator constantly monitors
the positive and negative terminals of the error
amplifier, and if the VFB pin falls more than
250mV (typical) below the positive reference, a
short-circuit fault is set. Because the SS pin
overridestheinternal0.8Vreferenceduringsoft
start, the SP7651 is capable of detecting short-
circuit faults throughout the duration of soft
start as well as in regular operation.
I
VIN = COUT * (DVOUT / DTSOFT-START)
The SP7651 provides the user with the option to
program the soft start rate by tying a capacitor
from the SS pin to GND. The selection of this
capacitor is based on the 10uA pull up current
present at the SS pin and the 0.8V reference
voltage. Therefore, the excess source can be
redefined as:
Handling of Faults:
Upon the detection of power (UVLO), thermal,
or short-circuit faults, the SP7651 is forced into
an idle state where the SS and COMP pins are
pulled low and the NFETS are held off. In the
eventofUVLOfault, theSP7651remainsinthis
idle state until the UVLO fault is removed.
Upon the detection of a thermal or short-circuit
fault, an internal 200ms timer is activated. In the
event of a short-circuit fault, a re-start is at-
tempted immediately after the 200ms timeout
expires. Whereas, when a thermal fault is de-
tected the 200ms delay continuously recycles
and a re-start cannot be attempted until the
thermal fault is removed and the timer expires.
I
VIN = COUT * (DVOUT *10µA / (CSS * 0.8V)
Under Voltage Lock Out (UVLO)
The SP7651 contains two separate UVLO com-
parators to monitor the internal bias (VCC) and
conversion (VIN) voltages independently. The
VCC UVLO threshold is internally set to 4.25V,
whereas the VIN UVLO threshold is program-
mable through the UVIN pin. When the UVIN
pinisgreaterthan2.5V, theSP7651ispermitted
to start up pending the removal of all other
faults. Both the VCC and VIN UVLO compara-
tors have been designed with hysteresis to pre-
vent noise from resetting a fault.
Error Amplifier and Voltage Loop
Since the heart of the SP7651 voltage error loop
is a high performance, wide bandwidth
transconductance amplifier great care should be
taken to select the optimal compensation net-
work. Because of the amplifier’s current lim-
ited (+/-150µA) transconductance, there are
many ways to compensate the voltage loop or to
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
5
THEORY OF OPERATION
control the COMP pin externally. If a simple,
single pole, single zero response is desired, then
compensation can be as simple as an RC to
ground. If a more complex compensation is
required, then the amplifier has enough band-
width (45° at 4 MHz) and enough gain (60dB) to
run Type III compensation schemes with ad-
equate gain and phase margins at cross over
frequencies greater than 50kHz.
V
BST
GH
Voltage
V
SWN
V(V
CC)
GL
Voltage
0V
V(V
)
IN
SWN
The common mode output of the error amplifier
is 0.9V to 2.2V. Therefore, the PWM voltage
ramp has been set between 1.1V and 2.2V to
ensureproper0%to100%dutycyclecapability.
The voltage loop also includes two other very
importantfeatures.Oneisasynchronousstartup
mode. Basically, the synchronous rectifier can
not turn on unless the high side NFET has
attempted to turn on or the SS pin has exceeded
1.7V. This feature prevents the controller from
“dragging down” the output voltage during
startup or in fault modes. The second feature is
a100%dutycycletimeoutthatensuressynchro-
nized refreshing of the BST capacitor at very
high duty ratios. In the event that the high side
NFET is on for 20 continuous clock cycles, a
reset is given to the PWM flip flop half way
through the 21st cycle. This forces GL to rise for
the cycle, in turn refreshing the BST capacitor.
Voltage
-0V
-V(Diode) V
V(V )+V(V
IN
)
CC
BST
Voltage
V(V
)
CC
TIME
Setting Output Voltages
The SP7651 can be set to different output
voltages. The relationship in the following
formula is based on a voltage divider from the
output to the feedback pin VFB, which is set
to an internal reference voltage of 0.80V.
Standard 1% metal film resistors of surface
mount size 0603 are recommended.
Power MOSFETs
The SP7651 contains a pair of integrated low
resistance N MOSFETs designed to drive up to
3A of output current. Maximum output current
could be limited by thermal limitations of a
particular application. The SP7651 incorpo-
rates a built-in over-temperature protection to
prevent internal overheating.
Vout = 0.80V ( R1 / R2 + 1 ) => R2 = R1 / [ (
Vout / 0.80V ) – 1 ]
Where R1 = 68.1KΩ and for Vout = 0.80V
setting, simply remove R2 from the board.
Furthermore, one could select the value of R1
and R2 combination to meet the exact output
voltage setting by restricting R1 resistance
range such that 50KΩ < R1 < 100KΩ for
overall system loop stability.
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
6
APPLICATIONS INFORMATION
saturate at the peak inductor current
Inductor Selection
There are many factors to consider in selecting
the inductor including core material, inductance
vs. frequency, current handling capability, effi-
ciency, size and EMI. In a typical SP7651 cir-
cuit, the inductor is chosen primarily by operat-
ing frequency, saturation current and DC resis-
tance. Increasing the inductor value will de-
crease output voltage ripple, but degrade tran-
sient response. Low inductor values provide the
smallest size, but cause large ripple currents,
poor efficiency and more output capacitance to
smooth out the larger ripple current. The induc-
tor must be able to handle the peak current at the
switching frequency without saturating, and the
copper resistance in the winding should be kept
as low as possible to minimize resistive power
loss. A good compromise between size, loss and
cost is to set the inductor ripple current to be
within 20% to 40% of the maximum output
current.
IPP
IPEAK = IOUT (max)
+
2
and provide low core loss at the high switching
frequency. Low cost powdered iron cores are
inappropriate for 900kHz operation. Gapped
ferriteinductorsarewidelyavailableforconsid-
eration. Select devices that have operating data
shown up to 1MHz. Ferrite materials, on the
other hand, are more expensive and have an
abrupt saturation characteristic with the induc-
tance dropping sharply when the peak design
current is exceeded. Nevertheless, they are pre-
ferred at high switching frequencies because
they present very low core loss and the design
only needs to prevent saturation. In general,
ferrite or molyperm alloy materials will be used
with the SP7651.
Optimizing Efficiency
The switching frequency and the inductor oper-
ating point determine the inductor value as fol-
lows:
The power dissipated in the inductor is equal to
the sum of the core and copper losses. To mini-
mizecopperlosses,thewindingresistanceneeds
to be minimized, but this usually comes at the
expense of a larger inductor. Core losses have a
more significant contribution at low output cur-
rent where the copper losses are at a minimum,
and can typically be neglected at higher output
currentswherethecopperlossesdominate.Core
loss information is usually available from the
magnetic vendor. Proper inductor selection can
affect the resulting power supply efficiency by
more than 15-20%!
VOUT (VIN (max) −VOUT
)
L =
VIN (max) FS Kr IOUT (max)
where:
Fs = switching frequency
Kr = ratio of the ac inductor ripple current to the
maximum output current
Thecopperlossintheinductorcanbecalculated
using the following equation:
The peak to peak inductor ripple current is:
PL(Cu) = IL2(RMS) RWINDING
VOUT (VIN (max) −VOUT
)
IPP
=
where IL(RMS) is the RMS inductor current that
can be calculated as follows:
VIN(max) FS L
2
1
3
IPP
IOUT(max)
IL(RMS) = IOUT(max) 1 +
Once the required inductor value is selected, the
proper selection of core material is based on
peak inductor current and efficiency require-
ments. The core must be large enough not to
(
)
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
7
APPLICATIONS INFORMATION
Output Capacitor Selection
The required ESR (Equivalent Series Resis-
tance) and capacitance drive the selection of the
type and quantity of the output capacitors. The
ESR must be small enough that both the resis-
tive voltage deviation due to a step change in the
load current and the output ripple voltage do not
exceed the tolerance limits expected on the
output voltage. During an output load transient,
the output capacitor must supply all the addi-
tional current demanded by the load until the
SP7651 adjusts the inductor current to the new
value.
FS = Switching Frequency
D = Duty Cycle
COUT = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for ripple
current rating, capacitance and voltage rating.
The input capacitor must meet the ripple current
requirement imposed by the switching current.
In continuous conduction mode, the source cur-
rent of the high-side MOSFET is approximately
a square wave of duty cycle VOUT/VIN. Most of
this current is supplied by the input bypass
capacitors. The RMS value of input capacitor
current is determined at the maximum output
current and under the assumption that the peak
In order to maintain VOUT, the capacitance must
belargeenoughsothattheoutputvoltageisheld
up while the inductor current ramps up or down
to the value corresponding to the new load
current. Additionally, the ESR in the output
capacitor causes a step in the output voltage
equaltothecurrent. Becauseofthefasttransient
response and inherent 100% and 0% duty cycle
capability provided by the SP7651 when ex-
posed to output load transient, the output ca-
pacitor is typically chosen for ESR, not for
capacitance value.
to peak inductor ripple current is low, it is given
by:
ICIN(rms) = I
OUT(max) √D(1 - D)
The worse case occurs when the duty cycle D is
50% and gives an RMS current value equal to
I
OUT/2.
The output capacitor’s ESR, combined with the
inductor ripple current, is typically the main
contributor to output voltage ripple. The maxi-
mum allowable ESR required to maintain a
specifiedoutputvoltageripplecanbecalculated
by:
Select input capacitors with adequate ripple
current rating to ensure reliable operation.
The power dissipated in the input capacitor is:
P
= IC2IN (rms) RESR(CIN)
CIN
RESR ≤ ∆VOUT
IPK-PK
This can become a significant part of power
losses in a converter and hurt the overall energy
transfer efficiency. The input voltage ripple
primarily depends on the input capacitor ESR
and capacitance. Ignoring the inductor ripple
current, the input voltage ripple can be deter-
mined by:
where:
∆VOUT = Peak to Peak Output Voltage Ripple
IPK-PK = Peak to Peak Inductor Ripple Current
The total output ripple is a combination of the
ESR and the output capacitance value and can
be calculated as follows:
2 + (IPPRESR
)
IPP (1 – D)
2
∆VOUT
=
COUTFS
(
)
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
8
APPLICATIONS INFORMATION
High cross over frequency is desirable for fast
transient response, but often jeopardizes the
system stability. Cross over frequency should
be higher than the ESR zero but less than 1/5 of
the switching frequency. The ESR zero is con-
tributed by the ESR associated with the output
capacitors and can be determined by:
I
OUT (MAX )VOUT (VIN −VOUT )
∆VIN = Iout(max) RESR(CIN )
+
2
FSCINVIN
The capacitor type suitable for the output capac-
itors can also be used for the input capacitors.
However, exercise extra caution when tantalum
capacitorsareused.Tantalumcapacitorsareknown
for catastrophic failure when exposed to surge
current, and input capacitors are prone to such
surge current when power supplies are connected
“live” to low impedance power sources.
1
ƒZ(ESR)
=
2π COUT RESR
Loop Compensation Design
The next step is to calculate the complex conju-
gate poles contributed by the LC output filter,
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross
over at the selected frequency FCO, the gain of
the error amplifier has to compensate for the
attenuation caused by the rest of the loop at this
frequency.
1
ƒP(LC)
=
2π L COUT
When the output capacitors are of a Ceramic
Type, the SP7651 Evaluation Board requires a
Type III compensation circuit to give a phase
boostof180°inordertocounteracttheeffectsof
an under damped resonance of the output filter
at the double pole frequency.
The goal of loop compensation is to manipulate
loop frequency response such that its gain
crossesover 0db at a slope of -20db/dec. The
first step of compensation design is to pick the
loop cross over frequency.
Type III Voltage Loop
Compensation
GAMP (s) Gain Block
PWM Stage
GPWM Gain
Block
Output Stage
GOUT (s) Gain
Block
VIN
(SRz2Cz2+1)(SR1Cz3+1)
(SRESRCOUT+ 1)
+
VREF
(Volts)
VOUT
(Volts)
_
VRAMP_PP
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
[S^2LCOUT+S(RESR+RDC) COUT+1]
Notes: RESR = Output Capacitor Equivalent Series Resistance.
DC = Output Inductor DC Resistance.
R
VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> RESR & RDC
Voltage Feedback
G
FBK Gain Block
R2
(R1 R2)
VREF
VOUT
or
+
VFBK
(Volts)
SP7651 Voltage Mode Control Loop with Loop Dynamic
Definitions:
R
R
R
ESR = Output Capacitor Equivalent Series Resistance
DC = Output Inductor DC Resistance
RAMP_PP = SP7651 internal RAMP Amplitude Peak to Peak Voltage
Conditions:
CZ 2 >> Cp1 and R1 >> RZ 3
Output Load Resistance >> RESR and RDC
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
9
APPLICATIONS INFORMATION
Gain
(dB)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
20 Log (RZ2/R1)
Frequency
(Hz)
Bode Plot of Type III Error Amplifier Compensation.
CP1
RZ2
CZ2
RZ3
CZ3
V
OUT
5
-
+
R1
6
VFB
68.1k, 1%
COMP
R
SET
CF1
+
0.8V
-
R
-0.8)
(kΩ)
=54.48/ (V
OUT
SET
Type III Error Amplifier Compensation Circuit
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
10
PACKAGE: 26 PIN DFN
D
(7 x 4 mm)
E
Top View
A
A3
A1
Side View
b
e
L
E2
DIMENSIONS in
26 Pin DFN
D2
D2
(mm)
D3
SYMBOL
MIN
MAX
NOM
0.800 0.850 0.900
0.000
0.178 0.203 0.228
0.17
6.95 7.00 7.05
2.05 2.10
A
0.050
-
A1
A3
b
Bottom View
0.22
0.27
D
2.00
D2
D3
e
1.78 1.83 1.88
0.45 0.50 0.55
3.95 4.00 4.05
E
E2
L
2.830
2.780
2.730
0.350 0.400 0.450
26 Pin DFN
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
11
ORDERING INFORMATION
Package
Part Number
Temperature
SP7651ER/TR.........................................-40°C to +85°C ................................. 26 Pin 7 X 4 DFN
SP7651ER-L/TR .....................................-40°C to +85°C ............. (Lead Free) 26 Pin 7 X 4 DFN
/TR = Tape and Reel
Pack quantity is 3000 DFN.
Corporation
ANALOGEXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 08/25/04
SP7651 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2004 Sipex Corporation
12
相关型号:
SP7651ER-L/TR
Switching Regulator, Voltage-mode, 5A, 990kHz Switching Freq-Max, PDSO26, 7 X 4 MM, ROHS COMPLIANT, DFN-26
EXAR
SP7652ER-L
Switching Regulator, Voltage-mode, 10A, 720kHz Switching Freq-Max, PDSO26, 7 X 4 MM, LEAD FREE, DFN-26
SIPEX
©2020 ICPDF网 联系我们和版权申明