SP7653ER-L/TR [SIPEX]
Wide Input Voltage Range, 1.3MHz,Buck Regulator; 宽输入电压范围, 1.3MHz ,降压型稳压器型号: | SP7653ER-L/TR |
厂家: | SIPEX CORPORATION |
描述: | Wide Input Voltage Range, 1.3MHz,Buck Regulator |
文件: | 总12页 (文件大小:206K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
Preliminary
SP7653
TM
Wide Input Voltage Range, 1.3MHz,
Buck Regulator
Power
Blox
FEATURES
SP7653
DFN PACKAGE
■ 2.5V to 20V Step Down Achieved Using Dual Input
■ Output Voltage down to 0.8V
7mm x 4mm
P
P
GND
GND
GND
1
2
3
26
25
24
23
LX
LX
LX
TOP VIEW
■ 3A Output Capability
Heatsink Pad 1
Connect to Lx
■ Built in Low RDSON Power Switches (40 mΩ typical)
■ Highly Integrated Design, Minimal Components
■ 1.3MHz Fixed Frequency Operation
■ UVLO Detects Both VCC and VIN
P
GND
4
5
LX
V
FB
22 V
CC
COMP
UVIN
GND
SS
21 GND
20 GND
6
7
Heatsink pad 2
Connect to GND
■ Over Temperature Protection
8
9
19
18
GND
BST
■ Short Circuit Protection with Auto-Restart
■ Wide BW Amp Allows Type II or III Compensation
■ Programmable Soft Start
V
IN 10
17
16
NC
LX
Heatsink pad 3
V
V
V
IN 11
IN 12
Connect to V
IN
■ Fast Transient Response
15 LX
14
■ High Efficiency: Greater than 95% Possible
■ Asynchronous Start-Up into a Pre-Charged Output
■ Small 7mm x 4mm DFN Package
LX
IN 13
Now Available in Lead Free Packaging
DESCRIPTION
The SP7653 is a synchronous step-down switching regulator optimized for high efficiency. The part is designed to be
especially attractive for dual supply, 12V to 20V distributed power systems stepped down with 5V used to power the
controller.ThislowerVCC voltageminimizespowerdissipationinthepartandisusedtodrivethetopswitch.TheSP7653
is designed to provide a fully integrated buck regulator solution using a fixed 1.3MHz frequency, PWM voltage mode
architecture. Protection features include Under Voltage Lock Out (UVLO), thermal shutdown and output short circuit
protection. The SP7653 is available in the space saving DFN package.
TYPICAL APPLICATION CIRCUIT
L1: IHLP2525CZER2R2M01
U1
2.2uH, Irate=8A
SP7653
DCR=18mOhm
1
2
26
25
PGND
PGND
LX
LX
VOUT
3.30V
C3
CERAMIC
X5R
RZ2
CZ2
C3
RZ3
158,1%
3
4
5
24
23
22
0-3A
R1
68.1k,1%
PGND
GND
LX
LX
38.3k, 1%
1.5nF
47uF
6.3V
CP1
CZ3
820pF
VFB
VCC
GND
3.3pF
6
7
8
21
20
19
COMP
CVCC
2.2uF
CF1
100pF
UVIN
GND
SS
GND
GND
BST
GND2
9
18
17
16
R2
21.5k,1%
10
RBST
5.11, 1%
CSS
22nF
VIN
VIN
VIN
NC
LX
LX
11
DBST
SD101AWS
12
13
15
14
CBST
1uF
VIN
LX
VIN
12V
fs=1.3MHz
U2
SPX5205
R3
200k,1%
Notes:
C1,C5
CERAMIC
X5R
1
5
4
VIN VOUT
C1
22uF
16V
C5
U1 Bottom-Side Layout should have three
Contacts which are isolated from one
2
3
GND
22uF
16V
EN
BYP
another: QT Contact, QB Drain Contact, and
R4
100k,1%
C2
0.1uF
Controller GND Contact.
ALL RESISTORS & CAPACITORS SIZE 0603 UNLESS
OTHERWISE SPECIFIED.
GND
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect reliability.
GH ....................................................................... -0.3V to Boost+0.3V
GH-SWN ......................................................................................... 7V
All other pins .......................................................... -0.3V to VCC+0.3V
VCC .................................................................................................. 7V
VIN ........................................................................................................................................... 20V
ILX ............................................................................................................................................... 5A
Boost ............................................................................................. 27V
Boost-SWN ....................................................................... -0.3V to 7V
SWN ................................................................................... -1V to 20V
Storage Temperature .................................................. -65°C to 150°C
Power Dissipation ...................................... Internally Limited via OTP
ESD Rating .......................................................................... 2kV HBM
Thermal Resistance ϑ .................................................................................... 5°C/W
JC
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C< Tj< 125°C, 4.5V < VCC < 5.5V, 3V< Vin< 28V, Boost=LX + 5V,
LX = GND = 0Volts, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.
The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
QUIESCENT CURRENT
VCC Supply Current (No switching)
VCC Supply Current (switching)
BST Supply Current (No switching)
BST Supply Current (switching)
1.5
8
3
mA
mA
mA
mA
VFB =0.9V
VFB =0.9V
♦
♦
0.2
4.0
0.4
PROTECTION: UVLO
VCC UVLO Start Threshold
VCC UVLO Hysteresis
UVIN Start Threshold
UVIN Hysteresis
4.00
100
2.3
4.25
200
2.5
4.5
300
2.65
400
1
V
mV
V
♦
200
300
mV
µA
UVIN Input Current
UVIN= 3.0V
ERROR AMPLIFIER REFERENCE
2X Gain Config., Measure
VFB; VCC =5 V, T=25ºC
Error Amplifier Reference
0.792
0.788
0.800
0.800
0.808
0.812
V
V
Error Amplifier Reference
Over Line and Temperature
♦
Error Amplifier Transconductance
Error Amplifier Gain
6
60
150
150
50
4
mA/V
dB
No Load
COMP Sink Current
µA
VFB =0.9V, COMP= 0.9V
COMP Source Current
VFB Input Bias Current
Internal Pole
µA
VFB =0.7V, COMP= 2.2V
200
nA
VFB = 0.8V
MHz
V
COMP Clamp
2.5
-2
VFB =0.7V, TA=25ºC
COMP Clamp Temp. Coefficient
mV/ºC
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
2
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C< Tj< 125°C, 4.5V < VCC < 5.5V, 3V< Vin< 28V, Boost=LX + 5V,
LX = GND = 0Volts, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.
The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Amplitude
RAMP Offset
0.92
1.1
1.1
1.28
180
V
V
TA = 25ºC, RAMP COMP
until GH starts Switching
RAMP offset Temp. Coefficient
GH Minimum Pulse Width
-2
mV/ºC
ns
♦
♦
90
Maximum Duty Ratio
Measured just before
pulsing begins
Maximum Controllable Duty Ratio
92
97
%
Maximum Duty Ratio
Internal Oscillator Ratio
TIMERS: SOFTSTART
SS Charge Current:
100
1.1
%
Valid for 20 cycles
1.3
10
1.5
0.3
MHz
µA
♦
♦
SS Discharge Current:
1
mA
Fault Present, SS = 0.2V
PROTECTION: Short Circuit & Thermal
Measured VREF (0.8V) -
VFB
Short Circuit Threshold Voltage
Hiccup Timeout
0.2
0.25
200
20
V
ms
VFB = 0.5V
Number of Allowable Clock Cycles
at 100% Duty Cycle
Cycles
Minimum GL Pulse After 20 Cycles
Thermal Shutdown Temperature
Thermal Recovery Temperature
Thermal Hysteresis
0.5
145
135
10
Cycles
ºC
VFB = 0.7V
VFB = 0.7V
ºC
ºC
OUTPUT: POWER STAGE
V
= 5V ; I
= 3A
= 3A
TACMCB = 25ºCOUT
High Side Switch RDSON
40
40
mΩ
VCC = 5V ; I
TAMB = 25ºCOUT
Synchronous Lowside Switch RDSON
Maximum Output Current
mΩ
3
A
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
3
PIN DESCRIPTION
Pin #
Pin Name
Description
1-3
PGND
Ground connection for the synchronous rectifier
Ground Pin. The control circuitry of the IC and lower power driver are
referenced to this pin. Return separately from other ground traces to the (-)
4,8,19-21
5
GND
VFB
terminal of COUT
.
Feedback Voltage and Short Circuit Detection pin. It is the inverting input
of the Error Amplifier and serves as the output voltage feedback point for
the Buck Converter. The output voltage is sensed and can be adjusted
through an external resistor divider. Whenever V drops 0.25V below the
positive reference, a short circuit fault is detectedFaBnd the IC enters hiccup
mode.
Output of the Error Amplifier. It is internally connected to the inverting input
of the PWM comparator. An optimal filter combination is chosen and
connected to this pin and either ground or VFB to stabilize the voltage
mode loop.
6
COMP
UVLO input for Vin voltage. Connect a resistor divider between VIN and
UVIN to set minimum operating voltage.
7
9
UVIN
SS
Soft Start. Connect an external capacitor between SS and GND to set the
soft start rate based on the 10µA source current. The SS pin is held low
via a 1mA (min) current during all fault conditions.
Input connection to the high side N-channel MOSFET. Place a decoupling
10-13
VIN
capacitor between this pin and PGND
.
14-16,23-26
17
LX
Connect an inductor between this pin and VOUT
No Connect
NC
THEORY OF OPERATION
General Overview
The SP7653 is a fixed frequency, voltage mode,
synchronousPWMregulatoroptimizedforhigh
efficiency. The part has been designed to be
especially attractive for high input voltages of
2.5V to 20V.
The SP7653 contains two unique control fea-
tures that are very powerful in distributed appli-
cations. First, asynchronous driver control is
enabled during start up, to prohibit the low side
switch from pulling down the output until the
high side switch has attempted to turn on. Sec-
ond, a 100% duty cycle timeout ensures that the
low side switch is periodically enhanced during
extended periods at 100% duty cycle. This guar-
antees the synchronized refreshing of the Boost
capacitor during very large duty ratios.
The heart of the SP7653 is a wide bandwidth
transconductance amplifier designed to accom-
modate Type II and Type III compensation
schemes. Aprecision0.8Vreference, presenton
the positive terminal of the error amplifier per-
mits the programming of the output voltage
down to 0.8V via the VFB pin. The output of the
error amplifier, COMP, compared to a 1.1V
peak-to-peak ramp is responsible for trailing
edge PWM control. This voltage ramp, and
PWM control logic are governed by the internal
oscillator that accurately sets the PWM fre-
quency to 1.3MHz.
The SP7653 also contains a number of valuable
protection features. Programmable VIN UVLO
allowstheusertosettheexactvalueatwhichthe
conversion voltage can safely begin down con-
version, and an internal VCC UVLO which en-
sures that the controller itself has enough volt-
age to properly operate. Other protection fea-
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
4
THEORY OF OPERATION
Thermal and Short-Circuit
tures include thermal shutdown and short-cir-
cuit detection. In the event that either a thermal,
short-circuit, or UVLO fault is detected, the
SP7653 is forced into an idle state where the
output drivers are held off for a finite period
before a restart is attempted.
Protection
Because the SP7653 is designed to drive large
output current, there is a chance that the power
converter will become too hot. Therefore, an
internal thermal shutdown (145°C) has been
included to prevent the IC from malfunctioning
at extreme temperatures.
Soft Start
“Soft Start” is achieved when a power converter
ramps up the output voltage while controlling
the magnitude of the input supply source cur-
rent. In a modern step down converter, ramping
up the positive terminal of the error amplifier
controls soft start. As a result, excess source
current can be defined as the current required to
charge the output capacitor:
A short-circuit detection comparator has also
been included in the SP7653 to protect against
an accidental short at the output of the power
converter. This comparator constantly monitors
the positive and negative terminals of the error
amplifier, and if the VFB pin falls more than
250mV (typical) below the positive reference, a
short-circuit fault is set. Because the SS pin
overridestheinternal0.8Vreferenceduringsoft
start, the SP7653 is capable of detecting short-
circuit faults throughout the duration of soft
start as well as in regular operation.
I
VIN = COUT * (DVOUT / DTSOFT-START)
The SP7653 provides the user with the option to
program the soft start rate by tying a capacitor
from the SS pin to GND. The selection of this
capacitor is based on the 10uA pull up current
present at the SS pin and the 0.8V reference
voltage. Therefore, the excess source can be
redefined as:
Handling of Faults:
Upon the detection of power (UVLO), thermal,
or short-circuit faults, the SP7653 is forced into
an idle state where the SS and COMP pins are
pulled low and both switches are held off. In the
eventofUVLOfault, theSP7653remainsinthis
idle state until the UVLO fault is removed.
Upon the detection of a thermal or short-circuit
fault, aninternal200ms timerisactivated. Inthe
event of a short-circuit fault, a re-start is at-
tempted immediately after the 200ms timeout
expires. Whereas, when a thermal fault is de-
tected the 200ms delay continuously recycles
and a re-start cannot be attempted until the
thermal fault is removed and the timer expires.
IVIN = COUT *[ (DVOUT *10µA) /(CSS * 0.8V)]
Under Voltage Lock Out (UVLO)
The SP7653 contains two separate UVLO com-
parators to monitor the bias (VCC) and conver-
sion (VIN) voltages independently. The VCC
UVLO threshold is internally set to 4.25V,
whereas the VIN UVLO threshold is program-
mable through the UVIN pin. When the voltage
ontheUVIN pinisgreaterthan2.5V,theSP7653
is permitted to start up pending the removal of
all other faults. Both the VCC and VIN UVLO
comparatorshavebeendesignedwithhysteresis
to prevent noise from resetting a fault.
Error Amplifier and Voltage Loop
The heart of the SP7653 voltage error loop
compensationisahighperformance,wideband-
width transconductance amplifier. Because of
the amplifier’s current limited (+/-150µA)
transconductance, there are many ways to com-
pensate the voltage loop or to control the COMP
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
5
THEORY OF OPERATION
pin externally. If a simple, single pole-single
zero response is desired, then compensation can
beassimpleasanRCcircuittoground. Ifamore
complex compensation is required, then the
amplifier has enough bandwidth (45° at 4 MHz)
andenoughgain(60dB)torunTypeIIIcompen-
sation schemes with adequate gain and phase
margins at cross over frequencies greater than
50kHz.
V
BST
GH
Voltage
V
SWN
V(V
CC)
GL
Voltage
0V
V(V
)
IN
SWN
The common mode output of the error amplifier
is 0.9V to 2.2V. Therefore, the PWM voltage
ramp has been set between 1.1V and 2.2V to
ensureproper0%to100%dutycyclecapability.
The voltage loop also includes two other very
importantfeatures. Oneisanasynchronousstart
up mode. Basically, the synchronous rectifier
cannot turn on unless the high side switch has
attempted to turn on or the SS pin has exceeded
1.7V. This feature prevents the controller from
“dragging down” the output voltage during
startup or in fault modes. The second feature is
a100%dutycycletimeoutthatensuressynchro-
nized refreshing of the Boost capacitor at very
high duty ratios. In the event that the high side
NFET is on for 20 continuous clock cycles, a
reset is given to the PWM flip flop half way
through the 21st cycle. This forces GL to rise for
the cycle, in turn refreshing the Boost capacitor.
The boost capacitor is used to generate a high
voltage drive supply for the high side switch,
which is 5V above VIN.
Voltage
-0V
-V(Diode) V
V(V )+V(V
IN
)
CC
BST
Voltage
V(V
)
CC
TIME
Setting Output Voltages
The SP7653 can be set to different output
voltages. The relationship in the following
formula is based on a voltage divider from the
output to the feedback pin VFB, which is set to
an internal reference voltage of 0.80V.
Standard 1% metal film resistors of surface
mount size 0603 are recommended.
Vout = 0.80V ( R1 / R2 + 1 ) =>
R2 = R1 / [ ( Vout / 0.80V ) – 1 ]
Power MOSFETs
The SP7653 contains a pair of integrated low
resistance N-channel switches designed for up
to 3A. Care should be taken to de-rate the output
current based on the thermal conditions in the
system such as ambient temperature, airflow
andheatsinking.Maximumoutputcurrentcould
be limited by thermal limitations of a particular
application by taking advantage of the inte-
grated-over-temperatureprotectiveschemeem-
ployedintheSP7653. TheSP7653incorporates
a built-in overtemperature protection to prevent
internal overheating.
Where R1 = 68.1KΩ and for Vout = 0.80V
setting, simply remove R2 from the board.
Furthermore, one could select the value of the
R1 and R2 combination to meet the exact
output voltage setting by restricting the
resistance range of R1 such that 50KΩ < R1
< 100KΩ for overall system loop stability.
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
6
APPLICATIONS INFORMATION
Inductor Selection
IPP
There are many factors to consider in selecting
the inductor including core material, inductance
vs. frequency, current handling capability, effi-
ciency, size and EMI. In a typical SP7653 cir-
cuit, the inductor is chosen primarily for value,
saturationcurrentandDCresistance. Increasing
the inductor value will decrease output voltage
ripple, but degrade transient response. Low in-
ductor values provide the smallest size, but
cause large ripple currents, poor efficiency and
moreoutputcapacitancetosmoothoutthelarger
ripple current. The inductor must be able to
handle the peak current at the switching fre-
quency without saturating, and the copper resis-
tance in the winding should be kept as low as
possible to minimize resistive power loss. A
good compromise between size, loss and cost is
to set the inductor ripple current to be within
20% to 40% of the maximum output current.
IPEAK = IOUT (max)
+
2
and provide low core loss at the high switching
frequency. Low cost powdered iron cores have
a gradual saturation characteristic but can intro-
duceconsiderableACcoreloss,especiallywhen
the inductor value is relatively low and the
ripplecurrentishigh.Ferritematerials,although
more expensive, have an abrupt saturation char-
acteristic with the inductance dropping sharply
when the peak design current is exceeded. Nev-
ertheless, they are preferred at high switching
frequencies because they present very low core
loss while the designer is only required to
prevent saturation. In general, ferrite or
molypermalloy materials are a better choice for
all but the most cost sensitive applications.
The switching frequency and the inductor oper-
ating point determine the inductor value as fol-
lows:
Optimizing Efficiency
The power dissipated in the inductor is equal to
the sum of the core and copper losses. To mini-
mizecopperlosses,thewindingresistanceneeds
to be minimized, but this usually comes at the
expense of a larger inductor. Core losses have a
more significant contribution at low output cur-
rent where the copper losses are at a minimum,
and can typically be neglected at higher output
currentswherethecopperlossesdominate.Core
loss information is usually available from the
magnetic vendor. Proper inductor selection can
affect the resulting power supply efficiency by
more than 15%!
VOUT (VIN (max) −VOUT
)
L =
VIN (max) FS Kr IOUT (max)
where:
fS = switching frequency
Kr = ratio of the AC inductor ripple current to
the maximum output current
The peak to peak inductor ripple current is:
Thecopperlossintheinductorcanbecalculated
using the following equation:
VOUT (VIN (max) −VOUT
)
PL(Cu) = IL2(RMS) RWINDING
IPP
=
VIN(max) FS L
where IL(RMS) is the RMS inductor current that
can be calculated as follows:
Once the required inductor value is selected, the
proper selection of core material is based on
peak inductor current and efficiency require-
ments. The core must be large enough not to
saturate at the peak inductor current
2
1
3
IPP
IOUT(max)
IL(RMS) = IOUT(max) 1 +
(
)
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
7
APPLICATIONS INFORMATION
FS = Switching Frequency
D = Duty Cycle
OUT = Output Capacitance Value
Output Capacitor Selection
The required ESR (Equivalent Series Resis-
tance) and capacitance drive the selection of the
type and quantity of the output capacitors. The
ESR must be small enough that both the resis-
tive voltage deviation due to a step change in the
load current and the output ripple voltage do not
exceed the tolerance limits expected on the
output voltage. During an output load transient,
the output capacitor must supply all the addi-
tional current demanded by the load until the
SP7653 adjusts the inductor current to the new
value.
C
Input Capacitor Selection
The input capacitor should be selected for ripple
current rating, capacitance and voltage rating.
The input capacitor must meet the ripple current
requirement imposed by the switching current.
In continuous conduction mode, the source cur-
rent of the high-side MOSFET is approximately
a square wave of duty cycle VOUT/VIN. More
accurately the current wave form is trapezoidal,
given a finite turn-on and turn-off, switch tran-
sition slope. Most of this current is supplied by
the input bypass capacitors. The RMS current
handling capability of the input capacitors is
determined at maximum output current and
under the assumption that the peak-to-peak in-
ductor ripple current is low, it is given by:
In order to maintain VOUT ,the capacitance must
be large enough so that the output voltage is
helped up while the inductor current ramps to
the value corresponding to the new load current.
Additionally, the ESR in the output capacitor
causes a step in the output voltage equal to the
current. Because of the fast transient response
and inherent 100%/0% duty cycle capability
providedbytheSP7653whenexposedtooutput
load transient, the output capacitor is typically
chosen for ESR, not for capacitance value.
ICIN(RMS) = I
OUT(max) √D(1 - D)
The worse case occurs when the duty cycle D is
50% and gives an RMS current value equal to
I
OUT/2. Select input capacitors with adequate
The output capacitor’s ESR, combined with the
inductor ripple current, is typically the main
contributor to output voltage ripple. The maxi-
mum allowable ESR required to maintain a
specifiedoutputvoltageripplecanbecalculated
by:
ripple current rating to ensure reliable opera-
tion.
The power dissipated in the input capacitor is:
P
= IC2IN (rms) RESR(CIN)
CIN
RESR ≤ ∆VOUT
IPK-PK
This can become a significant part of power
losses in a converter and hurt the overall energy
transfer efficiency. The input voltage ripple
primarily depends on the input capacitor ESR
and capacitance. Ignoring the inductor ripple
current, the input voltage ripple can be deter-
mined by:
where:
∆VOUT = Peak to Peak Output Voltage Ripple
I
PK-PK = Peak to Peak Inductor Ripple Current
The total output ripple is a combination of the
ESR and the output capacitance value and can
be calculated as follows:
I
OUT (MAX )VOUT (VIN −VOUT )
∆VIN = Iout(max) RESR(CIN )
+
2
FSCINVIN
2 + (IPPRESR
)
IPP (1 – D)
2
∆VOUT
=
COUTFS
(
)
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
8
APPLICATIONS INFORMATION
The first step of compensation design is to pick
the loop cross over frequency. High cross over
frequencyisdesirableforfasttransientresponse,
but often jeopardizes the power supply stability.
Cross over frequency should be higher than the
ESR zero but less than 1/5 of the switching
frequency or 60kHz. The ESR zero is contrib-
uted by the ESR associated with the output
capacitors and can be determined by:
The capacitor type suitable for the output capac-
itors can also be used for the input capacitors.
However, exercise extra caution when tantalum
capacitorsareused.Tantalumcapacitorsareknown
for catastrophic failure when exposed to surge
current, and input capacitors are prone to such
surge current when power supplies are connected
“live” to low impedance power sources. Although
tantalum capacitors have been successfully em-
ployed at the input, it is generally not recom-
mended.
1
ƒZ(ESR)
=
2π COUT RESR
The next step is to calculate the complex conju-
gate poles contributed by the LC output filter,
Loop Compensation Design
1
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross
over at the desired frequency cut-off (FCO), the
gain of the error amplifier has to compensate for
the attenuation caused by the rest of the loop at
this frequency. The goal of loop compensation
is to manipulate loop frequency response such
that its cross-over gain at 0db, results in a slope
of -20db/dec.
ƒP(LC)
=
2π L COUT
When the output capacitors are of a Ceramic
Type, the SP7653 Evaluation Board requires a
Type III compensation circuit to give a phase
boostof180°inordertocounteracttheeffectsof
an under damped resonance of the output filter
at the double pole frequency.
Type III Voltage Loop
PWM Stage
GPWM Gain
Block
Output Stage
Compensation
G
OUT (s) Gain
GAMP (s) Gain Block
Block
VIN
(SRz2Cz2+1)(SR1Cz3+1)
(SRESRCOUT+ 1)
+
VREF
(Volts)
VOUT
(Volts)
_
VRAMP_PP
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
[S^2LCOUT+S(RESR+RDC) COUT+1]
Notes: RESR = Output Capacitor Equivalent Series Resistance.
DC = Output Inductor DC Resistance.
R
VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> RESR & RDC
Voltage Feedback
G
FBK Gain Block
R2
(R1 R2)
VREF
VOUT
or
+
VFBK
(Volts)
SP7653 Voltage Mode Control Loop with Loop Dynamic
Definitions:
R
R
R
ESR = Output Capacitor Equivalent Series Resistance
DC = Output Inductor DC Resistance
RAMP_PP = SP7653 internal RAMP Amplitude Peak to Peak Voltage
Conditions:
CZ2 >> Cp1 and R1 >> Rz3
Output Load Resistance >> RESR and RDC
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
9
APPLICATIONS INFORMATION
Gain
(dB)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
20 Log (RZ2/R1)
Frequency
(Hz)
Bode Plot of Type III Error Amplifier Compensation.
CP1
RZ2
CZ2
RZ3
CZ3
V
OUT
5
-
+
R1
6
VFB
68.1k, 1%
COMP
R
SET
CF1
+
0.8V
-
R
-0.8V)
(kΩ)
=54.48/ (V
SET
OUT
Type III Error Amplifier Compensation Circuit
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
10
PACKAGE: 26 PIN DFN
D
(7 x 4 mm)
Top View
E
A
A3
K
A1
Side View
e
b
L
E2
J
D2
D3
D2
26 Pin DFN
Bottom View
MIN
NOM
MAX
SYMBOL
A
A1
A3
b
0.800
0.000
0.178
0.170
6.950
2.000
1.780
0.850
-
0.900
0.050
0.228
0.270
7.050
2.100
1.880
0.203
0.220
7.000
2.050
1.830
0.500 BSC
4.000
2.780
0.390
0.250
0.400
D
D2
D3
e
E
E2
K
3.950
2.730
0.340
0.200
0.350
4.050
2.830
0.440
0.300
0.450
J
L
Note: Dimensions in (mm)
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
11
ORDERING INFORMATION
Package
Part Number
Temperature
SP7653ER/TR.........................................-40°C to +85°C ................................. 26 Pin 7 X 4 DFN
SP7653ER-L/TR .....................................-40°C to +85°C ............. (Lead Free) 26 Pin 7 X 4 DFN
/TR = Tape and Reel
Pack quantity is 3,000 DFN.
Corporation
ANALOGEXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
12
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