USB3450 [SMSC]
HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE; HI -SPEED USB主机或UTMI +接口的PHY设备
| 型号： | USB3450 |
| 厂家： | 
SMSC CORPORATION |
| 描述： | HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE |
| 文件： | 总40页 (文件大小：1089K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USB3450
Hi-Speed USB Host or
Device PHY With UTMI+
Interface
Datasheet
PRODUCT FEATURES
■ USB-IF “Hi-Speed” certified to the Universal Serial
■ Integrated 24MHz Crystal Oscillator supports either
Bus Specification Rev 2.0
crystal operation or 24MHz external clock input.
■ Interface compliant with the UTMI+ Specification,
■ Internal PLL for 480MHz Hi-Speed USB operation.
■ Supports Hi-Speed USB and legacy USB 1.1 devices
Revision 1.0.
■ Functional as a host or device PHY.
■ Supports HS, FS, and LS data rates.
■ 55mA Unconfigured Current (typical) - ideal for bus
powered applications.
■ Supports FS pre-amble for FS hubs with a LS device
■ 83uA suspend current (typical) - ideal for battery
attached (UTMI+ Level 3)
powered applications.
■ Supports HS SOF and LS keep alive pulse.
■ Full Commercial operating temperature range from
0°C to +70°C
■ Low Latency Hi-Speed Receiver (43 Hi-Speed clocks
Max)
■ 40 pin QFN package; green, lead-free (6 x 6 x 0.9mm
height)
■ Internal 1.8 volt regulators allow operation from a
single 3.3 volt supply
■ Internal short circuit protection of DP and DM lines to
VBUS or ground.
SMSC USB3450
DATASHEET
Revision 0.1 (05-11-05)
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
ORDER NUMBER(S): USB3450-FZG FOR 40 PIN, QFN PACKAGE (GREEN, LEAD-FREE)
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Copyright © 2005 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently,
complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be
accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any
time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this
information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual
property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may
contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other
application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written
approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other
SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a
registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective
holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE,
AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE
LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA,
PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT;
NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY
OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
Revision 0.1 (05-11-05)
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SMSC USB3450
DATASHEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
0.1
Reference Documents
■
■
■
Universal Serial Bus Specification, Revision 2.0, April 27, 2000
Hi-Speed Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000
UTMI+ Specification, Revision 1.0, February 2, 2004
SMSC USB3450
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Revision 0.1 (05-11-05)
DATASHEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
Table of Contents
0.1
Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 3 Pin Configuration and Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
USB3450 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 4 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 6 Detailed Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1
6.2
6.3
6.4
8bit Bi-Directional Data Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Hi-Speed Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.1
6.4.2
6.4.3
High Speed and Full Speed Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5
6.6
Crystal Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6.1
6.6.2
Internal Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 7 Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Linestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
OPMODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Test Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SE0 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Suspend Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
HS Detection Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
HS Detection Handshake – FS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
HS Detection Handshake – HS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.10 HS Detection Handshake – Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.11 Assertion of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.12 Detection of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.13 HS Device Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.14 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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SMSC USB3450
DATASHEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
List of Figures
Figure 1.1 Basic UTMI+ USB Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 1.2 UTMI+ Level 3 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2.1 USB3450 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.1 USB3450 Pinout - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6.1 FS CLK Relationship to Transmit Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6.2 FS CLK Relationship to Receive Data and Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6.3 Transmit Timing for a Data Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6.4 Receive Timing for Data with Unstuffed Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6.5 Receive Timing for a Handshake Packet (no CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6.6 Receive Timing for Setup Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6.7 Receive Timing for Data Packet (with CRC-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7.1 Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7.2 Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 7.3 HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7.5 HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 7.6 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 7.7 Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 7.8 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7.9 USB3450 Application Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 8.1 USB3450-FZG 40 Pin QFN Package Outline, 6 x 6 x 0.9 mm Body (Lead Free) . . . . . . . . . 40
SMSC USB3450
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Revision 0.1 (05-11-05)
DATASHEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
List of Tables
Table 3.1 USB3450 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5.1 Electrical Characteristics: Supply Pins (Note 5.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5.2 Electrical Characteristics: CLKOUT Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5.3 DC Electrical Characteristics: Logic Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5.6 Regulator Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6.1 DP/DM termination vs. Signaling Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7.1 Linestate States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7.3 Hi-Speed Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7.4 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7.5 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7.6 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7.7 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7.8 HS Detection Handshake Timing Values from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7.9 Resume Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7.10 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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SMSC USB3450
DATASHEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
Chapter 1 General Description
The USB3450 is a stand-alone Hi-Speed USB Physical Layer Transceiver (PHY). The USB3450 uses
a UTMI+ interface to connect to an SOC or ASIC or FPGA. SMSC’s advanced proprietary technology
minimizes power dissipation, resulting in maximum battery life for portable applications. The USB3450
is a flexible solution for adding USB to new designs without integrating the analog PHY block.
SOC/FPGA/ASIC
USB3450
Including Device Controller
VBUS
USB
UTMI+
Hi-
ID
Hi-Speed
USB App.
UTMI+
Link
UTMI+
Interface
Connector
(Standard
or Mini)
Digital
Logic
Speed
Analog
DM
DP
Figure 1.1 Basic UTMI+ USB Device Block Diagram
The USB3450 provides a fully compliant Hi-Speed interface, and supports Hi-Speed (HS), Full-Speed
(FS), and Low-Speed (LS) USB. The USB3450 supports all levels of the UTMI+ specification as shown
in Figure 1.2.
UTMI+ Level 3
Hi-Speed Peripheral, host controllers, On-
the-Go devices
USB3450
USB3500
(HS, FS, LS, preamble packet)
UTMI+ Level 2
Hi-Speed Peripheral, host controllers, On-
the-Go devices
(HS, FS, and LS but no preamble packet)
UTMI+ Level 1
Hi-Speed Peripheral, host controllers,
and On-the-Go devices
(HS and FS Only)
UTMI+ Level 0
Hi-Speed Peripherals Only
USB3280
USB3250
Figure 1.2 UTMI+ Level 3 Support
SMSC USB3450
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Revision 0.1 (05-11-05)
DATASHEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
1.1
Applications
The USB3450 is targeted for any application where a high speed USB connection is desired.
The USB3450 is well suited for:
■
■
■
■
■
■
■
■
■
Cell Phones
MP3 Players
Scanners
Set Top Boxes
Printers
External Hard Drives
Still and Video Cameras
Portable Media Players
Entertainment Devices
Revision 0.1 (05-11-05)
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SMSC USB3450
DATASHEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
Chapter 2 Functional Overview
The USB3450 is a highly integrated USB transceiver system. It contains a complete Hi-Speed PHY
with the UTMI+ industry standard interface to support fast time to market for a USB controller. The
USB3450 is composed of the functional blocks shown in Figure 2.1 below.
24 MHz
XTAL
Internal
XTAL &
VDD3.3
Regulator &
PLL
POR
VDD3.3
Mini-AB
USB
XCVRSEL[1:0]
TERMSEL
Connector
TXREADY
SUSPENDN
TXVALID
DP
DM
RESET
RXACTIVE
OPMODE[1:0]
CLKOUT
HS XCVR
UTMI+
Digital
LINESTATE[1:0]
HOSTDISC
DATA[7:0]
HOST
Resistors
RXERROR
Bias
Gen.
RBIAS
FS/LS
XCVR
USB3450
Figure 2.1 USB3450 Block Diagram
SMSC USB3450
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DATASHEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
Chapter 3 Pin Configuration and Pin Definitions
The USB3450 is offered in a 40 pin QFN package. The pin definitions and locations are documented
below.
3.1
USB3450 Pin Locations
XCVRSEL0
TERMSEL
TXREADY
SUSPENDN
TXVALID
RESET
VDD3.3
DP
30
29
28
27
26
25
24
23
22
21
RXVALID
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
HOSTDISC
1
2
3
4
5
6
7
8
9
10
USB3450
Hi-Speed USB
UTMI+ PHY
40 Pin QFN
DM
GND FLAG
NC
Figure 3.1 USB3450 Pinout - Top View
The flag of the QFN package must be connected to ground.
Revision 0.1 (05-11-05)
SMSC USB3450
DATA1S0HEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
3.2
Pin Definitions
Table 3.1 USB3450 Pin Definitions
DIRECTION,
ACTIVE
LEVEL
PIN
NAME
TYPE
DESCRIPTION
1
XCVRSEL[0]
Input
N/A
Transceiver Select. These signals select between
the FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times
2
3
TERMSEL
TXREADY
Input
N/A
Termination Select. This signal selects between the
FS and HS terminations:
0: HS termination enabled
1: FS termination enabled
Output
High
Transmit Data Ready. If TXVALID is asserted, the
Link must always have data available for clocking
into the TX Holding Register on the rising edge of
CLKOUT. TXREADY is an acknowledgement to the
Link that the transceiver has clocked the data from
the bus and is ready for the next transfer on the bus.
If TXVALID is negated, TXREADY can be ignored by
the Link.
4
5
SUSPENDN
TXVALID
Input
Input
Low
Suspend. Places the transceiver in a mode that
draws minimal power from supplies. In host mode,
RPU is removed during suspend. In device mode,
RPD is controlled by TERMSEL. In suspend mode
the clocks are off.
0: PHY in suspend mode
1: PHY in normal operation
High
Transmit Valid. Indicates that the DATA bus is valid
for transmit. The assertion of TXVALID initiates the
transmission of SYNC on the USB bus. The
negation of TXVALID initiates EOP on the USB.
Control inputs (OPMODE[1:0],
TERMSEL,XCVERSEL) must not be changed on the
de-assertion or assertion of TXVALID.
6
7
RESET
VDD3.3
Input
N/A
High
N/A
Reset. Reset all state machines. After coming out
of reset, must wait 5 rising edges of clock before
asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to
CLKOUT
De-assertion of Reset: Must be synchronous to
CLKOUT
3.3V PHY Supply. Provides power for Hi-Speed
Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.
8
9
DP
I/O,
N/A
N/A
D+ pin of the USB cable.
Analog
DM
I/O,
D- pin of the USB cable.
Analog
10
11
NC
N/A
N/A
N/A
N/A
No Connect.
VDD3.3
3.3V PHY Supply.
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Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
Table 3.1 USB3450 Pin Definitions (continued)
DIRECTION,
TYPE
ACTIVE
LEVEL
PIN
NAME
DESCRIPTION
12
XCVRSEL[1]
Input
N/A
Transceiver Select. These signals select between
the FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times
13
RXACTIVE
Output
High
Receive Active. Indicates that the receive state
machine has detected Start of Packet and is active.
14
15
OPMODE[1]
OPMODE[0]
Input
Input
N/A
N/A
Operational Mode. These signals select between
the various operational modes:
[1] [0] Description
0
0
1
1
0
1
0
1
0: Normal Operation
1: Non-driving (all terminations removed)
2: Disable bit stuffing and NRZI encoding
3: Reserved
16
CLKOUT
Output,
CMOS
N/A
60MHz reference clock output. All UTMI+ signals are
driven synchronous to this clock.
17
18
LINESTATE[1]
LINESTATE[0]
Output
Output
N/A
N/A
Line State. These signals reflect the current state of
the USB data bus in FS mode. Bit [0] reflects the
state of DP and bit [1] reflects the state of DM. When
the device is suspended or resuming from a
suspended state, the signals are combinatorial.
Otherwise, the signals are synchronized to CLKOUT.
[1] [0] Description
0
0
1
1
0
1
0
1
0: SEO
1: J State
2: K State
3: SE1
19
VDD1.8
N/A
N/A
1.8V regulator output for digital circuitry on chip.
Place a 0.1uF capacitor near this pin and connect
the capacitor from this pin to ground. Connect pin 19
to pin 34.
20
21
VDD3.3
N/A
N/A
3.3V PHY Supply. Provides power for Hi-Speed
Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.
HOSTDISC
Output
High
Host Disconnect. Indicates that a downstream
device has been disconnected from this host PHY
when operating in HS host mode. Automatically
reset to 0b when Low Power Mode is entered.
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Table 3.1 USB3450 Pin Definitions (continued)
DIRECTION,
TYPE
ACTIVE
LEVEL
PIN
NAME
DESCRIPTION
22
DATA[7]
I/O,
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
High
8-bit bi-directional data bus. Data[7] is the MSB and
Data[0] is the LSB.
CMOS,
Pull-low
23
24
25
26
27
28
29
30
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
RXVALID
I/O,
CMOS,
Pull-low
I/O,
CMOS,
Pull-low
I/O,
CMOS,
Pull-low
I/O,
CMOS,
Pull-low
I/O,
CMOS,
Pull-low
I/O,
CMOS,
Pull-low
I/O,
CMOS,
Pull-low
Output
Receive Data Valid. Indicates that the DATA bus has
received valid data. The Receive Data Holding
Register is full and ready to be unloaded. The Link
is expected to register the DATA bus on the rising
edge of CLKOUT.
31
32
HOST
Input
N/A
Host Pull-down Select. This signal enables the 15k
Ohm pull-down resistor on the DM line.
0: Pull-down resistor not connected to DM
1: Pull-down resistor connected to DM
RXERROR
Output
High
Receive Error. This output is clocked with the same
timing as the receive DATA lines and can occur at
anytime during a transfer.
0: Indicates no error.
1: Indicates a receive error has been detected.
33
34
VDD3.3
VDD1.8
N/A
N/A
N/A
N/A
3.3V PHY Supply. Provides power for Hi-Speed
Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.
1.8V regulator output for digital circuitry on chip.
Place a 4.7uF low ESR capacitor near this pin and
connect the capacitor from this pin to ground.
Connect pin 34 to pin 19. See Section 6.6.1,
"Internal Regulators".
35
XO
Output,
Analog
N/A
Crystal pin. If using an external clock on XI this pin
should be floated.
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Datasheet
Table 3.1 USB3450 Pin Definitions (continued)
DIRECTION,
TYPE
ACTIVE
LEVEL
PIN
NAME
DESCRIPTION
36
XI
Input,
N/A
Crystal pin. A 24MHz crystal is supported. The
crystal is placed across XI and XO. An external
24MHz clock source may be driven into XI in place
of a crystal.
Analog
37
VDDA1.8
N/A
N/A
1.8V regulator output for analog circuitry on chip.
Place a 0.1uF capacitor near this pin and connect
the capacitor from this pin to ground. In parallel,
place a 4.7uF low ESR capacitor near this pin and
connect the capacitor from this pin to ground. See
Section 6.6.1, "Internal Regulators".
38
VDD3.3
N/A
N/A
N/A
3.3V PHY Supply. Provides power for Hi-Speed
Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.
39
40
VDD3.3
RBIAS
N/A
N/A
N/A
3.3V PHY Supply. Should be connected directly to
pin 39.
Analog,
CMOS
External 1% bias resistor. Requires a 12KΩ resistor
to ground.
GND FLAG
Ground
Ground. The flag must be connected to the ground
plane.
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Chapter 4 Limiting Values
Table 4.1 Maximum Guaranteed Ratings
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum VBUS, ID, DP,
and DM voltage to GND
VMAX_5V
-0.5
+5.5
V
Maximum VDD1.8 and
VDDA1.8 voltage to
Ground
VMAX_1.8V
-0.5
2.5
V
Maximum 3.3V supply
voltage to Ground
VMAX_3.3V
VMAX_IN
-0.5
-0.5
4.0
4.0
V
V
Maximum I/O voltage to
Ground
Operating Temperature
Storage Temperature
TMAX_OP
0
70
C
C
TMAX_STG
-55
150
Note: Stresses above those listed could cause damage to the device. This is a stress rating only and
functional operation of the device at any other condition above those indicated in the operation
sections of this specification is not implied. When powering this device from laboratory or
system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or
device failure can result. Some power supplies exhibit voltage spikes on their outputs when the
AC power is switched on or off. In addition, voltage transients on the AC power line may appear
on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
Table 4.2 Recommended Operating Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.3V Supply Voltage
VDD3.3
3.0
0.0
0.0
3.3
3.6
V
V
V
Input Voltage on Digital Pins VI
VDD3.3
VDD3.3
Input Voltage on Analog I/O
Pins (DP, DM)
VI(I/O)
Ambient Temperature
TA
0
+70
oC
Table 4.3 Recommended External Clock Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
System Clock Frequency
XI driven by the external clock;
and no connection at XO
2 4
MHz
(±100ppm)
System Clock Duty Cycle
XI driven by the external clock;
and no connection at XO
45
50
55
%
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Chapter 5 Electrical Characteristics
Table 5.1 Electrical Characteristics: Supply Pins (Note 5.1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Unconfigured Current
FS Idle Current
IAVG(UCFG)
IAVG(FS)
Device Unconfigured
55
55
mA
mA
mA
FS idle not data transfer
FS Transmit Current
IAVG(FSTX)
FS current during data
transmit
60.5
FS Receive Current
IAVG(FSRX)
FS current during data
receive
57.5
mA
HS Idle Current
IAVG(HS)
FS idle not data transfer
60.6
62.4
mA
mA
HS Transmit Current
IAVG(HSTX)
FS current during data
transmit
HS Receive Current
Low Power Mode
IAVG(HSRX)
IDD(LPM)
FS current during data
receive
61.5
83
mA
uA
VBUS 15kΩ pull-down and
1.5kΩ pull-up resistor
currents not included.
Note 5.1 VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.
Table 5.2 Electrical Characteristics: CLKOUT Start-Up
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Suspend Recovery Time
TSTART
2.25
3.5
ms
Table 5.3 DC Electrical Characteristics: Logic Pins
PARAMETER
SYMBOL
VIL
CONDITIONS
MIN
TYP
MAX
UNITS
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
High-Level Output Voltage
VSS
2.0
0.8
VDD3.3
0.4
V
V
V
V
VIH
VOL
VOH
IOL = 8mA
IOH = -8mA
VDD3.3
- 0.4
Input Leakage Current
Pin Capacitance
ILI
±10
4
uA
pF
Cpin
Note: VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.
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Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FS FUNCTIONALITY
Input levels
Differential Receiver Input
Sensitivity
VDIFS
| V(DP) - V(DM) |
0.2
0.8
V
V
V
V
V
Differential Receiver
VCMFS
VILSE
VIHSE
VHYSSE
2.5
0.8
Common-Mode Voltage
Single-Ended Receiver Low
Level Input Voltage
Single-Ended Receiver High
Level Input Voltage
2.0
Single-Ended Receiver
Hysteresis
0.050
0.150
Output Levels
Low Level Output Voltage
VFSOL
VFSOH
Pull-up resistor on DP;
0.3
3.6
V
V
RL = 1.5kΩ to VDD3.3
High Level Output Voltage
Pull-down resistor on DP,
DM;
2.8
RL = 15kΩ to GND
Termination
Driver Output Impedance for
HS and FS
ZHSDRV
Steady state drive
40.5
45
49.5
Ù
Input Impedance
ZINP
ZPU
TX, RPU disabled
Bus Idle
1.0
MΩ
kΩ
kΩ
kΩ
Pull-up Resistor Impedance
Pull-up Resistor Impedance
Pull-dn Resistor Impedance
HS FUNCTIONALITY
Input levels
0.900
1.425
14.25
1.24
2.26
15.0
1.575
3.09
ZPURX
ZPD
Device Receiving
15.75
HS Differential Input
Sensitivity
VDIHS
| V(DP) - V(DM) |
100
-50
mV
mV
mV
mV
HS Data Signaling Common
Mode Voltage Range
VCMHS
500
100
HS Squelch Detection
Threshold (Differential)
Squelch Threshold
VHSSQ
Un-squelch Threshold
150
-10
Output Levels
Hi-Speed Low Level
Output Voltage (DP/DM
referenced to GND)
VHSOL
45Ω load
45Ω load
10
mV
mV
Hi-Speed High Level
Output Voltage (DP/DM
referenced to GND)
VHSOH
360
440
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Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (continued)
PARAMETER
SYMBOL
CONDITIONS
45Ω load
MIN
TYP
MAX
UNITS
Hi-Speed IDLE Level
Output Voltage (DP/DM
referenced to GND)
VOLHS
-10
10
mV
Chirp-J Output Voltage
(Differential)
VCHIRPJ
HS termination resistor
disabled, pull-up resistor
connected. 45Ω load.
700
1100
-500
mV
mV
Chirp-K Output Voltage
(Differential)
VCHIRPK
HS termination resistor
disabled, pull-up resistor
connected. 45Ω load.
-900
Leakage Current
OFF-State Leakage Current
Port Capacitance
ILZ
±10
10
uA
pF
Transceiver Input
Capacitance
CIN
Pin to GND
5
Note: VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.
Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FS Output Driver Timing
Rise Time
TFSR
CL = 50pF; 10 to 90% of
4
4
20
20
ns
ns
V
|VOH - VOL
|
Fall Time
TFFF
CL = 50pF; 10 to 90% of
|VOH - VOL
|
Output Signal Crossover
Voltage
VCRS
FRFM
Excluding the first
1.3
90
2.0
transition from IDLE state
Differential Rise/Fall Time
Matching
Excluding the first
111.1
%
transition from IDLE state
HS Output Driver Timing
Differential Rise Time
Differential Fall Time
THSR
THSF
500
500
ps
ps
Driver Waveform
Requirements
Eye pattern of Template 1
in Hi-Speed specification
Hi-Speed Mode Timing
Receiver Waveform
Requirements
Eye pattern of Template 4
in Hi-Speed specification
Data Source Jitter and
Receiver Jitter Tolerance
Eye pattern of Template 4
in Hi-Speed specification
Note: VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.
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Table 5.6 Regulator Output Voltages
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDDA1.8
VDDA1.8
VDD1.8
VDDA1.8
Normal Operation
(SUSPENDN = 1)
1.6
1.8
2.0
V
VDDA1.8
VDD1.8
Low Power mode
(SUSPENDN = 0)
0
V
V
1.6
1.8
2.0
Note: VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified
SMSC USB3450
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Datasheet
Chapter 6 Detailed Functional Overview
Figure 2.1 on page 9 shows the functional block diagram of the USB3450. Each of the functions is
described in detail below.
6.1
8bit Bi-Directional Data Bus Operation
The USB3450 supports an 8-bit bi-directional parallel interface.
■
■
■
CLKOUT runs at 60MHz
The 8-bit data bus (DATA[7:0]) is used for transmit when TXVALID = 1
The 8-bit data bus (DATA[7:0]) is used for receive when TXVALID = 0
Figure 6.1 shows the relationship between CLKOUT and the transmit data transfer signals in FS mode.
TXREADY is only asserted for one CLKOUT per byte time to signal the Link that the data on the DATA
lines has been read by the PHY. The Link may hold the data on the DATA lines for the duration of the
byte time. Transitions of TXVALID must meet the defined setup and hold times relative to CLKOUT.
Figure 6.1 FS CLK Relationship to Transmit Data and Control Signals
Figure 6.2 shows the relationship between CLKOUT and the receive data control signals in FS mode.
RXACTIVE “frames” a packet, transitioning only at the beginning and end of a packet. However
transitions of RXVALID may take place any time 8 bits of data are available. Figure 6.2 also shows
how RXVALID is only asserted for one CLKOUT cycle per byte time even though the data may be
presented for the full byte time. The XCVRSELECT signal determines whether the HS or FS timing
relationship is applied to the data and control signals.
Figure 6.2 FS CLK Relationship to Receive Data and Control Signals
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6.2
TX Logic
This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit
operations. These operations include parallel to serial conversion, bit stuffing and NRZI encoding.
Upon valid assertion of the proper TX control lines by the Link and TX State Machine, the TX LOGIC
block will synchronously shift, at either the FS or HS rate, the data to the FS/HS TX block to be
transmitted on the USB cable. Data transmit timing is shown in Figure 6.3.
Figure 6.3 Transmit Timing for a Data Packet
The behavior of the Transmit State Machine is described below.
■
The Link asserts TXVALID to begin a transmission.
■
After the Link asserts TXVALID it can assume that the transmission has started when it detects
TXREADY has been asserted.
■
■
The Link must assume that the USB3450 has consumed a data byte if TXREADY and TXVALID
are asserted on the rising edge of CLKOUT.
The Link must have valid packet information (PID) asserted on the DATA bus coincident with the
assertion of TXVALID.
■
■
TXREADY is sampled by the Link on the rising edge of CLKOUT.
The Link negates TXVALID to complete a packet. Once negated, the transmit logic will never
reassert TXREADY until after the EOP has been generated. (TXREADY will not re-assert until
TXVALD asserts again.
■
■
The USB3450 is ready to transmit another packet immediately, however the Link must conform to
the minimum inter-packet delays identified in the Hi-Speed specification.
Supports high speed disconnect detect through the HOSTDISC pin. In Host mode the USB3450
will sample the disconnect comparator at the 32nd bit of the 40 bit long EOP during SOF packets.
■
■
■
Supports FS pre-amble for FS hubs with a LS device.
Supports LS keep alive by receiving the SOF PID.
Supports Host mode resume K which ends with two low speed times of SE0 followed by 1 FS “J”.
6.3
RX Logic
This block receives serial data from the clock recovery circuits and processes it to be transferred to
the Link on the DATA bus. The processing involved includes NRZI decoding, bit unstuffing, and serial
to parallel conversion. Upon valid assertion of the proper RX control lines, the RX Logic block will
provide bytes to the DATA bus as shown in the figures below. The behavior of the receiver is described
below.
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Figure 6.4 Receive Timing for Data with Unstuffed Bits
The assertion of RESET will cause the USB3450 to deasserts RXACTIVE and RXVALID. When the
RESET signal is deasserted the Receive State Machine starts looking for a SYNC pattern on the USB.
When a SYNC pattern is detected the receiver will assert RXACTIVE. The length of the received Hi-
Speed SYNC pattern varies and can be up to 32 bits long or as short as 12 bits long when at the end
of five hubs.
After valid serial data is received, the data is loaded into the RX Holding Register on the rising edge
of CLKOUT and RXVALID is asserted. The Link must clock the data off the DATA bus on the next
rising edge of CLKOUT. In normal mode (OPMODE = 00), then stuffed bits are stripped from the data
stream. Each time 8 stuffed bits are accumulated the USB3450 will negate RXVALID for one clock
cycle, thus skipping a byte time.
When the EOP is detected the USB3450 will negate RXACTIVE and RXVALID. After the EOP has
been stripped the USB3450 will begin looking for the next packet.
The behavior of the USB3450 receiver is described below:
■
■
■
■
■
■
RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT.
After a EOP is complete the receiver will begin looking for SYNC.
The USB3450 asserts RXACTIVE when SYNC is detected.
The USB3450 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty.
When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full.
RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time.
This will occur if 8 stuffed bits have been accumulated.
■
■
The Link must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data
state).
Figure 6.5 shows the timing relationship between the received data (DP/DM), RXVALID,
RXACTIVE, RXERROR and DATA signals.
Notes:
Figure 6.5, Figure 6.6 and Figure 6.7 are timing examples of a HS/FS PHY when it is in HS mode.
■
When a HS/FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time.
The Receive State Machine assumes that the Link captures the data on the DATA bus if RXACTIVE
and RXVALID are asserted. In FS mode, RXVALID will only be asserted for one CLKOUT per byte
time.
■
In Figure 6.5, Figure 6.6 and Figure 6.7 the SYNC pattern on DP/DM is shown as one byte long.
The SYNC pattern received by a device can vary in length. These figures assume that all but the
last 12 bits have been consumed by the hubs between the device and the host controller.
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Figure 6.5 Receive Timing for a Handshake Packet (no CRC)
Figure 6.6 Receive Timing for Setup Packet
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Figure 6.7 Receive Timing for Data Packet (with CRC-16)
The receivers connect directly to the USB cable. The block contains a separate differential receiver
for HS and FS mode. Depending on the mode, the selected receiver provides the serial data stream
through the mulitplexer to the RX Logic block. The FS mode section of the FS/HS RX block also
consists of a single-ended receiver on each of the data lines to determine the correct FS LINESTATE.
For HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never
interpreted as data.
6.4
Hi-Speed Transceiver
The SMSC Hi-Speed Transceiver consists of four blocks in the lower left corner of Figure 2.1 on
page 9. These four blocks are labeled HS XCVR, FS/LS XCVR, Resistors, and Bias Gen.
6.4.1
High Speed and Full Speed Transceivers
The USB3450 transceiver meets all requirements in the Hi-Speed specification.
The receivers connect directly to the USB cable. This block contains a separate differential receiver
for HS and FS mode. Depending on the mode, the selected receiver provides the serial data stream
through the multiplexer to the RX Logic block. The FS mode section of the FS/HS RX block also
consists of a single-ended receiver on each of the data lines to determine the correct FS linestate. For
HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never
interpreted as data.
The transmitters connect directly to the USB cable. The block contains a separate differential FS and
HS transmitter which receive encoded, bit stuffed, serialized data from the TX Logic block and transmit
it on the USB cable.
6.4.2
Termination Resistors
The USB3450 transceiver fully integrates all of the USB termination resistors. The USB3450 includes
two 1.5kΩ pull-up resistors on DP and DM and a 15kΩ pull-down resistor on both DP and DM. In
addition the 45Ω high speed termination resistors are also integrated. These integrated resistors
require no tuning or trimming by the Link. The state of the resistors is determined by the operating
mode of the PHY. The possible valid resistor combinations are shown in Table 6.1. Operation is
guaranteed in the configurations given in Table 6.1, "DP/DM termination vs. Signaling Mode".
■
RPU_DP_EN activates the 1.5kΩ DP pull-up resistor
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■
■
■
■
RPU_DM_EN activates the 1.5kΩ DM pull-up resistor
RPD_DP_EN activates the 15kΩ DP pull-down resistor
RPD_DM_EN activates the 15kΩ DM pull-down resistor
HSTERM_EN activates the 45Ω DP and DM high speed termination resistors
Table 6.1 DP/DM termination vs. Signaling Mode
UTMI+ INTERFACE
SETTINGS
RESISTOR SETTINGS
SIGNALING MODE
General Settings
Tri-State Drivers
XXb
01b
Xb
0b
01b
00b
Xb
1b
0b
0b
0b
0b
0b
1b
0b
1b
0b
0b
Power-up or Vbus < VSESSEND
Host Settings
Host Chirp
00b
00b
X1b
01b
01b
10b
10b
10b
00b
0b
0b
1b
1b
1b
1b
1b
1b
0b
10b
00b
00b
00b
10b
00b
00b
10b
10b
1b
1b
1b
1b
1b
1b
1b
1b
1b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
0b
0b
0b
0b
0b
0b
1b
Host Hi-Speed
Host Full Speed
Host HS/FS Suspend
Host HS/FS Resume
Host low Speed
Host LS Suspend
Host LS Resume
Host Test J/Test_K
Peripheral Settings
Peripheral Chirp
00b
00b
01b
01b
01b
10b
10b
10b
00b
1b
0b
1b
1b
1b
1b
1b
1b
0b
10b
00b
00b
00b
10b
00b
00b
10b
10b
0b
0b
0b
0b
0b
0b
0b
0b
0b
1b
0b
1b
1b
1b
0b
0b
0b
0b
0b
0b
0b
0b
0b
1b
1b
1b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
1b
0b
0b
0b
0b
0b
0b
1b
Peripheral HS
Peripheral FS
Peripheral HS/FS Suspend
Peripheral HS/FS Resume
Peripheral LS
Peripheral LS Suspend
Peripheral LS Resume
Peripheral Test J/Test K
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Datasheet
6.4.3
Bias Generator
This block consists of an internal bandgap reference circuit used for generating the high speed driver
currents and the biasing of the analog circuits. This block requires an external 12KΩ, 1% tolerance,
external reference resistor connected from RBIAS to ground.
6.5
Crystal Oscillator and PLL
The USB3450 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference
clock that is used by the PHY during both transmit and receive. The USB3450 requires a clean 24MHz
crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY
may not operate correctly.
The USB3450 can use either a crystal or an external clock oscillator for the 24MHz reference. The
crystal is connected to the XI and XO pins as shown in the application diagram, Figure 7.9. If a clock
oscillator is used the clock should be connected to the XI input and the XO pin left floating. When an
external clock is used the XI pin is designed to be driven with a 0 to 3.3 volt signal. When using an
external clock the user needs to take care to ensure the external clock source is clean enough to not
degrade the high speed eye performance.
Once, the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz
clock. The USB3450 is guaranteed to start the clock within the time specified in Table 5.2.
6.6
Internal Regulators and POR
The USB3450 includes an integrated set of built in power management functions. These power
management features include a POR generation and allow the USB3450 to be powered from a single
3.3 volt power supply. This reduces the bill of materials and simplifies product design.
6.6.1
Internal Regulators
The USB3450 has two internal regulators that create two 1.8V outputs (labeled VDD1.8 and VDDA1.8)
from the 3.3volt power supply input (VDD3.3). Each regulator requires an external 4.7uF +/-20% low
ESR bypass capacitor to ensure stability. X5R or X7R ceramic capacitors are recommended since they
exhibit an ESR lower that 0.1ohm at frequencies greater than 10kHz..
The specific capacitor recommendations for each pin are detailed in Table 3.1, “USB3450 Pin
Definitions,” on page 11, and shown in Figure 7.9 USB3450 Application Diagram (Top View) on
page 39.
Note: The USB3450 regulators are designed to generate a 1.8 volt supply for the USB3450 only.
Using the regulators to provide current for other circuits is not recommended and SMSC does
not guarantee USB performance or regulator stability.
6.6.2
Power On Reset (POR)
The USB3450 provides an internal POR circuit that generates a reset pulse once the PHY supplies
are stable. The UTMI+ Digital can be reset at any time with the RESET pin.
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Datasheet
Chapter 7 Application Notes
The following sections consist of select functional explanations to aid in implementing the USB3450
into a system. For complete description and specifications consult the Hi-Speed Transceiver Macrocell
Interface Specification and Universal Serial Bus Specification Revision 2.0.
7.1
Linestate
The voltage thresholds that the LINESTATE[1:0] signals use to reflect the state of DP and DM depend
on the state of XCVRSELECT. LINESTATE[1:0] uses HS thresholds when the HS transceiver is
enabled (XCVRSELECT = 0) and FS thresholds when the FS transceiver is enabled (XCVRSELECT
= 1). There is not a concept of variable single-ended thresholds in the Hi-Speed specification for HS
mode.
The HS receiver is used to detect Chirp J or K, where the output of the HS receiver is always qualified
with the Squelch signal. If squelched, the output of the HS receiver is ignored. In the USB3450, as an
alternative to using variable thresholds for the single-ended receivers, the following approach is used.
Table 7.1 Linestate States
STATE OF DP/DM LINES
LINESTATE[1:0]
LS[1] LS[0]
FULL SPEED
XCVRSELECT =1
TERMSELECT=1
HIGH SPEED
XCVRSELECT =0
TERMSELECT=0
CHIRP MODE
XCVRSELECT =0
TERMSELECT=1
0
0
0
1
SE0
Squelch
Squelch
Squelch
J
Squelch &
HS Diff. Receiver Output
1
1
0
1
K
Invalid
Invalid
Squelch &
HS Diff. Receiver Output
SE1
Invalid
In HS mode, 3ms of no USB activity (IDLE state) signals a reset. The Link monitors LINESTATE[1:0]
for the IDLE state. To minimize transitions on LINESTATE[1:0] while in HS mode, the presence of
Squelch is used to force LINESTATE[1:0] to a J state.
7.2
OPMODES
The OPMODE[1:0] pins allow control of the operating modes.
Table 7.2 Operational Modes
MODE[1:0]
STATE#
STATE NAME
DESCRIPTION
00
0
Normal Operation
Transceiver operates with normal USB data encoding and
decoding
01
1
Non-Driving
Allows the transceiver logic to support a soft disconnect feature
which tri-states both the HS and FS transmitters, and removes
any termination from the USB making it appear to an upstream
port that the device has been disconnected from the bus
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Table 7.2 Operational Modes (continued)
MODE[1:0]
STATE#
STATE NAME
DESCRIPTION
10
2
Disable Bit Stuffing
Disables bitstuffing and NRZI encoding logic so that 1's loaded
and NRZI encoding from the DATA bus become 'J's on the DP/DM and 0's become
'K's
11
3
Reserved
N/A
The OPMODE[1:0] signals are normally changed only when the transmitter and the receiver are
quiescent, i.e. when entering a test mode or for a device initiated resume.
When using OPMODE[1:0] = 10 the SYNC and EOP patterns are not transmitted.
The only exception to this is when OPMODE[1:0] is set to state 2 while TXVALID has been asserted
(the transceiver is transmitting a packet), in order to flag a transmission error. In this case, the
USB3450 has already transmitted the SYNC pattern so upon negation of TXVALID the EOP must also
be transmitted to properly terminate the packet. Changing the OPMODE[1:0] signals under all other
conditions, while the transceiver is transmitting or receiving data will generate undefined results.
7.3
Test Mode Support
Table 7.3 Hi-Speed Test Modes
USB3450 SETUP
LINK TRANSMITTED
DATA
XCVRSELECT &
TERMSELECT
HI-SPEED TEST MODES
OPERATIONAL MODE
SE0_NAK
State 0
State 2
State 2
State 0
No transmit
All '1's
HS
HS
HS
HS
J
K
All '0's
Test_Packet
Test Packet data
7.4
7.5
SE0 Handling
For FS operation, IDLE is a J state on the bus. SE0 is used as part of the EOP or to indicate reset.
When asserted in an EOP, SE0 is never asserted for more than 2 bit times. The assertion of SE0 for
more than 2.5us is interpreted as a reset by the device operating in FS mode.
For HS operation, IDLE is a SE0 state on the bus. SE0 is also used to reset a HS device. A HS
device cannot use the 2.5us assertion of SE0 (as defined for FS operation) to indicate reset since the
bus is often in this state between packets. If no bus activity (IDLE) is detected for more than 3ms, a
HS device must determine whether the downstream facing port is signaling a suspend or a reset. The
following section details how this determination is made. If a reset is signaled, the HS device will then
initiate the HS Detection Handshake protocol.
Reset Detection
If a device in HS mode detects bus inactivity for more than 3ms (T1), it reverts to FS mode. This
enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus. The
Link must then check LINESTATE for the SE0 condition. If SE0 is asserted at time T2, then the
upstream port is forcing the reset state to the device (i.e., a Driven SE0). The device will then initiate
the HS detection handshake protocol.
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Figure 7.1 Reset Timing Behavior (HS Mode)
Table 7.4 Reset Timing Values (HS Mode)
DESCRIPTION
TIMING
PARAMETER
VALUE
HS Reset T0
Bus activity ceases, signaling either a reset
0 (reference)
or a SUSPEND.
T1
T2
Earliest time at which the device may place
itself in FS mode after bus activity stops.
HS Reset T0 + 3. 0ms < T1 < HS Reset T0
+ 3.125ms
Link samples LINESTATE. If LINESTATE =
SE0, then the SE0 on the bus is due to a
Reset state. The device now enters the HS
Detection Handshake protocol.
T1 + 100µs < T2 <
T1 + 875µs
7.6
Suspend Detection
If a HS device detects SE0 asserted on the bus for more than 3ms (T1), it reverts to FS mode. This
enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus. The
Link must then check LINESTATE for the J condition. If J is asserted at time T2, then the upstream
port is asserting a soft SE0 and the USB is in a J state indicating a suspend condition. By time T4 the
device must be fully suspended.
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Figure 7.2 Suspend Timing Behavior (HS Mode)
Table 7.5 Suspend Timing Values (HS Mode)
TIMING
PARAMETER
DESCRIPTION
VALUE
HS Reset T0
End of last bus activity, signaling either a reset
or a SUSPEND.
0 (reference)
T1
T2
The time at which the device must place itself
in FS mode after bus activity stops.
HS Reset T0 + 3. 0ms < T1 < HS Reset T0
+ 3.125ms
Link samples LINESTATE. If LINESTATE = 'J',
then the initial SE0 on the bus (T0 - T1) had
been due to a Suspend state and the Link
remains in HS mode.
T1 + 100 µs < T2 <
T1 + 875µs
T3
T4
The earliest time where a device can issue
Resume signaling.
HS Reset T0 + 5ms
HS Reset T0 + 10ms
The latest time that a device must actually be
suspended, drawing no more than the
suspend current from the bus.
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7.7
HS Detection Handshake
The High Speed Detection Handshake process is entered from one of three states: suspend, active
FS or active HS. The downstream facing port asserting an SE0 state on the bus initiates the HS
Detection Handshake. Depending on the initial state, an SE0 condition can be asserted from 0 to 4
ms before initiating the HS Detection Handshake. These states are described in the Hi-Speed
specification.
There are three ways in which a device may enter the HS Handshake Detection process:
1. If the device is suspended and it detects an SE0 state on the bus it may immediately enter the HS
handshake detection process.
2. If the device is in FS mode and an SE0 state is detected for more than 2.5µs. it may enter the HS
handshake detection process.
3. If the device is in HS mode and an SE0 state is detected for more than 3.0ms. it may enter the
HS handshake detection process. In HS mode, a device must first determine whether the SE0 state
is signaling a suspend or a reset condition. To do this the device reverts to FS mode by placing
XCVRSELECT and TERMSELECT into FS mode. The device must not wait more than 3.125ms
before the reversion to FS mode. After reverting to FS mode, no less than 100µs and no more
than 875µs later the Link must check the LINESTATE signals. If a J state is detected the device
will enter a suspend state. If an SE0 state is detected, then the device will enter the HS Handshake
detection process.
In each case, the assertion of the SE0 state on the bus initiates the reset. The minimum reset interval
is 10ms. Depending on the previous mode that the bus was in, the delay between the initial assertion
of the SE0 state and entering the HS Handshake detection can be from 0 to 4ms.
This transceiver design pushes as much of the responsibility for timing events on to the Link as
possible, and the Link requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3
above, CLKOUT has been running and is stable, however in case 1 the USB3450 is reset from a
suspend state, and the internal oscillator and clocks of the transceiver are assumed to be powered
down. A device has up to 6ms after the release of SUSPENDN to assert a minimum of a 1ms Chirp K.
7.8
HS Detection Handshake – FS Downstream Facing Port
Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The
DP pull-up is asserted and the HS terminations are disabled. The Link then sets OPMODE to Disable
Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and begins the transmission of all 0's
data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and
must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp
sequence from the host port.
If the downstream facing port is not HS capable, then the HS K asserted by the device is ignored and
the alternating sequence of HS Chirp K’s and J’s is not generated. If no chirps are detected (T4) by
the device, it will enter FS mode by returning XCVRSELECT to FS mode.
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Figure 7.3 HS Detection Handshake Timing Behavior (FS Mode)
Table 7.6 HS Detection Handshake Timing Values (FS Mode)
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
T1
T2
T3
T4
T5
HS Handshake begins. DP pull-up enabled, HS
terminations disabled.
0 (reference)
Device enables HS Transceiver and asserts Chirp
K on the bus.
T0 < T1 < HS Reset T0 + 6.0ms
Device removes Chirp K from the bus. 1ms
minimum width.
T1 + 1.0 ms < T2 <
HS Reset T0 + 7.0ms
Earliest time when downstream facing port may
assert Chirp KJ sequence on the bus.
T2 < T3 < T2+100µs
Chirp not detected by the device. Device reverts to
FS default state and waits for end of reset.
T2 + 1.0ms < T4 <
T2 + 2.5ms
Earliest time at which host port may end reset
HS Reset T0 + 10ms
Notes:
■
T0 may occur to 4ms after HS Reset T0.
■
The Link must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration.
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7.9
HS Detection Handshake – HS Downstream Facing Port
Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The
DP pull-up is asserted and the HS terminations are disabled. The Link then sets OPMODE to Disable
Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and begins the transmission of all 0's
data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and
must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp
sequence from the downstream facing port. If the downstream facing port is HS capable then it will
begin generating an alternating sequence of Chirp K’s and Chirp J’s (T3) after the termination of the
chirp from the device (T2). After the device sees the valid chirp sequence Chirp K-J-K-J-K-J (T6), it
will enter HS mode by setting TERMSELECT to HS mode (T7).
Figure 7.4 provides a state diagram for Chirp K-J-K-J-K-J validation. Prior to the end of reset (T9) the
device port must terminate the sequence of Chirp K’s and Chirp J’s (T8) and assert SE0 (T8-T9). Note
that the sequence of Chirp K’s and Chirp J’s constitutes bus activity.
Start Chirp
K-J-K-J-K-J
detection
!K
Chirp
K State
Invalid
Chirp Count
= 0
Detect K?
INC Chirp
Count
SE0
Chirp Count != 6
& !SE0
!J
Chirp Count
Chirp Valid
J State
Detect J?
INC Chirp
Count
Chirp Count != 6
& !SE0
Figure 7.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram
The Chirp K-J-K-J-K-J sequence occurs too slow to propagate through the serial data path, therefore
LINESTATE signal transitions must be used by the Link to step through the Chirp K-J-K-J-K-J state
diagram, where “K State” is equivalent to LINESTATE = K State and “J State” is equivalent to
LINESTATE = J State. The Link must employ a counter (Chirp Count) to count the number of Chirp K
and Chirp J states. Note that LINESTATE does not filter the bus signals so the requirement that a bus
state must be “continuously asserted for 2.5µs” must be verified by the Link sampling the LINESTATE
signals.
SMSC USB3450
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Hi-Speed USB Host or Device PHY With UTMI+ Interface
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Figure 7.5 HS Detection Handshake Timing Behavior (HS Mode)
Table 7.7 Reset Timing Values
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
HS Handshake begins. DP pull-up enabled, HS
terminations disabled.
0 (reference)
T1
T2
Device asserts Chirp K on the bus.
T0 < T1 < HS Reset T0 + 6.0ms
Device removes Chirp K from the bus. 1 ms
minimum width.
T0 + 1.0ms < T2 <
HS Reset T0 + 7.0ms
T3
T4
T5
Downstream facing port asserts Chirp K on the
bus.
T2 < T3 < T2+100µs
Downstream facing port toggles Chirp K to Chirp J
on the bus.
T3 + 40µs < T4 < T3 + 60µs
T4 + 40µs < T5 < T4 + 60µs
Downstream facing port toggles Chirp J to Chirp K
on the bus.
T6
T7
Device detects downstream port chirp.
T6
Chirp detected by the device. Device removes DP
pull-up and asserts HS terminations, reverts to HS
default state and waits for end of reset.
T6 < T7 < T6 + 500µs
T8
T9
Terminate host port Chirp K-J sequence (Repeating
T4 and T5)
T9 - 500µs < T8 < T9 - 100µs
HS Reset T0 + 10ms
The earliest time at which host port may end reset.
The latest time, at which the device may remove
the DP pull-up and assert the HS terminations,
reverts to HS default state.
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Notes:
■
■
■
T0 may be up to 4ms after HS Reset T0.
The Link must use LINESTATE to detect the downstream port chirp sequence.
Due to the assertion of the HS termination on the host port and FS termination on the device port,
between T1 and T7 the signaling levels on the bus are higher than HS signaling levels and are
less than FS signaling levels.
7.10
HS Detection Handshake – Suspend Timing
If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are
assumed to be powered down. Figure 7.6 shows how CLKOUT is used to control the duration of the
chirp generated by the device.
When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE),
SUSPENDN is combinatorially negated at time T0 by the Link. It takes approximately 5 milliseconds
for the transceiver's oscillator to stabilize. The device does not generate any transitions of the CLKOUT
signal until it is “usable” (where “usable” is defined as stable to within ±10% of the nominal frequency
and the duty cycle accuracy 50±5%).
The first transition of CLKOUT occurs at T1. The Link then sets OPMODE to Disable Bit Stuffing and
NRZI encoding, XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLKOUT cycles to
ensure a 1ms minimum duration. If CLKOUT is 10% fast (66MHz) then Chirp K will be 1.0ms. If
CLKOUT is 10% slow (54 MHz) then Chirp K will be 1.2ms. The 5.6ms requirement for the first
CLKOUT transition after SUSPENDN, ensures enough time to assert a 1ms Chirp K and still complete
before T3. Once the Chirp K is completed (T3) the Link can begin looking for host chirps and use
CLKOUT to time the process. At this time, the device follows the same protocol as in Section 7.9, "HS
Detection Handshake – HS Downstream Facing Port" for completion of the High Speed Handshake.
T0
T1
T2
T3 T4
time
OPMODE 0
OPMODE 1
XCVRSELECT
TERMSELECT
SUSPENDN
TXVALID
CLK60
DP/DM
SE0
J
CLK power up time
Device Chirp K
Look for host chirps
Figure 7.6 HS Detection Handshake Timing Behavior from Suspend
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To detect the assertion of the downstream Chirp K's and Chirp J's for 2.5us {TFILT}, the Link must see
the appropriate LINESTATE signals asserted continuously for 165 CLKOUT cycles.
Table 7.8 HS Detection Handshake Timing Values from Suspend
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
While in suspend state an SE0 is detected on the USB. HS
Handshake begins. D+ pull-up enabled, HS terminations
disabled, SUSPENDN negated.
0 (HS Reset T0)
T1
First transition of CLKOUT. CLKOUT "Usable" (frequency
accurate to ±10%, duty cycle accurate to 50±5).
T0 < T1 < T0 + 5.6ms
T1 < T2 < T0 + 5.8ms
T2
T3
Device asserts Chirp K on the bus.
Device removes Chirp K from the bus. (1 ms minimum width)
and begins looking for host chirps.
T2 + 1.0 ms < T3 <
T0 + 7.0 ms
T4
CLK "Nominal" (CLKOUT is frequency accurate to ±500
ppm, duty cycle accurate to 50±5).
T1 < T3 < T0 + 20.0ms
7.11
Assertion of Resume
In this case, an event internal to the device initiates the resume process. A device with remote wake-
up capability must wait for at least 5ms after the bus is in the idle state before sending the remote
wake-up resume signaling. This allows the hubs to get into their suspend state and prepare for
propagating resume signaling.
The device has 10ms where it can draw a non-suspend current before it must drive resume signaling.
At the beginning of this period the Link may negate SUSPENDN, allowing the transceiver (and its
oscillator) to power up and stabilize.
Figure 7.7 illustrates the behavior of a device returning to HS mode after being suspended. At T4, a
device that was previously in FS mode would maintain TERMSELECT and XCVRSELECT high.
To generate resume signaling (FS 'K') the device is placed in the "Disable Bit Stuffing and NRZI
encoding" Operational Mode (OPMODE [1:0] = 10), TERMSELECT and XCVRSELECT must be in FS
mode, TXVALID asserted, and all 0's data is presented on the DATA bus for at least 1ms (T1 - T2).
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Figure 7.7 Resume Timing Behavior (HS Mode)
Table 7.9 Resume Timing Values (HS Mode)
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
T1
T2
Internal device event initiating the resume
process
0 (reference)
Device asserts FS 'K' on the bus to signal
resume request to downstream port
T0 < T1 < T0 + 10ms.
The device releases FS 'K' on the bus. However
by this time the 'K' state is held by downstream
port.
T1 + 1.0ms < T2 < T1 + 15ms
T3
T4
Downstream port asserts SE0.
T1 + 20ms
Latest time at which a device, which was
previously in HS mode, must restore HS mode
after bus activity stops.
T3 + 1.33µs {2 Low-speed bit times}
7.12
Detection of Resume
Resume signaling always takes place in FS mode (TERMSELECT and XCVRSELECT = FS enabled),
so the behavior for a HS device is identical to that of a FS device. The Link uses the LINESTATE
signals to determine when the USB transitions from the 'J' to the 'K' state and finally to the terminating
FS EOP (SE0 for 1.25us-1.5µs.).
The resume signaling (FS 'K') will be asserted for at least 20ms. At the beginning of this period the
Link may negate SUSPENDN, allowing the transceiver (and its oscillator) to power up and stabilize.
The FS EOP condition is relatively short. Links that simply look for an SE0 condition to exit suspend
mode do not necessarily give the transceiver’s clock generator enough time to stabilize. It is
recommended that all Link implementations key off the 'J' to 'K' transition for exiting suspend mode
(SUSPENDN = 1). And within 1.25µs after the transition to the SE0 state (low-speed EOP) the Link
must enable normal operation, i.e. enter HS or FS mode depending on the mode the device was in
when it was suspended.
SMSC USB3450
Revision 0.1 (05-11-05)
DATA3S7HEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
If the device was in FS mode: then the Link leaves the FS terminations enabled. After the SE0 expires,
the downstream port will assert a J state for one low-speed bit time, and the bus will enter a FS Idle
state (maintained by the FS terminations).
If the device was in HS mode: then the Link must switch to the FS terminations before the SE0 expires
(< 1.25µs). After the SE0 expires, the bus will then enter a HS IDLE state (maintained by the HS
terminations).
7.13
HS Device Attach
Figure 7.8 demonstrates the timing of the USB3450 control signals during a device attach event. When
a HS device is attached to an upstream port, power is asserted to the device and the device sets
XCVRSELECT and TERMSELECT to FS mode (time T1).
VBUS is the +5V power available on the USB cable. Device Reset in Figure 7.8 indicates that VBUS is
within normal operational range as defined in the Hi-Speed specification. The assertion of Device
Reset (T0) by the upstream port will initialize the device. By monitoring LINESTATE, the Link state
machine knows to set the XCVRSELECT and TERMSELECT signals to FS mode (T1).
The standard FS technique of using a pull-up resistor on DP to signal the attach of a FS device is
employed. The Link must then check the LINESTATE signals for SE0. If LINESTATE = SE0 is asserted
at time T2 then the upstream port is forcing the reset state to the device (i.e. Driven SE0). The device
will then reset itself before initiating the HS Detection Handshake protocol.
Figure 7.8 Device Attach Behavior
Table 7.10 Attach and Reset Timing Values
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
T1
Vbus Valid.
0 (reference)
Maximum time from Vbus valid to when the device
must signal attach.
T0 + 100ms < T1
T2
Debounce interval. The device now enters the HS
Detection Handshake protocol.
T1 + 100ms < T2
(HS Reset T0)
Revision 0.1 (05-11-05)
SMSC USB3450
DATA3S8HEET
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
7.14
Application Diagram
CLOAD
VDD3.3
3.3 Volt
Supply
CLOAD
XCVRSEL0
TERMSEL
TXREADY
SUSPENDN
TXVALID
RESET
VDD3.3
DP
RXVALID
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
HOSTDISC
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
5 Volt
VBUS
Supply
CVBUS
USB3450
Host Only
Hi-Speed USB
UTMI+ PHY
40 Pin QFN
USB
ID
Connector
(Standard
or Mini)
DP
DM
DM
GND FLAG
NC
CVBUS
Min
Max
Host
Device
100uF
1uF
UTMI+
10uF
6.5uF
Interface
to Link
OTG Device
1uF
25
Figure 7.9 USB3450 Application Diagram (Top View)
SMSC USB3450
Revision 0.1 (05-11-05)
DATA3S9HEET
Chapter 8 Package Outline
REVISION HISTORY
DESCRIPTION
REVISION
A
DATE
RELEASED BY
S.K.ILIEV
INITIAL RELEASE
10/29/04
D
D2
TERMINAL #1
IDENTIFIER AREA
(D/2 X E/2)
3
D1
e
3
TERMINAL #1
IDENTIFIER AREA
(D1/2 X E1/2)
2
E1
E
E2
EXPOSED PAD
40X L
4X 45°x0.6MAX (OPTIONAL)
40X 0.2 MIN
40X b
2
TOP VIEW
BOTTOM VIEW
A2
A
A1
SIDE VIEW
D2 / E2 VARIATIONS
CATALOG PART
3-D VIEWS
THIRD ANGLE PROJECTION
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
AND TOLERANCES ARE:
80 ARKAY DRIVE
HAUPPAUGE, NY 11788
USA
DECIMAL
ANGULAR
±1°
X.X
±0.1
X.XX ±0.05
X.XXX ±0.025
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETER.
2. POSITION TOLERANCE OF EACH TERMINAL AND EXPOSED PAD IS ± 0.05mm AT
MAXIMUM MATERIAL CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS
AND IT IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP.
3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN
THE AREA INDICATED.
TITLE
NAME
DATE
DIM AND TOL PER ASME Y14.5M - 1994
MATERIAL
PACKAGE OUTLINE
40 TERMINAL QFN, 6x6mm BODY, 0.5mm PITCH
DRAWNS.K.ILIEV
10/29/04
10/29/04
10/29/04
-
FINISH
CHECKED
DWG NUMBER
REV
-
S.K.ILIEV
A
MO-40-QFN-6x6
APPROVED
SCALE
STD COMPLIANCE
SHEET
PRINT WITH "SCALE TO FIT"
DO NOT SCALE DRAWING
S.K.ILIEV
1:1
JEDEC: MO-220
1 OF 1
Figure 8.1 USB3450-FZG 40 Pin QFN Package Outline, 6 x 6 x 0.9 mm Body (Lead Free)
相关型号：
USB3503AI-1-GL-TR
UNIVERSAL SERIAL BUS CONTROLLER, PBGA25, 1.97 X 1.97 MM, 0.40 MM PITCH, ROHS COMPLIANT, WLCSP-25
MICROCHIP
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