CXD1914Q [SONY]
Digital Video Encoder; 数字视频编码器
| 型号： | CXD1914Q |
| 厂家： | 
SONY CORPORATION |
| 描述： | Digital Video Encoder |
| 文件： | 总41页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD1914Q
Digital Video Encoder
For the availability of this product, please contact the sales office.
Description
100 pin QFP (Plastic)
The CXD1914Q is a digital video encoder
designed for DVDs, set top boxes, digital VCRs and
other digital video equipment. This device accepts
ITU-R601 compatible Y, Cb and Cr data, and the
data are encoded to composite video and separate
Y/C video (S-video) signals and converted to
RGB/YUV signals.
Features
Absolute Maximum Ratings (Ta=25 °C)
• NTSC and PAL encoding modes
• Supply voltage
• Input voltage
• Output voltage
VDD
VI
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
–20 to +75
V
V
• Composite video and separate Y/C video (S-video)
signal output
VO
V
• R, G, B/Y, U and V (BetaCam/SMPTE level) signal
output
• Operating temperature Topr
• Storage temperature
°C
Tstg –40 to +125 °C
(VSS=0 V)
• 8/16-bit pixel data input modes
• 13.5 Mpps pixel rate
• 10-bit 6-channel DAC
Recommended Operating Conditions
• Supports I2C bus (400 kHz) and Sony SIO
• Closed Caption (Line 21, Line 284) encoding
• Macrovision Pay-Per-View copy protection system
: NTSC Rev. 7.0, PAL Rev. 6.1 (Note 1)
• VBID encoding
• Supply voltage
• Input voltage
VDD
VIN
4.75 to 5.25
VSS to VDD
0 to +70
V
V
• Operating temperature Topr
°C
I/O Pin Capacitance
• WSS encoding
• Input pin
CI
11 (Max.)
11 (Max.)
pF
pF
• Supports non-interlace mode
• Monolithic CMOS single 5.0 V power supply
• 100-pin plastic QFP
• Output pin
CO
Note) Test conditions : VDD=VI=0 V, fM=1 MHz
(Note 1)
This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights.
Use of the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E96Z29-TE
CXD1914Q
Block Diagram
—2—
CXD1914Q
Pin Description
Pin
Symbol
I/O
I
Description
No.
Field ID input.
This signal indicates the field ID when resetting the vertical sync.
“H” indicates 1st field.
1
F1
“L” indicates 2nd field.
2
3
4
5
6
TVSYNC
OSDSW
ROSD
I
I
I
I
I
Test pin. Set “L”.
Test pin. Set “L”.
Test pin. Set “L”.
GOSD
Test pin. Set “L”.
BOSD
Test pin. Set “L”.
Vertical sync reset input in active low. This pin is pulled up. This is used for
synchronizing the phases of the external and internal vertical sync signals.
When XVRST= “L”, the internal digital sync generator is reset according to the
F1 status.
7
XVRST
I
System clock input.
8
9
SYSCLK
VSS1
I
—
I
To generate the correct subcarrier frequency, precise 27 MHz is required.
Digital ground.
System reset input in active low.
10 XRST
Set “L” for 40 clocks (SYSCLK) or more during power-on reset.
Pixel data clock signal output for 13.5 MHz.
A 13.5 MHz signal frequency divided from the system clock (SYSCLK) is output
and used as the clock signal when 16-bit pixel data is input.
Digital power supply.
11 PDCLK
O
12
VDD1
—
—
13 NC
Not connected inside the IC.
Field ID output.
When control register bit “FIDS” = “1”, “L” indicates 1st field and “H” indicates
2nd field. When control register bit “FIDS” = “0”, “H” indicates 1st field and “L”
indicates 2nd field.
14 FID
O
15 VSYNC
16 HSYNC
17 CSYNC
O
O
Vertical sync signal output.
Horizontal sync signal output.
O
Composite SYNC output when using RGB output.
Digital ground.
18
VSS2
—
19 PD0
20 PD1
21 PD2
22 PD3
I
I
I
8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is
input. [PD0 to 7]
When control register bit “PIF MODE” = “0”, these are multiplexed Y, Cb, and
Cr signal inputs. When control register bit “PIF MODE” = “1”, these are Y
signal inputs.
I
23
VDD2
—
Digital power supply.
—3—
CXD1914Q
Pin
No.
Symbol
I/O
Description
24 PD4
25 PD5
26 PD6
27 PD7
I
I
I
I
8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is
input. [PD0 to 7]
When control register bit “PIF MODE” = “0”, these are multiplexed Y, Cb, and
Cr signal inputs. When control register bit “PIF MODE" =“1”, these are Y signal
inputs.
28 NC
29 NC
30 NC
31 NC
32 NC
—
—
—
—
—
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
33 PD8 / TD0
34 PD9 / TD1
35 PD10 / TD2
36 PD11 / TD3
I/O Upper 8-bit pixel data inputs/test data bus when 16-bit pixel data is input.
[PD8 to 15]
I/O When control register bit “PIF MODE” = “0”, these inputs are not used. When
control register bit “PIF MODE” = “1”, these are multiplexed Cb and Cr signal
I/O inputs.
In the test mode, these are used for the internal circuit test data bus. The test
I/O data bus is available only for the device vendor.
37
VSS3
—
Digital ground.
38 PD12 / TD4
39 PD13 / TD5
40 PD14 / TD6
41 PD15 / TD7
I/O Upper 8-bit pixel data inputs/test data bus when 16-bit pixel data is input.
[PD8 to 15]
I/O When control register bit “PIF MODE” = “0”, these inputs are not used. When
control register bit “PIF MODE” = “1”, these are multiplexed Cb and Cr signal
I/O inputs.
In the test mode, these are used for the internal circuit test data bus. The test
I/O data bus is available only for the device vendor.
42
VDD3
—
I
Digital power supply.
Serial interface mode select input. This pin is pulled up. When XIICEN = “L”,
Pins 44, 45, 47 and 48 are I2C bus mode.
43 XIICEN
44 XCS/SA
45 SCK/SCL
When XIICEN = “H”, Pins 44, 45, 47 and 48 are Sony SIO mode.
This pin’s function is selected by XIICEN (Pin 43). This pin is pulled up.
When XIICEN = “H”, this pin is Sony SIO mode ; XCS chip select input.
When XIICEN = “L”, this pin is I2C bus mode ; SA slave address select input
which selects the I2C bus slave address.
I
This pin’s function is selected by XIICEN (Pin 43).
I
When XIICEN = “H”, this pin is Sony SIO mode ; SCK serial clock input.
When XIICEN = “L”, this pin is I2C bus mode ; SCL input.
Digital ground.
46
VSS4
—
—4—
CXD1914Q
Pin
No.
Symbol
I/O
Description
This pin’s function is selected by XIICEN (Pin 43).
47 SI/SDA
48 SO
I/O When XIICEN = “H”, this pin is Sony SIO mode ; SI serial data input.
When XIICEN = “L”, this pin is I2C bus mode ; SDA input/output.
This pin’s function is selected by XIICEN (Pin 43).
O
When XIICEN = “H”, this pin is Sony SIO mode ; SO serial out output.
When XIICEN = “L”, this pin is not used and output is high impedance.
Not connected inside the IC.
49 NC
50 NC
51 NC
52 NC
53 NC
—
—
—
—
—
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
DAC reference current input.
54 IREF
I
I
Connect resistance “16R” which is 16 times output resistance “R”.
DAC reference voltage input.
55 VREF
Sets the DAC output full-scale width.
10-bit DAC output. This pin outputs the composite signal.
Analog power supply.
56 CP-OUT
O
—
O
57
58 C-OUT
59
AVDD1
10-bit DAC output. This pin outputs the chroma (C) signal.
Analog ground.
AVSS1
—
—
O
60 NC
61 VB
Not connected inside the IC.
Connect to ground via a capacitor of approximately 0.1 µF.
62 VG
63 NC
64 Y-OUT
O
Connect to analog power supply via a capacitor of approximately 0.1 µF.
Not connected inside the IC.
—
O
10-bit DAC output. This pin outputs the luminance (Y) signal.
Analog power supply.
65
66 B-OUT
67
AVDD2
—
O
10-bit DAC output. This pin outputs the B and V signals.
Analog ground.
AVSS2
—
—
—
—
—
O
68 NC
69 NC
70 NC
71 NC
72 G-OUT
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
10-bit DAC output. This pin outputs the G and Y signals.
Analog power supply.
73
74 R-OUT
75
AVDD3
—
O
10-bit DAC output. This pin outputs the R and U signals.
Analog ground.
AVSS3
—
—
—
—
—
—
—
76 NC
77 NC
78 NC
79 NC
80 NC
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
81
VDD4
Digital power supply.
—5—
CXD1914Q
Pin
No.
Symbol
I/O
Description
82 TD8
I/O Test data I/Os. These pins should be open.
83 TD9
I/O In the test mode, these are used for the internal circuit test data bus. The test
84 TD10
I/O data bus is available only for the device vendor.
I
85 XTEST1
86 XTEST2
87 XTEST3
88 XTEST4
89 XTEST5
I
I
Test mode control signal inputs. These pins are pulled up. When all these
pins are “H”, the CXD1914Q is not in the test mode, but is in the normal mode.
The test mode is available only for the device vendor.
I
I
90
VSS5
—
I
Digital ground.
91 TDI
92 TMS
93 TDO
94 TCK
Test pin. Set “H”. This pin is pulled up.
Test pin. Set “H”. This pin is pulled up.
Test pin. This pin should be open.
Test pin. Set “H”.
I
O
I
Reset signal input for JTAG in active low.
This pin is pulled up.
95 TRST
I
96
VDD5
—
—
—
—
—
Digital power supply.
97 NC
98 NC
99 NC
100 NC
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
Not connected inside the IC.
—6—
CXD1914Q
Electrical Characteristics
DC Characteristics
(Ta=0 to +70 °C, VSS=0 V)
Measurement
Item
Symbol
Measurement conditions
Min.
2.2
Typ.
Max.
0.8
Unit
pins
1
Input High voltage
Input Low voltage
VIH
VIL
VDD=5.0 V ±5 %
VDD=5.0 V ±5 %
IOH=–2.4 mA
V
V
1
Output High voltage
Output Low voltage
Output High voltage
Output Low voltage
Input leak current
Input leak current
Supply current
VOH1
VOL1
VOH2
VOL2
IIL1
2
2
3
3
4
5
VDD–0.8
VDD–0.8
V
V
VDD=4.75 to 5.25 V
IOL=4.8 mA
0.4
VDD=4.75 to 5.25 V
IOH=–1.2 mA
V
VDD=4.75 to 5.25 V
IOL=2.4 mA
0.4
10
V
VDD=4.75 to 5.25 V
VI=0 to 5.25 V
VDD=4.75 to 5.25 V
VI=0 V
–10
–40
µA
µA
mA
IIL2
–100
–240
VDD=5.0 V ±5 %
6
IDD
VDD=5.0 V ±5 %
85
Note :
1 PD0-15, TD8-10, XTEST1-5, TRST, TDI, TMS,TCK, SI/SDA, SCK/SCL, XCS/SA, XVRST, XRST,
SYSCLK, F1, XIICEN, TVSYNC, OSDSW, ROSD, GOSD, BOSD
2 PDCLK, VSYNC, HSYNC, FID, SO, CSYNC
3 TDO, TD0-10
4 PD0-15, TD8-10, TCK, SI/SDA, SCK/SCL, XRST, F1, SYSCLK, TVSYNC, OSDSW,ROSD, GOSD,
BOSD
5 XTEST1-5, TRST, TDI, TMS, XCS/SA, XVRST, XIICEN
6 Not including analog supply current
DAC Characteristics 1
(AVDD=5 V, R=200 Ω, VREF=2.00V , Ta=25 °C)
Item
Symbol Measurement conditions
Min.
Typ.
10
Max.
Unit
bit
Resolution
n
Linearity error
EL
–2.0
–1.0
9.5
2.0
1.0
10.5
1
LSB
LSB
mA
mV
V
Differential linearity error
Output full-scale current
Output offset voltage
Output full-scale voltage
Precision guaranteed output
voltage range
ED
IFS
10.0
VOS
VFS
1.9
1.9
2.0
2.0
2.1
VOC
2.1
V
—7—
CXD1914Q
AC Characteristics
1. Pixel data interface
(1) 8-bit mode
SYSCLK
PD0-7
tPDS
tPDH
(Ta=0 to +70 °C, VDD=4.75 to 5.25 V, VSS=0 V)
Item
Symbol
tPDS
Min.
10
3
Typ.
Max.
Unit
ns
Pixel data setup time to SYSCLK
Pixel data hold time to SYSCLK
tPDH
ns
(2) 16-bit mode
PDCLK
tPDS
tPDH
PD0-15
(Ta=0 to +70 °C, VDD=4.75 to 5.25 V, VSS=0 V)
Item
Pixel data setup time to PDCLK
Pixel data hold time to PDCLK
Symbol
tPDS
Min.
20
0
Typ.
Max.
Unit
ns
tPDH
ns
—8—
CXD1914Q
2. Serial port interface
fSCK
tPWHSCK
tPWLSCK
SCK
XCS
tCSS
tCSH
tSIH
tSIS
SI
tSOD
tSOH
SO
(Ta=0 to +70 °C, VDD=4.75 to 5.25 V, VSS=0 V)
Item
Symbol
fSCK
Min.
DC
100
100
150
150
50
Typ.
Max.
3
Unit
MHz
ns
SCK clock rate
SCK pulse width Low
SCK pulse width High
tPWLSCK
tPWHSCK
tCSS
ns
Chip select setup time to SCK
Chip select hold time to SCK
Serial input setup time to SCK
Serial input hold time to SCK
ns
tCSH
ns
tSIS
ns
tSIH
10
ns
Serial output delay time from SCK
Serial output hold time from SCK
tSOD
30
ns
tSOH
3
ns
CL=35 pF
3. XVRST, F1
SYSCLK
tVS
tVH
XVRST
F1
Item
Symbol
tVS
Min.
10
0
Typ.
Max.
Unit
ns
XVRST, F1 setup time to SYSCLK
XVRST, F1 hold time to SYSCLK
tVH
ns
—9—
CXD1914Q
4. SYSCLK, PDCLK, VSYNC, HSYNC, FID, CSYNC
fSYSCLK
tPWHCLK
tPWLCLK
SYSCLK
PDCLK
tPDCLKD
tPDCLKD
tCOD
VSYNC,
HSYNC,
FID,
tCOH
CSYNC
(Ta=0 to +70 °C, VDD=4.75 to 5.25 V, VSS=0 V)
Item
Symbol
Min.
Typ.
27
Max.
Unit
MHz
ns
SYSCLK clock rate
fSYSCLK
tPWLCLK
tPWHCLK
tPDCLKD
tCOD
SYSCLK pulse width Low
SYSCLK pulse width High
11
11
ns
PDCLK delay time from SYSCLK
20
25
ns
Control output delay time from SYSCLK
Control output hold time from SYSCLK
ns
tCOH
3
ns
CL=35 pF
—10—
CXD1914Q
Description of Functions
The CXD1914Q converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC
(RS170A) or PAL (ITU-R624; B, G, H, I) format.
The CXD1914Q first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit
parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts the Cb and Cr
signals into the U and V signals, respectively, interpolates 4 : 2 : 2 to 4 : 4 : 4, and then modulates the
signals with the digital subcarrier inside the CXD1914Q to create the chroma (C) signal.
The Y and chroma (C) signals are oversampled at double speed to reduce sin (X) / X roll-off, and then
added to become the digital composite signal.
The 10-bit DAC converts the digital composite, Y/C, U, V, and RGB signals into analog signals.
1. Pixel input format
The pixel input format is selected according to the value (bit 4 of address 01H) of control register “PIF
MODE” as shown in Table 1-1 below.
When “PIF MODE” is “0”, the image data (multiplexed Y, Cb, and Cr data) input from PD0 to 7 are sampled
at the rising edge of SYSCLK as shown in the chart on the following page. When “PIF MODE” is “1”, the
image data (PD0 to 7 : Y data, PD8 to 15 : multiplexed Cb and Cr data) input from PD0 to 15 are sampled
at the rising edge of PDCLK.
PIF MODE
0 (8-bit mode)
1 (16-bit mode)
PD15 to 8
N/A
PD7 to 0
Y/Cb/Cr
Y
Cb/Cr
Table 1-1
Also, the pixel input data timing is determined according to bits 3 and 2 (PIX TIM) of control register
address 01H as shown in Table 1-2 below.
When “PIF MODE” is “0", Cb0 of the image data (Cb0, Y0, Cr0 and Y1) input from PD0 to 7 is sampled at
the rising edge of SYSCLK after the fall of HSYNC.
(Default : Cb0 is sampled at the rising edge of the second SYSCLK after the fall of HSYNC.)
When “PIF MODE” is “1”, Y0 and Y1 data are input to PD0 to 7, multiplexed Cb0 and Cr0 data are input to
PD8 to 15, and Y0 and Cb0 are sampled at the respective rising edge of PDCLK after the fall of HSYNC.
(Default : Y0 and Cb0 are sampled at the rising edge of the second PDCLK after the fall of HSYNC.)
PIX TIM
Timing phase
0
0
1
1
0
1
0
1
#0 (default)
#1
#2
#3
Table 1-2
—11—
CXD1914Q
Pixel Data Input Timing
1
2
3
4
5
SYSCLK
1
2
3
PDCLK
HSYNC
[16-bit mode]
PD0 to 7
# 0 #1
Y0
Y1
Y2
Y3
Y4
Y5
PD8 to 15
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Y0
Y1
Y2
Y3
Y4
# 2 #3
Cb0
Cr0
Cb2
Cr2
Cb4
[8-bit mode]
PD0 to 7
# 0
# 1
# 2
# 3
Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2
Y3 Cb4 Y4
Cr4 Y5 Cb6
Y3 Cb4 Y4
Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2
Cb0 Y0
Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4
Cb0 Y0 Cr0
Y1 Cb2 Y2
Cr2 Y3 Cb4 Y4 Cr4 Y5
PD0
PD1
:
Pixel data 0 (LSB)
Pixel data 1
PD8
PD9
:
Pixel data 0 (LSB)
Pixel data 1
:
:
PD7
Pixel data 7 (MSB)
PD15 Pixel data 7 (MSB)
—12—
CXD1914Q
2. Serial interface
The CXD1914Q supports both the I2C bus (high-speed mode) and Sony serial interface modes. These
modes can be selected by the XIICEN input pin as shown in Table 2-1 below.
H
L
I2C Mode
SDA
XIICEN
SONY SIO Mode
SI/SDA
SCK/SCL
XCS/SA
SO
SI
SCK
XCS
SO
SCL
SA
High-Z
Table 2-1
2-1 I2C bus interface
The CXD1914Q becomes an I2C bus slave transceiver, and supports the 7-bit slave address and the
high-speed mode (400 Kbits/s).
2-1-1. Slave address
Two kinds of slave address (88H, 8CH) can be selected by the SA signal as shown in Table 2-2 below.
A6
1
A5
0
A4
0
A3
0
A2
1
A1
SA
A0
0
R/W
X
Table 2-2
2-1-2. Write cycle
S
Slave address
W
A
start address
A
write data
A
write data
A
P
‘0’
from master to slave
from slave to master
D7
D6
D5
D4
D3
D2
D1
D0
Start address
ADR [4 : 0]
After the slave address is supplied from the master, the data in the next transfer cycle is set up inside the
start address register of this IC as the start address of the control register. In subsequent cycles, the data
supplied from the master is written in the addresses indicated by the control register address. The set
control register address is automatically incremented with the completed transfer of each byte of data.
—13—
CXD1914Q
2-1-3. Read cycle
S
Slave address
R
A
read data
A
read data
A
P
‘1’
from master to slave
from slave to master
After the slave address is supplied from the master, subsequent cycles change immediately to read cycles
and only the ID code (address 0CH, 0DH) is read out. During the read cycle, the start address is
automatically set to 0CH.
(Note) In the Sony SIO mode, addresses from 00H to 0DH can be read out.
2-1-4. Handling of the general call address (00H)
The general call address is ignored and there is no ACK response.
—14—
CXD1914Q
2-2. Sony serial interface
The Sony serial interface uses the SCK, XCS, SI and SO signals.
The serial interface is active when the XCS signal is Low and transmits and receives signals to and
from the host.
The first byte after the XCS signal becomes Low is set up as a serial control command. Its data
includes a control register address and read/write mode information for the interface. (See 2-2-1.
Serial control command format.)
The control register address is automatically incremented with the transfer of each byte of data. In the
write mode, the SI signal of the serial input data is sampled at the rising edge of the SCK signal. In
the read mode, the register value is read out as the SO signal of the serial output data at the falling
edge of the SCK signal, and is variable. In this case, the SI signal of the serial input data is ignored.
Serial Interface Timing
SCK
XCS
SI
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D1
D2
D2
D3
D4
D5
D5
D6
D6
D7
LSB
Serial Control Command
MSB
LSB
Serial Data
MSB
SO
D0
D3
D4
D7
Serial Interface Sequence
SCK
XCS
SI
00H
FFH
11H
CEH
02H
00H
01H
Internal address
Control register
address set
Control register
address auto-increment
Control register
address auto-increment
Control Register Address
Control Register Data
00H
01H
02H
FFH
11H
CEH
2-2-1. Serial control command format
D7
D6
D5
D4
D3
D2
D1
D0
WR
ADR [4 : 0]
WR
: Read/write mode
When this bit is “1” :
The serial interface is write mode, and the SI signal of the serial input data is written
in the register.
When this bit is “0” :
The serial interface is read mode, and the register value is read out as the SO
signal of the serial output data.
ADR [4 : 0] : Control register address setting (Initial value of the address)
—15—
CXD1914Q
3. XVRST, F1
The XVRST and F1 signals are used to synchronize with the external V sync.
The XVRST and F1 signals are sampled at the rising edge of SYSCLK, and the F1 signal is sampled when
XVRST is Low. When F1 is High, the internal sync generator is reset to the 1st field, and when F1 is Low, it
is reset to the 2nd field. When XVRST is set to High, the digital sync generator starts operation, and the
sequence of the 1st or 2nd field starts.
In the 16-bit mode, input XVRST with a width of four SYSCLK pulses at the rise of PDCLK.
[8-bit mode]
XVRST Timing
(1st Field)
SYSCLK
XVRST
F1 “H”
(NTSC : 4H)
(PAL : 1H)
Start of 1st field
VSYNC
F-ID
HSYNC
XVRST Timing
SYSCLK
(2nd Field)
XVRST
F1 “L”
(NTSC : 266H)
(PAL : 313H)
Start of 2nd field
VSYNC
F-ID
1/2H
HSYNC
—16—
CXD1914Q
[16-bit mode]
XVRST Timing
(1st Field)
SYSCLK
PDCLK
XVRST
F1 “H”
(NTSC : 4H)
(PAL : 1H)
Start of 1st field
VSYNC
F-ID
HSYNC
XVRST Timing
(2nd Field)
SYSCLK
PDCLK
XVRST
F1 “L”
(NTSC : 266H)
(PAL : 313H)
Start of 2nd field
VSYNC
F-ID
1/2H
HSYNC
—17—
CXD1914Q
4. Closed caption
The CXD1914Q supports closed caption encoding.
ASCII data for closed captions are encoded in line 21 and line 284 by adding a parity bit to every ASCII
data set up in control registers 04H, 05H (data #1 and #2 for line 21) and 06H, 07H (data #1 and #2 for line
284). The control registers (04H to 07H) are double-buffered and ASCII data, which are set up by the serial
interface, are synchronized with VSYNC.
Automatic reset on/off can be selected for ASCII data which has been synchronized with VSYNC by
changing the setting of bit 5 (CCRST) of control register address 03H.
When CCRST=“1”, the control registers (04H, 05H or 06H, 07H) are automatically reset in sync with the
rise of the next VSYNC.
When CCRST=“0” (default), the control registers (04H, 05H or 06H, 07H) are not reset, and the data set
last is held.
Closed Caption Data Renewal Timing
When CCRST=“1”
Field
4 field
1 field
VSYNC
Control registers 04H and 05H set
NEW DATA
SI/SDA
Data 21H
Front-end buffer
OLD DATA
NEW DATA
(7’ h00)
Data 21H
Rear-end buffer
OLD DATA
NEW DATA
Data 284H
Front-end buffer
DATA A
DATA RESET (7’h00)
DATA A
Data 284H
Rear-end buffer
(7’ h00)
2 field
Field
1 field
VSYNC
Control registers 06H and 07H set
NEW DATA
SI/SDA
Data 284H
Front-end buffer
OLD DATA
NEW DATA
(7’ h00)
Data 284H
Rear-end buffer
OLD DATA
NEW DATA
Data 21H
Front-end buffer
DATA A
DATA RESET (7’h00)
DATA A
Data 21H
Rear-end buffer
(7’ h00)
—18—
CXD1914Q
When CCRST=“0”
Field
4 field
1 field
VSYNC
SI/SDA
Control registers 04H and 05H set
NEW DATA
Data 21H
Front-end buffer
OLD DATA
NEW DATA
NEW DATA
Data 21H
Rear-end buffe
OLD DATA
DATA A
Data 284H
Front-end buffer
Data 284H
Rear-end buffe
DATA A
Field
1 field
2 field
VSYNC
Control registers 06H and 07H set
NEW DATA
SI/SDA
Data 284H
Front-end buffer
OLD DATA
NEW DATA
Data 284H
Rear-end buffe
OLD DATA
DATA A
NEW DATA
Data 21H
Front-end buffer
Data 21H
Rear-end buffe
DATA A
Double Buffer for Closed Caption
SI
04H
VSYNC
Load ASCII data #1
Closed Caption Signal Waveform
HSYNC Color Burst
Clock Run-In
Start Bits
ASCII Data #1
ASCII Data #2
S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2
50 IRE
—19—
CXD1914Q
5. VBID (Video ID)
The CXD1914Q supports encoding of Video ID (Provisional Standard EIAJ CPX-1204) to discriminate the
aspect ratio. VBID is 14-bit data as shown in Table 5-1, and becomes 20-bit data with the addition of 6-bit
CRCC. These data are superimposed and output to lines 20 and 283 during the vertical blanking period of
NTSC video signals.
The data setting in Table 5-1 below is done by writing data in control registers (08H and 09H) via the serial
interface. These control registers (08H and 09H) are double-buffered, and the VBID data are renewed in
sync with the VSYNC signal.
bit-No.
Contents
Transmission aspect ratio
Image display format
Undefined
“1”
“0”
1
Full-mode (16 : 9)
Letter-box
4 : 3
A
B
2
Normal
3
Word 0
4
Identification information about video and other signals (audio signals, etc.)
incidental to image which are transmitted simultaneously
5
6
Word 1
Word 2
4-bit width
4-bit width
Identification signal incidental to Word 0
Identification signal and information incidental to Word 0
Table 5-1
Double Buffer for VBID
SI
08H
VSYNC
Load
Word 0
VBID Data Renewal Timing
VSYNC
Control register 08H set
NEW DATA
SI
Data #1
OLD DATA
NEW DATA
—20—
CXD1914Q
VBID Code Allocation
The VBID data are composed of Word 0=6 bits (Word 0-A=3 bits and Word 0-B=3 bits), Word 1=4 bits,
Word 2=4 bits, and CRCC=6 bits.
bit 0…
…bit 20
Data
0-A
0-B
Word 1
4 bits
Word 2
4 bits
CRCC
6 bits
Word 0
6 bits
VBID Signal Waveform
…
Ref.
bit 1 bit 2 bit 3
bit 20
2.235µs±20ns
49.1µs±0.5µs
11.2µs±0.6µs
1H
6. RGB/YUV output
The CXD1914Q has an RGB/YUV output function. RGB and YUV can be switched by setting bit 2 (RGB_
UV) of control register address 03H. Also, the UV level can be selected from BetaCam or SMPTE by
setting bit 0 (BTCM) of address 03H. During RGB output, when bit 1 (GSYNC) of control register address
03H is “1”, the sync signal is added to the G signal and output ; when bit 1 (GSYNC) is “0”, the sync signal
is not added.
7. Support of interlace/non-interlace modes
The CXD1914Q can be switched to the interlace and non-interlace modes by varying the setting of bit 1
(INTERLS) of control register address 01H. During the non-interlace mode, the 1st field is repeatedly
output.
Register setting
value INTERLS
0 (non-interlace)
1 (interlace)
Number of lines/field
NTSC
PAL
312
262
262.5
312.5
—21—
CXD1914Q
8. WSS (Widescreen Signaling)
The CXD1914Q supports WSS encoding to discriminate the aspect ratio. WSS is 14-bit data as shown in
Table 6-1. These data are superimposed and output to line 23 during the vertical blanking period of PAL
video signals.
The data setting in Table 6-1 below is done by writing data in control registers (0AH and 0BH) via the serial
interface. These control registers (0AH and 0BH) are double-buffered, and the WSS data are renewed in
sync with the VSYNC signal.
Group 1
Group 2
Aspect ratio information (4 bits)
PAL plus related information (4 bits)
b0-b3
b4-b7
0001 Normal
1000 Letter-box 14 : 9
0100 Letter-box 14 : 9
1101 Letter-box 16 : 9
0010 Letter-box 16 : 9
1011 Letter-box >16 : 9
0111 Full-mode 14 : 9
1110 Full-mode 16 : 9
Center
Top
bit4
Camera/Film mode
bit5-7 Reserved
(Color plus)
(Helper)
Center
Top
Center
(Baseband Helper)
b3 is odd parity.
Group 3
Group 4
Subtitle information (3 bits)
Undefined (3 bits)
b8-b10
bit8
b11-b13
TeleText subtitle enable/disable
bit9, 10
00 No subtitle
Reserved
10 Subtitle inside screen
01 Subtitle in black portion
11 Reserved
Table 6-1
Double Buffer for WSS
SI
0AH
VSYNC
Load
Group 1, 2
WSS Data Renewal Timing
VSYNC
Control register 0AH set
NEW DATA
SI
Data #1
OLD DATA
NEW DATA
—22—
CXD1914Q
WSS Signal Waveform
…
bit 0 bit 1 bit 2 bit 3
bit 13
649
71.4 IRE
RUN Start
-IN Code
256
20
0 IRE
11.03µs
10.67µs
16.59µs
—23—
CXD1914Q
Signal Waveform of NTSC Vertical Blanking Interval (Interlace mode)
—24—
CXD1914Q
Signal Waveform of PAL Vertical Blanking Interval (Interlace mode)
—25—
CXD1914Q
Signal Waveform of NTSC Vertical Blanking Interval (Non-interlace mode)
—26—
CXD1914Q
Signal Waveform of PAL Vertical Blanking Interval (Non-interlace mode)
—27—
CXD1914Q
Sync Signal Timing
0.148µs
0.148µs
2.3µs
29.5µs
27.1µs
4.67µs
1/2H
63.555µs
NTSC Equalizing Pulse and Sync Pulse Signal Waveform
0.296µs
0.296µs
2.37µs
29.63µs
27.3µs
4.67µs
1/2H
64µs
PAL Equalizing Pulse and Sync Pulse Signal Waveform
—28—
CXD1914Q
Control Register Map
When “0” or “1” is indicated in the map, fix the respective bits to these values.
BIT
Function Selection #1
7
6
5
4
0
3
2
1
0
0
ENC
MODE
Address
00H
MASK
EN
PIX
EN
FIDS
BF
SET UP
R/W
ENC MODE
SET UP
BF
Encoding mode
0
1
: PAL encoding mode
: NTSC encoding mode (Default)
Setup enable
0
1
: No setup level, black level=blanking level
: 7.5 IRE setup level insertion (Default)
Burst flag enable
0
1
: Disable burst flag
: Enable burst flag (Default)
PIX EN
MASK EN
FIDS
Pixel data enable
0
1
: Disable input pixel data
: Enable input pixel data (Default)
Mask enable
0
1
: Pixel data through during vertical blanking
: Pixel data reject during vertical blanking (Default)
FID polarity select
0
1
: 1st field “H”, 2nd field “L”
: 1st field “L”, 2nd field “H” (Default)
—29—
CXD1914Q
BIT
Function Selection #2
7
6
5
4
3
2
1
0
1
Address
DAC
PIF
MODE
INTERLS
MODE
PIX TIM
R/W
01H
INTERLS
0
1
: Non-interlace mode
: Interlace mode (Default)
PIXTIM
Pixel input timing
0 0 : #0 (Default)
0 1 : #1
1 0 : #2
1 1 : #3
PIF MODE
Pixel input format
0
1
: 8-bit mode, multiplexed Y, Cb, Cr (4 : 2 : 2) (Default)
: 16-bit mode, Y and multiplexed Cb, Cr (4 : 2 : 2)
DAC MODE DAC output activity
0 0 0 : Non-active
0 0 1 : Comp-Out active
0 1 0 : Inhibit
0 1 1 : Video signal (Y, C, Comp) -Out active (Default)
1 0 0 : Inhibit
1 0 1 : R, G, B-Out and Comp-Out active
1 1 0 : Inhibit
1 1 1 : All outputs active
Function Selection #3
7
6
0
5
0
4
0
3
2
1
0
Address
02H
0
VBID
WSS
CC Mode
R/W
CC MODE
Closed caption encoding mode
0 0 : Disable closed caption encoding (Default)
0 1 : Enable encoding in 1st field (Line 21)
1 0 : Enable encoding in 2nd field (Line 284)
1 1 : Enable encoding in both fields
WSS
VBID
WSS encoding enable
0
1
: Disable WSS encoding (Default)
: Enable WSS encoding
VBID encoding enable
0
1
: Disable VBID encoding (Default)
: Enable VBID encoding
—30—
CXD1914Q
BIT
Function Selection #4
7
6
5
4
3
0
2
1
0
Address
03H
RGB_UV
CCRST
0
GSYNC BTCM
R/W
BTCM
UV output level control
0
1
: SMPTE
: BetaCam (Default)
GSYNC
RGB_UV
CCRST
GON SYNC enable
0
1
: Disable (Default)
: Enable
RGB/YUV output mode switching
0
1
: YUV (Default)
: RGB
Closed caption character RESET enable
0
1
: Disable (Default)
: Enable
Closed Caption Character #1 (Line 21H)
7
6
5
4
3
2
1
0
0
0
0
Address
04H
ASCII Data #1
(Default : 0H)
R/W
R/W
R/W
R/W
Closed Caption Character #2 (Line 21H)
7
6
5
4
3
2
1
Address
05H
ASCII Data #2
(Default : 0H)
Closed Caption Character #1 (Line 284H)
7
6
5
4
3
2
1
Address
06H
ASCII Data #1
(Default : 0H)
Closed Caption Character #2 (Line 284H)
7
6
5
4
3
2
1
Address
07H
ASCII Data #2
(Default : 0H)
—31—
CXD1914Q
BIT
VBID #1
7
7
6
5
5
4
3
3
2
2
1
0
0
Address
08H
Word 0
R/W
Word 0-B
Word 0-A
VBID #2
6
4
1
1
Address
09H
Word 2
Word 1
R/W
R/W
R/W
RO
WSS #1
7
6
5
4
3
2
0
Address
0AH
Group 2
bit 6
Group 1
bit 1
bit 7
bit 5
bit 4
bit 3
bit 2
bit 0
WSS #2
7
6
6
5
4
3
2
1
0
Address
0BH
Group 4
bit 12
Group 3
bit 9
bit 13
bit 11
bit 10
bit 8
Device ID #1
7
5
4
3
2
1
0
0
Address
0CH
ID Code
Identification code : 14H
(Lower) 14H
ID code
Device ID #2
7
6
5
4
3
2
1
Address
0DH
ID Code
(Upper) 19H
RO
ID code
Identification code : 19H
—32—
CXD1914Q
Video Signal Timing (NTSC, 7.5 IRE Setup)
806
806
WHITE LEVEL
748
655
597
506
100 IRE
448
7.5 IRE
355
297
BLACK LEVEL
BLANK LEVEL
256
40 IRE
36
SYNC LEVEL
NTSC Y (luminance) signal output waveform
7.5 IRE setup
832
622
512
402
20 IRE
BLANK LEVEL
COLOR BURST
192
NTSC C (chroma) signal output waveform
7.5 IRE setup
—33—
CXD1914Q
Video Signal Timing (NTSC, No Setup)
806
806
WHITE LEVEL
744
643
580
100 IRE
482
419
318
BLANK LEVEL
SYNC LEVEL
256
40 IRE
36
NTSC Y (luminance) signal output waveform
859
622
512
402
20 IRE
BLANK LEVEL
COLOR BURST
165
NTSC C (chroma) signal output waveform
—34—
CXD1914Q
Video Signal Timing (PAL)
806
806
WHITE LEVEL
744
643
580
100 IRE
482
419
318
BLANK LEVEL
SYNC LEVEL
256
43 IRE
20
PAL Y (luminance) signal output waveform
859
630
21.5 IRE
512
394
BLANK LEVEL
COLOR BURST
165
PAL C (chroma) signal output waveform
—35—
CXD1914Q
RGB Signal Output Waveform
R signal
806
806
257
257
805
805
256
256
806
WHITE LEVEL
BLANK LEVEL
100 IRE
256
G signal
806
807
806
806
256
256
256
256
806
WHITE LEVEL
100 IRE
BLANK LEVEL
WHITE LEVEL
256
During GON SYNC (NTSC)
806
100 IRE
BLANK LEVEL
SYNC LEVEL
256
40 IRE
36
During GON SYNC (PAL)
806
WHITE LEVEL
100 IRE
BLANK LEVEL
SYNC LEVEL
256
43 IRE
20
B signal
806
257
808
259
803
256
806
256
806
WHITE LEVEL
BLANK LEVEL
100 IRE
256
—36—
CXD1914Q
UV Output Level
Color Difference (U) Signal
SMPTE LEVEL
BetaCam LEVEL
782
901
690
768
603
643
512
512
421
381
334
256
242
123
153
237
NTSC, No setup
NTSC, No setup
761
871
677
750
596
633
512
512
428
391
347
274
263
NTSC, Setup
NTSC, Setup
787
787
693
693
605
605
512
512
419
419
331
331
237
PAL
PAL
—37—
CXD1914Q
Color Difference (V) Signal
SMPTE LEVEL
BetaCam LEVEL
782
901
738
838
555
574
570
556
512
512
469
450
286
186
242
123
NTSC, No setup
NTSC, No setup
761
721
871
813
552
512
512
471
453
303
211
263
153
NTSC, Setup
NTSC, Setup
787
742
787
742
556
512
512
468
468
282
282
237
237
PAL
PAL
—38—
CXD1914Q
Internal Filter Characteristics
Interpolation Filter Characteristic
0
–10
–20
–30
–40
–50
0
1
2
3
4
5
6
7
8
9
10 11 12 13
Frequency [MHz]
Chrominance Filter Characteristic
0
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
7
8
9
10
Frequency [MHz]
—39—
CXD1914Q
DAC Application Circuit
CXD1914Q
AVDD
VG
0.1µF
VREF
1kΩ
3.2kΩ
IREF
AVSS
Buff AMP
LPF
COMP-O
Y-OUT
C-OUT
75Ω
0.1µF
R/U-OUT
G/Y-OUT
B/V-OUT
VB
200Ω
VSS
Application Circuit
CXD1914Q
(Video encoder)
MPEG decoder
8
PD0 to 7
PD0 to 7
FID
HSYNC
VSYNC
FID
HSYNC
VSYNC
CLK
SYSCLK
27MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—40—
CXD1914Q
Package Outline Unit : mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
80
51
50
81
A
31
100
1
30
+ 0.15
0.65
+ 0.35
2.75 – 0.15
0.3 – 0.1
0.13
0.15
M
+ 0.2
0.1 – 0.05
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
QFP100-P-1420
SONY CODE
EIAJ CODE
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.7g
JEDEC CODE
—41—
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