CXD2442Q_技术文档

CXD2442Q

Timing Generator for LCD Panels

For the availability of this product, please contact the sales office.

Description

80 pin QFP (Plastic)

The CXD2442Q is a timing signal generator for the

SVGA LCD panel LCX016 and VGA LCD panel

LCX012BL driver. This chip has a built-in serial

interface circuit which supports various SVGA and

VGA signals as well as double-speed NTSC and

PAL signals through external control from a

microcomputer, etc.

Features

Applications

• Generates the LCX016/LCX012BL drive pulse.

• Supports various SVGA and VGA signals.

(LCX016/LCX012BL)

LCD projectors, etc.

Structure

LCX016

Silicon CMOS IC

• Aspect conversion performed at the panel side for

the 832 × 624 (Macintosh17), 800 × 600 (SVGA),

640 × 480 (VGA/NTSC), 762 × 572 (PAL),

640 × 400 (PC-98), 832 × 480 (WIDE) modes.

• Line double-speed display realized with a built-in

double-speed controller. (NTSC/PAL) (Line memory

µPD485505: NEC)

Absolute Maximum Ratings (Ta = 25°C, V^SS= 0V)

• Supply voltage

• Input voltage

• Output voltage

VDD

VI

VSS – 0.5 to +7.0

V

VSS – 0.5 to VDD + 0.5

VO VSS – 0.5 to VDD + 0.5

• Operating temperature

Topr

• Storage temperature

Tstg

–20 to +75

°C

LCX012BL

• 640 × 480 (VGA/NTSC/PAL)

–55 to +150

• Line double-speed display realized with a built-in

double-speed controller. (NTSC/PAL) (Line memory

µPD485505: NEC)

Recommended Operating Conditions

• Supply voltage

VDD

4.5 to 5.5

V

• Supports double-speed PAL pulse eliminate.

• Supports SVGA pulse eliminate.

• Supports PC-98 (640 × 400) line display.

• Generates timing signal of external sample-and-

hold circuit. (for RGB driver and high voltage drive

sample and hold)

• Operating temperature

Topr

–20 to +75

°C

• Supports up/down and/or right/left inversion.

• Supports 1H inversion.

• AC drive of LCD panels during no signal

Note) "Macintosh" is a registered trademark of Apple Computer Inc..

"PC-98" is a registered trademark of NEC.

"VGA" is a registered trademark of IBM.

Other company names and product names, etc. contained in these materials are trademarks or registered

trademarks of the respective companies.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E96537-ST

CXD2442Q

Block Diagram

VDD: 24, 33, 48, 73 VSS: 2, 12, 17, 23, 32, 38, 42, 52, 63, 72

7

6

PWM

PEO

3

CKI2

CKLIM

CKI1

25

11

74 XCLR

75 PRE

DIRECT CLEAR

MASTER CLOCK

CKO1

10

4

13 TC

9

8

RPD

FPD

PLL PHASE COMPARATOR

1

HDN

RSTR

RCK

RSTW

WCK

HD

H-SYNC DETECTOR

HSYNC

68

69

70

71

80

PLL COUNTER

DECODER

V-SYNC SEPARATOR

V-RESET PULSE GENERATOR

5

VSYNC

14

15

SCTR

SCLK

V-CONTROL COUNTER

16 SDAT

49

RGT

50 XRGT

51

MODE3

SERIAL I/F

53 MODE2

54 MODE1

67 DWN

V-POSITION COUNTER

BLK 58

VCK 61

27 XCLP1

H-POSITION COUNTER

XCLP2

PRG

SHD1

SHD2

SHD3

SHD4

SH1

62

78

79

28

29

34

35

36

37

39

40

41

43

44

45

46

47

55

VST

FLDI

DECODER

&

V-TIMING PULSE

GENERATOR

FLDO

DECODER

&

H-TIMING PULSE

GENERATOR

PULSE ELIMINATOR

SH2

30

31

FRP

SH3

XFRP

SH4

TST1 18

TST2 19

SH5

SH6

TST3

20

TST4 21

TST5

SH7

SH8

AUX-VD COUNTER

DECODER

22

HST

FIELD & LINE CONTROLLER

TST6 26

TST7 64

TST8 66

TST9 76

TST10 77

56 HCK1

57

59

60

65

HCK2

CLR

ENB

PCG

– 2 –

CXD2442Q

Pin Description

Input pin for

open status

Symbol

No.

I/O

Description

Phase comparison pulse output

1

2

3

4

5

6

7

8

9

HDN

O

—

I

—

H

Vss

GND

CKI2

HSYNC

VSYNC

PEO

Clock input pin (SVGA, VGA)

Horizontal sync signal input pin

Vertical sync signal input pin

I

I/O Loop filter integrator output pin (AV)

PWM

FPD

I

Loop filter integrator input pin (AV)

Phase comparator output pin (AV)

O

RPD

10 CKO1

11 CKI1

12 Vss

I/O Oscillation cell output pin (AV)

I

Oscillation cell input pin (AV)

GND

—

13 TC

I/O FPD output pulse width adjustment pin

14 SCTR

15 SCLK

16 SDAT

17 Vss

I

Chip select input pin (serial transfer block)

Serial clock input pin (serial transfer block)

Serial data input pin (serial transfer block)

GND

I

—

I

18 TST1

19 TST2

20 TST3

21 TST4

22 TST5

23 Vss

Test pin (Not connected.)

Test pin (Connect to GND.)

GND

24

V^DD

Power supply

25 CKLIM

26 TST6

27 XCLP1

28 XCLP2

29 PRG

30 FRP

CKI1 input limit pin (High: CKI1 input enabled, Low: Disabled)

Test pin (Not connected.)

—

O

—

Pedestal clamp pulse 1 output (negative polarity)

Pedestal clamp pulse 2 output (negative polarity)

Precharge signal pulse output (positive polarity)

AC drive inversion timing output

AC drive inversion timing output (reverse polarity of FRP)

GND

31 XFRP

32 Vss

33

VDD

Power supply

– 3 –

CXD2442Q

No.

Input pin for

open status

Symbol

I/O

Description

34 SHD1

35 SHD2

36 SHD3

37 SHD4

38 Vss

O

—

O

—

O

—

O

—

O

—

O

—

O

Sample-and-hold pulse 1 output (for driver/positive polarity)

Sample-and-hold pulse 2 output (for driver/positive polarity)

Sample-and-hold pulse 3 output (for driver/positive polarity)

Sample-and-hold pulse 4 output (for driver/positive polarity)

GND

—

39 SH1

40 SH2

41 SH3

42 Vss

Sample-and-hold pulse 1 output (for high voltage drive sample and hold/positive polarity)

Sample-and-hold pulse 2 output (for high voltage drive sample and hold/positive polarity)

Sample-and-hold pulse 3 output (for high voltage drive sample and hold/positive polarity)

GND

43 SH4

44 SH5

45 SH6

46 SH7

47 SH8

Sample-and-hold pulse 4 output (for high voltage drive sample and hold/positive polarity)

Sample-and-hold pulse 5 output (for high voltage drive sample and hold/positive polarity)

Sample-and-hold pulse 6 output (for high voltage drive sample and hold/positive polarity)

Sample-and-hold pulse 7 output (for high voltage drive sample and hold/positive polarity)

Sample-and-hold pulse 8 output (for high voltage drive sample and hold/positive polarity)

Power supply

48

V^DD

49 RGT

50 XRGT

51 MODE3

52 Vss

Right/left inversion discrimination signal output (High: Right, Low: Left)

Right/left inversion discrimination signal output (High: Left, Low: Right)

Mode switching pin 3 output

GND

53 MODE2

54 MODE1

55 HST

56 HCK1

57 HCK2

58 BLK

Mode switching pin 2 output

Mode switching pin 1 output

H start pulse output

H clock 1 pulse output

H clock 2 pulse output

BLK pulse output (positive polarity)

59 CLR

60 ENB

61 VCK

62 VST

CLR pulse output (positive polarity)

ENB pulse output (negative polarity)

V clock pulse output

V start pulse output

63 Vss

GND

64 TST7

65 PCG

66 TST8

67 DWN

Test pin (Not connected.)

PCG pulse output (positive polarity)

Test pin (Not connected.)

Up/down inversion discrimination signal output (High: Down, Low: Up)

– 4 –

CXD2442Q

No.

Input pin for

open status

Symbol

I/O

Description

68 RSTR

69 RCK

70 RSTW

71 WCK

72 Vss

O

—

I

Reset read output (for high-speed line buffer/negative polarity)

Read clock output (for high-speed line buffer)

Reset write output (for high-speed line buffer/negative polarity)

Write clock output (for high-speed line buffer)

GND

—

H

73

VDD

Power supply

74 XCLR

75 PRE

76 TST9

77 TST10

78 FLDI

79 FLDO

80 HD

System clear pin (Low: All clear)

I

Preset pin (Preset to Macintosh17 mode when Low.)

Test pin (Not connected.)

H

—

I

—

Test pin (Not connected.)

Field discrimination signal input

O

Field discrimination signal output

HD pulse output (positive polarity)

H: Pull up, L: Pull down

– 5 –

CXD2442Q

Electrical Characteristics

1. DC characteristics

(VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to + 75°C)

Item

Applicable pins

Symbol

VDD

VI, Vo

VIH

Conditions

Typ.

5.0

Max.

5.5

Unit

V

Min.

4.5

Supply voltage

Input, output voltages

Vss

V^DD

V

0.7VDD

1

V

Input voltage 1

CMOS input

VIL

0.3VDD

0.8

Vt+

2.2

TTL Schmitt

trigger input

HSYNC

VSYNC

Input voltage 2

Vt–

Vt+ – Vt–

Vt+

0.4

0.6

0.8VDD

CMOS Schmitt

trigger input

Input voltage 3

Vt–

0.2VDD

V

TC

Vt+ – Vt–

VOH

VOL

VOH

VOL

VOH

VOL

II

I^OH= –2mA

IOL = 4mA

IOH = –4mA

IOL = 8mA

IOH = –3mA

VDD – 0.8

VDD/2

V

Output voltage 1

Output voltage 2

Output voltage 3

2

3

0.4

CKO1,

PEO

IOL = 3mA

VDD/2

10

4

–10

–40

5

6

Input leak current

IIL

–100

–240

40

7

µA

8

II

9

10

12

Output leak current

IOZ

40

11

Current consumption

IDD

80

mA At a 30pF load

1

PRE, SCLK, SDAT, SCTR, XCLR, FLDI, CKLIM, CKI1, CKO1, CKI2, PWM, PEO

2

3

MODE1, MODE2, MODE3, HD, HDN, CLR, ENB, PRG, PCG, HST, XCLP1, XCLP2, VST, BLK, FRP,

XFRP, VCK, DWN, FLDO, FPD, TC, RPD, RGT, XRGT

RSTR, RSTW, RCK, WCK, SH1, SH2, SH3, SH4, SH5, SH6, SH7, SH8, SHD1, SHD2, SHD3, SHD4,

HCK1, HCK2

4

Normal input pins (VIN = VSS or VDD)

HSYNC, VSYNC, SCLK, SDAT, SCTR, CKI2

Pins with pull-up resistors (VIN = VSS)

PRE, XCLR, CKLIM

5

6

7

8

Bi-directional pins (input status, VIN = VSS or VDD)

CKO1, PEO, TC

9

10

11

12

At high impedance (VIN = VSS or VDD)

RPD, FPD

fclk = 60MHz, VDD = 5.5V

– 6 –

CXD2442Q

2. AC characteristics

(VDD = 5.0 ± 0.5V, Vss = 0V, Topr = –20 to +75°C)

Applicable pins

CKI1

Min.

28.5

16.6

Typ.

Item

Symbol

Max. Conditions Unit

Clock input cycle

CKI2

Output rise time

All outputs

HCK1, 2

All outputs

HCK1

tr

tf

20

10

15

52

CL = 30pF

ns

%

Output fall time

Cross-point time difference

Output rise delay time

Output fall delay time

HCK1 Duty

∆t

–10

tpr

tpf

t

H/(tH + tL)

L/(tH + tL)

48

HCK2 Duty

HCK2

t

Note) SHP6, 5, 4, 3, 2, 1, 0: LLLLLLL (LSB), HDN4, 3, 2, 1, 0: LLLLL (LSB), SHD2, 1, 0: HHH (LSB),

SH2, 1, 0: HLH (LSB)

The minimum value for the clock input cycle (CKI2) differs according to the mode used.

3. Serial transfer AC characteristics

(VDD = 5.0 ± 0.5V, Vss = 0V, Topr = –20 to +75°C)

Item

Min.

4Tns

2Tns

4Tns

2Tns

5Tns

Typ.

Max.

Symbol

ts0

ts1

SCTR setup time with respect to rise of SCLK

SDAT setup time with respect to rise of SCLK

SCTR hold time with respect to rise of SCLK

SDAT hold time with respect to rise of SCLK

SCLK pulse width

th0

th1

tw1L

tw1H

tw2

tw3

SCLK pulse width

T: Master clock cycle (ns)

– 7 –

CXD2442Q

4. Timing definitions

AC characteristics

VDD

0V

100%

CKI1/2

Output

tpr

VDD

0V

90%

10%

tr

tf

VDD

0V

90%

tpf

Output

VDD

50%

HCK1

0V

VDD

0V

HCK2

50%

∆t

50%

HCK1

tH

tL

Note) HCK2 is the reverse phase of HCK1.

Serial transfer AC characteristics

ts0

th0

tw3

SCTR

50%

tw1L

ts1

tw1H

th1

tw2

SCLK

SDAT

50%

th1

ts1

D15

D14

D9

D7

D0

D8

Note) See "Serial transfer timing" on P. 14 for the timing relationship between D15 to D0 and each pulse.

– 8 –

CXD2442Q

Dot Arrangement

The LCD panels supported by the CXD2442Q are the LCX016 and the LCX012BL. The dot arrangement is a

square arrangement for both panels. The shaded region in the diagram is not displayed, however, for the

LCX016, since the CXD2442Q has a built-in display area variable circuit, the number of display area dots

varies according to the mode ¹to match the various signal protocols.

LCX016 Dot Arrangement

Gate SW

Photo-shielding

area

Display area

4 dots

832 dots

840 dots

4 dots

Number of horizontal Number of vertical

Number of

display dots

MODE1 MODE2 MODE3

Display mode

display dots

L

H

L

Macintosh17

SVGA

832

624

519,168

480,000

435,864

307,200

256,000

399,360

800

600

L

H

L

PAL

762

572

H

L

VGA/NTSC

PC-98

640

480

H

640

400

H

L

WIDE

832

480

1

Unit: dot

See the description of serial data specifications for details.

– 9 –

CXD2442Q

LCX012BL Dot Arrangement

Gate SW

Photo-shielding

area

Display area

5 dots

644 dots

654 dots

5 dots

Number of horizontal

display dots

Number of vertical

display dots

Number of

display dots

644

484

311,696

Unit: dot

– 10 –

CXD2442Q

Input Signal Protocol

1. Horizontal sync signal

a) A standard signal (HSYNC) should be input for the following display modes.

LCX016:

Macintosh17 (832 × 624), SVGA (800 × 600), VGA/NTSC (640 × 480), PC-98 (640 × 400),

PAL (762 × 572), WIDE (832 × 480)

LCX012BL: VGA/NTSC/PAL (640 × 480), PC-98 (640 × 400)

However, since the CXD2442Q must be combined with a double-speed scan converter (CXD2428Q) for

NTSC/PAL double-speed display when not using the built-in double-speed controller, a double-speed

(see the CXD2428Q double-speed specifications), 1/2 cycle, 1/2 width horizontal sync signal (HSYNC)

should be input as the standard protocol signal.

b) The input sync signal polarity is not fixed, and is set by the serial data (HPOL).

2. Vertical sync signal

a) A sync-separated, normal-speed VSYNC should be input as the vertical sync signal. However, CSYNC

is also supported during NTSC/PAL display (when using the built-in double-speed controller) mode.

b) The input sync signal polarity is not fixed, and is set by the serial data (VPOL).

c) The phase relationship between HSYNC and VSYNC is specified as follows for the CXD2442Q.

(1) Macintosh17, SVGA, VGA, PC-98, WIDE (LCX016)/VGA, PC-98 (LCX012BL)

HSYNC

VSYNC

Sync signal phase reference

(2) Double-speed NTSC (LCX016/LCX012BL)

Double-speed HSYNC

VSYNC

Sync signal phase reference

(3) Double-speed PAL (LCX016/LCX012BL)

Double-speed HSYNC

VSYNC

Sync signal phase reference

– 11 –

CXD2442Q

(4) NTSC (LCX016/LCX012BL)

ODD FIELD

HSYNC

VSYNC

EVEN FIELD

HSYNC

VSYNC

Sync signal phase reference

(5) PAL (LCX016/LCX012BL)

ODD FIELD

HSYNC

VSYNC

EVEN FIELD

HSYNC

VSYNC

Sync signal phase reference

Notes) (2) and (3) show the timing when using a double-speed scan converter (CXD2428Q).

(4) and (5) show the timing when using the built-in double-speed controller (CXD2442Q) and a line

memory (µPD485505: NEC)

– 12 –

CXD2442Q

Description of Operation

Sync signal input

The HSYNC and VSYNC input pins support both separate SYNC and CSYNC. When using the CXD2442Q

with CSYNC input, input CSYNC to both pins. (However, CSYNC input is supported only when using the built-

in double-speed controller.)

Clock input

The CXD2442Q has two clock input pin systems to support two types of PLL circuits

(1) CKI1 pin

A PLL circuit is comprised by the built-in phase comparator and an external VCO circuit. CKI1 is the clock

input pin when using this system, and supports the NTSC and PAL double-speed display modes (systems

which use the built-in double-speed controller). The PLL clock for this system is adjusted by setting the

RPD and FPD transition points so that they fall at the center of the windows as shown in the diagram

below. (See the Application Circuit.)

a

HSYNC

RPD

Output waveform during PLL lock

500ns

b

FPD

b

(2) CKI2 pin

This is the clock input pin when using an external PLL IC. The 1/N frequency divider output is output from

the HDN pin for the PLL IC. The HDN polarity at this time is set by the serial data HPOL.

The HDN width is calculated using the frequency division ratio N/2.

N fH

HSYNC

HDN

HPOL: L

HPOL: H

fH: Master clock cycle (1 dot)

N/2 fH

AC driving of LCD panels for no signal

The following measures have been adopted to allow AC driving of LCD panels even when there is no signal.

Horizontal direction pulse

The PLL is set to free running status. Therefore, the frequency of the horizontal direction pulse is

dependent on the PLL free running frequency.

Vertical direction pulse

The number of lines is counted by an internal counter (AUX-VD COUNTER) and the vertical direction

pulses (VST, FRP) are output at a specified cycle. For the CXD2442Q, no signal (free running) status is

judged if there is no VSYNC input for longer than the following (free running detection) periods.

Mode

NTSC

V cycle for no signal

Free running detection

263H

313H

650H

468H

900H

PAL

Other

Note) NTSC and PAL modes are the modes when using the built-in double-speed controller.

– 13 –

CXD2442Q

XCLR pin

The CXD2442Q should be forcibly reset during power on in order to initialize the serial transfer block and other

internal circuits.

Serial transfer operation

1. Control method

The CXD2442Q operation timing is controlled by serial data.

The control data is comprised of an 8-bit address and 8-bit data, and the individual data is fetched at the rise

of SCLK. This fetching operation starts from the fall of SCTR and is completed at the next rise of SCTR.

Serial Transfer Timing

SCTR

SCLK

SDAT

D15 D14 D13 D12 D11 D10 D9

Address

D8

D7

D6

D5

D4

D3

D2

D1

D0

Data

2. Control data

When using the CXD2442Q, set the control data corresponding to each signal source according to the formats

in the table below.

Data

D4

Address

Function

D15 D14 D13 D12 D11D10 D9 D8 D7

D6

—

D5

—

D3

—

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

—

PLLP10 PLLP9 PLLP8

(A) PLL frequency

division ratio (1/N)

1 PLLP7 PLLP6 PLLP5 PLLP4 PLLP3 PLLP2 PLLP1 PLLP0

(B) H-POSITION

0

1

0

1

0

1

0

1

0

1

HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0

VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0

(C) V-POSITION

(D) HDN-POSITION

(E) SH-POSITION

(F) HCK-POSITION

(G) HST-POSITION

(H) CLP-POSITION

CLPP1 CLPP0

—

HDNP4 HDNP3 HDNP2 HDNP1 HDNP0

SHP6 SHP5 SHP4 SHP3 SHP2 SHP1 SHP0

—

HCKP3 HCKP2 HCKP1 HCKP0

HSTP3 HSTP2 HSTP1 HSTP0

—

SHD2 SHD1 SHD0

SH2 SH1 SH0

(I) Mode settings

MBK2 MBK1 MBK0 MBKB MBKA

0 FRP1 FRP0 VPOL HPOL MODE MODE3 MODE2 MODE1

1

CK

—

HR DWN RGT HST PCG DSP PC98

—

— — — — 1

1 —

—

Note) PLLP0, HP0, VP0, HDNP0, SHP0, HCKP0, HSTP0, CLPP0: LSB

– 14 –

CXD2442Q

Each control data is described in detail below. (A) to (I)

(A) PLLP10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0

These bits set the frequency division ratio (master clock) of the internal 1/N frequency divider for the PLL. The

data is 11 bits and the frequency division ratio can be set up to 2045. The actual frequency division ratio

should be set as follows.

Number of dots for the horizontal period – 2 = Actual number of dots set

Examples of settings for major modes are shown below.

Examples using the LCX016

1) Macintosh17 (832 × 624)

PLLP setting value = 1152 (horizontal period) – 2 → 1150 (HLLLHHHHHHL: LSB)

PLLP

10

H

9

L

8

L

7

L

6

5

4

3

2

1

0

L

Setting data

H

2) SVGA (800 × 600)

PLLP setting value = 1000 (horizontal period) – 2 → 998 (LHHHHHLLHHL: LSB)

PLLP

10

L

9

8

7

6

5

4

L

3

L

2

1

0

L

Setting data

H

3) VGA (640 × 480)

PLLP setting value = 896 (horizontal period) – 2 → 894 (LHHLHHHHHHL: LSB)

PLLP

10

L

9

8

7

L

6

5

4

3

2

1

0

L

Setting data

H

4) PC-98 (640 × 400)

PLLP setting value = 848 (horizontal period) – 2 → 846 (LHHLHLLHHHL: LSB)

PLLP

10

L

9

8

7

L

6

5

L

4

L

3

2

1

0

L

Setting data

H

5) NTSC WIDE (832 × 480)

PLLP setting value = 1014 (horizontal period) – 2 → 1012 (LHHHHHHLHLL: LSB)

PLLP

10

L

9

8

7

6

5

4

3

L

2

1

L

0

L

Setting data

H

6) NTSC (640 × 480)

PLLP setting value = 1560 (horizontal period) – 2 → 1558 (HHLLLLHLHHL: LSB)

PLLP

10

H

9

8

L

7

L

6

L

5

L

4

3

L

2

1

0

L

Setting data

H

7) PAL (762 × 572)

PLLP setting value = 1880 (horizontal period) – 2 → 1878 (HHHLHLHLHHL: LSB)

PLLP

10

H

9

8

7

L

6

5

L

4

3

L

2

1

0

L

Setting data

H

– 15 –

CXD2442Q

Examples using the LCX012BL

1) VGA (640 × 480)

PLLP setting value = 896 (horizontal period) – 2 → 894 (LHHLHHHHHHL: LSB)

PLLP

10

L

9

8

7

L

6

5

4

3

2

1

0

L

Setting data

H

2) PC-98 (640 × 400)

PLLP setting value = 848 (horizontal period) – 2 → 846 (LHHLHLLHHHL: LSB)

PLLP

10

L

9

8

7

L

6

5

L

4

L

3

2

1

0

Setting data

H

L

3) NTSC, PAL (640 × 480)

PLLP setting value = 1560 (horizontal period) – 2 → 1558 (HHLLLLHLHHL: LSB)

PLLP

10

H

9

8

L

7

L

6

L

5

L

4

3

L

2

1

0

L

Setting data

H

(B) HP7, 6, 5, 4, 3, 2, 1, 0

These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment

of up to 256 dots with 8 bits is possible using the front edge of HSYNC as the reference.

Thp

Image display period

HSYNC

Thp: Timing from the edge of HSYNC to the start of image display

Minimum and maximum Thp setting values for each mode

LCX016

HP

7 6 5 4 3 2 1 0 832 × 624 800 × 600 762 × 572 640 × 480 640 × 400 832 × 480

Min. H H H H H H H H 185 dots 153 dots

Max. L L L L L L L L 440 dots 408 dots

105 dots

360 dots

LCX012BL

HP

7 6 5 4 3 2 1 0 644 × 484

Min. H H H H H H H H 110 dots

Max. L L L L L L L L 365 dots

– 16 –

CXD2442Q

(C) VP7, 6, 5, 4, 3, 2, 1, 0

These bits set the vertical display start position. The minimum adjustment width is 1H, and adjustment of

up to 256H with 8 bits is possible using the following references.

Non-interlace signal input → Front edge of VSYNC

Interlace signal input → First 1H of VSYNC

(Interlace signal input indicates NTSC or PAL double-speed display (using the built-in double-speed

controller). In this case, the image is raised or lowered by two lines on the panel side with respect to a 1H

adjustment.)

(1) Non-Interlace Mode

Tvp

Image display period

VSYNC

HSYNC

Tvp: Timing from the edge of VSYNC to the start of image display

Minimum and maximum Tvp setting values

LCX016/LCX012BL

VP

7 6 5 4 3 2 1 0 Non-Interlace Mode

Min.

L L L L L L L L

8H

Max. H H H H H H H H

263H

(2) Interlace Mode

(a) NTSC

1H

Tvp

Image display period

VSYNC

HSYNC

(ODD FIELD)

HSYNC

(EVEN FIELD)

Tvp: Timing from the first 1H of the VSYNC edge to the start of image display

Minimum and maximum Tvp setting values

LCX016/LCX012BL

VP

7 6 5 4 3 2 1 0

L L L L L L L L

Interlace Mode

4.5H

Min.

Max. H H H H H H H H

259.5H

– 17 –

CXD2442Q

(b) PAL

1H

Tvp

Image display period

VSYNC

HSYNC

(ODD FIELD)

HSYNC

(EVEN FIELD)

Tvp: Timing from the first 1H of the VSYNC edhe to the start of image display

Minimum and maximum Tvp setting values

LCX016/LCX012BL

VP

7 6 5 4 3 2 1 0

L L L L L L L L

Interlace Mode

4.5H

Min.

Max. H H H H H H H H

259.5H

– 18 –

CXD2442Q

(D) HDNP4, 3, 2, 1, 0

These bits set the timing for the phase comparison pulse HDN (for the external PLL IC). The phase

relationship between the dot clock and the sync signal (HSYNC) is controlled in 3ns (Typ.) units. The control

range is 32 positions with 5 bits.

Phase control for the SH pulse (SHD4, 3, 2, 1) is also performed at the same time.

3ns (1 × 3ns)

HSYNC

HDN

a

HCKn

SHD1

SHD2

SHD3

SHD4

3ns (1 × 3ns)

HDNP4, 3, 2, 1, 0

: LLLLL

0 (decimal)

: LLLLH

1 (decimal)

90ns (30 × 3ns)

93ns (31 × 3ns)

HSYNC

HDN

a

HCKn

SHD1

SHD2

SHD3

SHD4

90ns (30 × 3ns)

HDNP4, 3, 2, 1, 0

: HHHHL

: HHHHH

30 (decimal)

31 (decimal)

Note) The above timings assume SHD2, 1, 0: HHH and HPOL: H (serial data).

The value of a is constant regardless of the HDNP setting. n = 1, 2

– 19 –

CXD2442Q

(E) SHP6, 5, 4, 3, 2, 1, 0

These bits control the phase relationship between HCK1, HCK2 and SH1, 2, 3, 4, 5, 6, 7 and 8. The phase can

be controlled in 1fH units by the upper 3 bits (SHP6, 5, 4), and in 3ns (Typ.) units by the lower 4 bits (SHP3, 2,

1, 0).

3ns (1 × 3ns)

45ns (15 × 3ns)

HCKn

SH1

SH2

SH3

SH4

SH5

SH6

SH7

SH8

SHP6, 5, 4, 3, 2, 1, 0

: LLLLLLL

0 (decimal)

: LLLLLLH

1 (decimal)

: LLLHHHH

15 (decimal)

1fH (1 × 1fH)

5fH (5 × 1fH)

HCKn

SH1

SH2

SH3

SH4

SH5

SH6

SH7

SH8

SHP6, 5, 4, 3, 2, 1, 0

: LLLLLLL

0 (decimal)

: LLHLLLL

1 (decimal)

: HLHLLLL

5 (decimal)

: HHXXXXX

> 5 (decimal)

Note) The above timings assume SH2, 1, 0: HLH (serial data). n = 1, 2

– 20 –

CXD2442Q

(F) HCKP3, 2, 1, 0

These bits control the phase relationship between the RGB signal and HCK (interlocked with HST) inside the

panel, and compensate the HCK delay for the wiring load and scanner, etc. The phase can be controlled to 15

positions (1fH increments) with 4 bits.

HST

HCK1

VCKn

A

A + (1fH × N)

: LLLL

0 (decimal)

: LLLH

1 (decimal)

HCKP3, 2, 1, 0

HST

HCK1

VCKn

A + (1fH × 14)

A: Timing chart timing (design specification value)

: HHHX > 13 (decimal)

HCKP3, 2, 1 ,0

Note) Only HCK and HST are adjusted. The above timings assume HSTP3, 2, 1, 0: LLLH (serial data).

(G) HSTP3, 2, 1, 0

These bits control the phase relationship between HCK and HST inside the panel, and compensate the delay

difference between HST and HCK for the wiring load and scanner, etc. The phase can be controlled to 12

positions (1fH increments) with 4 bits.

HST

HCK1

1fH (1×1fH)

HSTP1, 0

0 (dercimal)

1 (decimal)

: LLLL

: LLLH

HST

HCK1

11fH (11×1fH)

12fH (12×1fH)

: HLHH

11 (decimal)

: HHXX

> 11 (decimal)

HSTP1, 0

Note) The above timings assume RGT: H. The HST polarity is inversed during SVGA (LCX016) mode.

– 21 –

CXD2442Q

(H) CLPP1, 0

These bits adjust the clamp pulse position. The timing can be set to 4 positions with 2 bits, and the adjustment

width varies in accordance with each mode.

The centers of the XCLP1 and XCLP2 pulses match.

Tclp1

Wclp1

XCLP1

XCLP2

Tclp2

Wclp2

HST

Macintosh17 (LCX016)

CLPP1

CLPP0

Tclp1

46 dots

69 dots

92 dots

115 dots

Tclp2

Wclp1

69 dots

Wclp2

HP Limit (HP7, 6, 5, 4, 3, 2, 1, 0)

HHHHHHHH (255) : LSB

L

H

L

23 dots

46 dots

69 dots

92 dots

115 dots

H

HHHHLLHH (243) : LSB

HHLHHHLL (220) : LSB

H

SVGA (LCX016)

CLPP1

CLPP0

Tclp1

Tclp2

Wclp1

58 dots

Wclp2

96 dots

HP Limit (HP7, 6, 5, 4, 3, 2, 1, 0)

HHHHHHHH (255) : LSB

L

H

L

38 dots

57 dots

76 dots

95 dots

19 dots

38 dots

57 dots

76 dots

H

HHHHLHHL (246) : LSB

HHHLLLHH (227) : LSB

H

VGA/NTSC, PAL, PC-98, WIDE (LCX016), VGA, NTSC, PAL (LCX012BL)

CLPP1

CLPP0

Tclp1

Tclp2

Wclp1

38 dots

Wclp2

64 dots

HP Limit (HP7, 6, 5, 4, 3, 2, 1, 0)

HHHHHHHH (255) : LSB

L

H

L

26 dots

39 dots

52 dots

65 dots

13 dots

26 dots

39 dots

52 dots

H

HHHHHLLL (248) : LSB

HHHLHLHH (235) : LSB

H

Note) When CLPP1, 0 is set to HL or HH (serial data), the XCLP pulse may not be output due to the internal

logic depending on the HP serial data setting value. HP Limit is the upper limit for the serial data HP

when setting each mode.

– 22 –

CXD2442Q

(I) Mode settings

Mode

Description

SHD2

SHD1

SHD0

SH2

Resampling switching (High: Resampling, Low: No resampling)

0.5 bit offset switching (High: No offset, Low: Offset)

I-1

I-2

Overlap switching (High: No overlap, Low: Overlap)

0.5 bit offset switching (High: No offset, Low: Offset)

SH1

Overlap switching (High: Overlap, Low: No overlap)

SH0

Overlap width switching (High: 2-dot overlap, Low: 3-dot)

Pulse eliminate (FRP) timing switching (High: Main, Low: Sub)

Pulse eliminate mode switching (High: SVGA/6, 4 pulse eliminate, Low: PAL/6, 7 pulse eliminate)

Pulse eliminate switching (High: No pulse eliminate, Low: Pulse eliminate)

MBK2

MBK1

MBK0

MBKB

MBKA

FRP1

FRP0

VPOL

HPOL

MODE

MODE3

MODE2

MODE1

CK

I-3

I-4

Pulse eliminate interval switching

FRP polarity inversion cycle switching (High: 1F, Low: 2F)

FRP polarity inversion cycle switching (High: 1H, Low: F)

Input VSYNC polarity switching (High: Positive, Low: Negative)

Input HSYNC polarity switching (High: Positive, Low: Negative)

Mode switching (High: LCX016 mode, Low: LCX012BL mode)

I-5

I-6

Panel display area switching signal input

I-7

Input clock switching (High: CKI1, Low: CKI2)

I-8

I-9

HR

External reset switching (High: No reset, Low: Reset)

DWN

RGT

Up/down inversion discrimination signal input (High: Down, Low: Up)

Right/left inversion discrimination signal input (High: Right, Low: Left)

HST width switching (High: 12 dots wide, Low: 24 dots wide)

PCG width switching (High: Main, Low: Sub)

I-10

HST

I-11

I-12

I-13

I-14

PCG

DSP

Double-speed mode switching (High: Normal, Low: Double-speed)

PC-98 (400-line) display switching (High: No display, Low: Display)

PC98

– 23 –

CXD2442Q

(I-1) SHD2, 1, 0

These bits set the sample-and-hold pulse (SHD) timing.

Set the timing in accordance with each display system.

1fH

HCKn

SHD1

SHD2

SHD3

SHD4

SHD2, 1, 0

: LLL

: LHH

: HHL

: LLH

: HLL

: HHH

: LHL

HCKn

SHD1

SHD2

SHD3

SHD4

SHD2, 1, 0

: HLH

HCKn

SHD1

SHD2

SHD3

SHD4

SHD2, 1, 0

Note) The above timings assume HDN4, 3, 2, 1, 0: LLLLL (serial data). n = 1, 2

– 24 –

CXD2442Q

(I-2) SH2, 1, 0

These bits set the sample-and-hold pulse (SH) timing.

Set the timing in accordance with each display system.

1fH

HCKn

SH1

SH2

SH3

SH4

SH5

SH6

SH7

SH8

SH2, 1, 0

: LLL

: LLH

: LHX

HCKn

SH1

SH2

SH3

SH4

SH5

SH6

SH7

SH8

SH2, 1, 0

: HLL

: HLH

: HHX

Note) The above timings assume SHP6, 5, 4, 3, 2, 1, 0: LLLLLLL (serial data). n = 1, 2

– 25 –

CXD2442Q

(I-3) MBK2, 1, 0, B, A

These bits set the pulse eliminate-related mode timings. These timings enable SVGA (scanning line

conversion from 600 to 480 vertical lines by 6, 4 pulse eliminate) and double-speed PAL (scanning line

conversion from 575 to 480 vertical lines by 6, 7 pulse eliminate) display for the LCX012BL. However, for

SVGA display, the horizontal direction is supported by external signal processing.

(1) MBK2

This bit sets the FRP-related pulse eliminate timing.

VST

VCK

FRP

HST/PCG

ENB

MBK2: H (MAIN)

MBK2: L (SUB)

(2) MBK1

This bit sets the pulse eliminate mode. Select SVGA or double-speed PAL pulse eliminate mode.

Display start timing

VST

VCK

1

2

3

4

5

6

7

1

2

3

4

5

6 7

FRP

HST/PCG

ENB

ODD/EVEN FIELD

MBK1: L (double-speed PAL/6, 7 decimation)

MBK1: H (SVGA/6, 4 decimation)

(3) MBK0

MBK0

POSITON

H

L

No pulse eliminate

Pulse eliminate

– 26 –

CXD2442Q

(4) MBK B, A

These bits change pulse eliminate timing for each field.

These bits determine the pulse eliminate timing for the next 1-field period using the pulse eliminate timing

when the field identification pulse (FLDI) is Low as the reference. The optimal pulse eliminate position can

be set by setting a pulse eliminate interval of 0 to 3H. The charts below show the pulse eliminate timing for

SVGA mode, but the timing is the same for double-speed PAL pulse eliminate.

Display start timing

VST

1

2

3

4 5 6 7 8

VCK

FRP

Reference timing

HST/PCG

ENB

FLDI

L

Display start timing

VST

VCK

1

2

3

4

5

6

7

8

1

2

3

4

5 6 7 8

FRP

HST/PCG

ENB

FLDI

H

MBK B, A: LL

MBK B, A: LH

Display start timing

VST

VCK

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7 8

FRP

HST/PCG

ENB

FLDI

H

MBK B, A: HL

MBK B, A: HH

Note) MBK2: H, MBK1: H, MBK0: L

– 27 –

CXD2442Q

(I-4) FRP1, 0

These bits are the data for switching the LCD AC signal cycle. FRP1, 0 should normally be set to HH.

1H

FRP1, 0: HH

(1H/1F inversion)

FRP1, 0: LH

(1H/2F inversion)

FRP1, 0: HL

(1F inversion)

FRP1, 0: LL

(2F inversion)

1F

(I-5) VPOL, HPOL

These bits are the data for switching the input SYNC polarity. Sync separation processing is performed with

the SYNC polarity fixed to positive by the internal logic. Therefore, the polarity must be switched when the

input is positive or negative.

Accordingly, when the input SYNC is positive or negative, the VPOL and HPOL data should be set High or

Low, respectively.

(I-6) MODE

This bit switches the HCK, CLR, HST and PCG timing according to the mode. Operation shifts to LCX016

mode when MODE is High, and LCX012BL mode when MODE is Low. Be sure to set this data when using the

CXD2442Q in these modes.

(I-7) MODE3, 2, 1

These bits switch the panel display area. However, since the panel display area can only be switched for the

LCX016, VGA/NTSC mode should be set when using the LCX012BL.

When using the LCX016

MODE

1

L

H

2

L

3

L

Macintosh17 (832 × 624)

SVGA (800 × 600)

PAL (762 × 572)

L

H

L

H

L

VGA/NTSC (640 × 480)

PC-98 (640 × 400)

WIDE (832 × 480)

H

L

H

When using the LCX012BL

MODE

1

L

2

3

H

VGA/NTSC (640 × 480)

Also supports PAL display.

– 28 –

CXD2442Q

(I-8) CK

This bit switches the input clock. Operation shifts to CKI1 input when CK is High, and CKI2 input when CK is

Low.

CKI1 input supports only the double-speed NTSC and PAL modes which use the built-in double-speed

controller. Therefore, CKI2 input is used for other modes.

(I-9) HR

This bit controls the input HSYNC-based PLL counter reset operation. (Reset operation is allowed when HR is

Low.)

Resetting the internal PLL counter at the front edge of the input HSYNC generates an output pulse

synchronized to SYNC.

This function should be used with systems which do not use a PLL.

Input HSYNC

Reset the internal PLL counter at this timing.

(I-10) DWN, RGT

These bits set the up/down and right/left inversion discrimination data. These settings allow display to be

performed in accordance with each display system. The sample-and-hold pulse timing supports this right/left

inversion function, and SH1, 2, 3 are switched with SH4, 5, 6 and SHD1 with SHD3 by switching between right

scan and left scan operation, respectively.

See the Timing Charts for details.

(I-11) HST

This bit adjusts the HST width.

6fH

12fH

24fH

HST

HCK1

HST: H

HST: L

Note) HSTP3, 2, 1, 0: LLLH

– 29 –

CXD2442Q

(I-12) PCG

This bit adjusts the PCG width. The PRG and FRP timings are also interlocked at this time.

VCK

R1

PRG

C1

PCG

FRP

Note) The VCK transition timing is constant regardless of PCG.

PCG = H

PCG = L

MODE

R1

C1

R1

C1

Macintosh17

SVGA

97 dots

82 dots

68 dots

58 dots

86 dots

72 dots

57 dots

48 dots

PAL

VGA/NTSC

PC-98

54 dots

38 dots

48 dots

32 dots

WIDE

– 30 –

CXD2442Q

(I-13) DSP

This bit performs the double-speed NTSC and PAL display mode switching settings. Operation shifts to

double-speed display mode when DSP is Low. However, DSP should be set High for other modes.

This function is only supported when the CXD2442Q's built-in double-speed controller is used. This controller

is designed to use the µPD485505 (NEC/high-speed line buffer) as the system line memory IC, and generates

the double-speed processing pulses RSTW (reset write), WCK (write clock), RSTR (reset read) and RCK

(read clock).

Operation is as follows. Write operation is started at the RSTW timing, and this memory information is read

twice at double speed at the RSTR timing which is delayed by 1/2H and 1H from the RSTW timing. Labeling

the master clock frequency (MCK) as f, the write and read clock frequencies at this time are expressed as f/2

and f, respectively.

See the specifications for a detailed description of µPD485505 operation.

ADC

DAC

LINE Mem.

µPD485505

R, G, B IN

RSTW

WCK

RSTR

RCK

HSYNC

VSYNC

CSYNC

CXD2442Q

MCK: f

Double-speed display system diagram

HSYNC

RSTW

WCK

f/2

RSTR

RCK

f

HSYNC

RSTW

RSTR

Double-speed display timing

Note) See the Timing Charts for details.

– 31 –

CXD2442Q

(I-14) PC-98

This bit switches the PC-98 (400-vertical line) display mode. Operation shifts to PC-98 mode when PC-98 is

Low. However, since this function supports the LCX012BL, PC-98 is normally (modes other than LCX012BL/

PC-98 mode) set High.

This function is used to display PC-98 (640 × 400) images in the display area of the LCX012BL (644 × 484).

The upper and lower 42 lines outside of the display area are black display during this mode.

The vertical high-speed scanning and precharge black writing methods have been introduced as methods for

writing these black areas. VCK is shifted to double-speed operation to realize vertical double-speed transfer

and enable black display within the limited V blanking. Also, the black level during this period is determined by

the PSIG (LCX012BL) level and written at the PCG (LCX012BL pin) timing.

At this time, HST is masked, limiting the video signal input.

42 (A)

Effective display area

484

400 (B)

(400 lines)

42 (C)

644

Unit: dot

LCX012BL panel

2-line inversion (FRP)

Effective display area (B)

VST

VCK

FRP

HST

PCG

(A)

(C)

: Double-speed scanning black display areas

PC-98/400-line display timing

Note) FRP is inversed (panel display) every two lines during double-speed scanning.

See the Timing Charts for details.

– 32 –

CXD2442Q

– 33 –

CXD2442Q

– 34 –

CXD2442Q

– 35 –

CXD2442Q

– 36 –

CXD2442Q

– 37 –

CXD2442Q

– 38 –

CXD2442Q

– 39 –

CXD2442Q

– 40 –

CXD2442Q

– 41 –

CXD2442Q

– 42 –

CXD2442Q

– 43 –

CXD2442Q

– 44 –

CXD2442Q

– 45 –

CXD2442Q

– 46 –

CXD2442Q

– 47 –

CXD2442Q

– 48 –

CXD2442Q

– 49 –

CXD2442Q

– 50 –

CXD2442Q

– 51 –

CXD2442Q

– 52 –

CXD2442Q

– 53 –

CXD2442Q

– 54 –

CXD2442Q

– 55 –

CXD2442Q

– 56 –

CXD2442Q

– 57 –

CXD2442Q

– 58 –

CXD2442Q

– 59 –

CXD2442Q

– 60 –

CXD2442Q

– 61 –

CXD2442Q

– 62 –

CXD2442Q

– 63 –

CXD2442Q

– 64 –

CXD2442Q

– 65 –

CXD2442Q

– 66 –

CXD2442Q

– 67 –

CXD2442Q

– 68 –

CXD2442Q

Application Circuit

65

62

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

61

64 63

66 TST8

SH2 40

SH1 39

V^SS38

67 DWN

68 RSTR

69 RCK

70 RSTW

71 WCK

72 V^SS

SHD4 37

SHD3 36

SHD2 35

SHD1 34

V^DD33

µPD485505

(NEC)

73 VDD

74 XCLR

75 PRE

76 TST9

77 TST10

78 FLDI

79 FLDO

80 HD

V^SS32

XFRP 31

FRP 30

PRG 29

XCLP2 28

XCLP1 27

TST6 26

1

2

3

4

5

6

7

8

9

10 11 12

13

14 15 16 17

18 19

20 21 22 23 24 25

Sync signal input

+5V

0.1µ

47µ

16V

Serial I/F

+5V

1M

50k

100p

47µ

16V

PLL IC

0.01µ

IN

CLK

5.1k

0.1µ

33k

FB IN

1M

1k

33k

+5V

+12V

1000p

10k

L

Enable

Disable

OFF

ON

10k

1µ

10k

50k

3.3µ

16V

10µ

35V

0.01µ 0.01µ

PRE SET

CKI1 INPUT

0.1µ

C

33k

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 69 –

CXD2442Q

Package Outline

Unit: mm

80PIN QFP (PLASTIC)

23.9 ± 0.4

+ 0.1

0.15 – 0.05

+ 0.4

20.0 – 0.1

0.15

64

41

65

40

A

+ 0.2

0.1 – 0.05

80

25

1

24

+ 0.15

+ 0.35

2.75 – 0.15

0.8

0.35 – 0.1

0.12

M

0° to 10°

DETAIL A

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY RESIN

SOLDER PLATING

SONY CODE

EIAJ CODE

QFP-80P-L01

QFP080-P-1420-A

COPPER / 42 ALLOY

1.6g

JEDEC CODE

PACKAGE WEIGHT

– 70 –


型号：	CXD2442Q
厂家：	SONY CORPORATION
描述：	Timing Generator for LCD Panels 时序发生器，用于LCD面板 CD
文件：	总70页 (文件大小：9529K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXD2442Q [SONY]

相关型号：

CXD2443Q

CXD2449Q

CXD2450R

CXD2452R

CXD2453Q

CXD2457R

CXD2458

CXD2458AR

CXD2460R

CXD2463

CXD2463R

CXD2464R