CXL1503M [SONY]
CMOS-CCD Signal Processor; CMOS ， CCD信号处理器
| 型号： | CXL1503M |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS-CCD Signal Processor |
| 文件： | 总9页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXL1503M/1505M
CMOS-CCD Signal Processor
Description
24 pin SOP (Plastic)
CXL1503M/1505M are CMOS-CCD signal processors
developed for CCD camera complementary color filter
array processing system.
CXL1503M 1H × 4 301.5 bit CCD delay line
CXL1505M 1H × 4 453.5 bit CCD delay line
Features
• Single power supply 5V
• Low power consumption
CXL1503M 100mW (Typ.)
CXL1505M 150mW (Typ.)
• Built-in peripheral circuits
• Built-in CDS (Correlated Double Sampling) circuit
Function
• Clock driver
• Autobias circuit (center and black)
• Pedestal clamp circuit
• CDS circuit
Structure
CMOS-CCD
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
• Operating temperature
• Storage temperature
Topr –10 to +60 °C
Tstg –55 to +150 °C
• Allowable power dissipation PD
500
mW
Recommended Operating Conditions (Ta = 25°C)
Supply voltage 5 ± 5%
VDD
V
Recommended Clock Conditions (Ta = 25°C)
Item
Clock voltage Low
Clock voltage High
Symbol
VL
Min.
0
Typ.
Max.
1.0
Unit
V
Remarks
VH
VDD – 1.0
VDD
V
NTSC: 910fH/3
CCIR: 908fH/3
fCL
fCL
4.77
7.16
MHz
MHz
CXL1503M
CXL1505M
Clock frequency
NTSC: 455fH
CCIR: 454fH
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E89174A03-PS
CXL1503M/1505M
Block Diagram
Pin Configuration (Top View)
19
18
4
8
1
16
17
20
A. B
1
2
24
23
22
21
20
19
18
17
16
15
14
13
VSS
IN C
ABBL
VDD
IN B
21
ABCN
CENTER
TIMING GENERATOR
DCAB
IN A
A. B
BLACK
3
ABBL
DCAB
3
4
23
ABCN
VDD
P. D
P. D
5
IS
5V
PG GEN.
PG GEN.
PG GEN.
6
IN D
CLP
XDL1
XDL2
VSS
CDS-OUTPUT
CIRCUIT
CLP
22
24
2
IN A
IN B
IN C
IN D
DL A
15 OUT A
7
8
VDD
CDS-OUTPUT
CIRCUIT
CLP
13
OUT B
DL B
DL C
DL D
9
OUT D
VGG
VSS
10
11
12
OUT A
CDS
OUT B
CDS-OUTPUT
CIRCUIT
CLP
CLP
11 OUT C
OUT C
N.C.
PG GEN.
CDS-OUTPUT
CIRCUIT
6
9
OUT D
POTENTIAL
CONTROL
WAVE
FORM
INPUT
SOURCE
BIAS.
7
5
12
10
14
Pin Description
Symbol
1, 16, 17 VSS
No.
Description
Impedance (Ω)
I/O
GND
—
I
2
3
IN C
Signal input C channel
Autobias DC output for Y signal
5V power supply
> 100k (at no clamp)
2k to 20k
ABBL
O
—
O
I
4, 8, 20 VDD
5
IS
Input source DC output
Signal input D channel
Clamp pulse input
5k
6
IN D
> 100k (at no clamp)
> 100k
7
CLP
I
9
OUT D
VGG
Signal output D channel
Gate bias DC output
Signal output C channel
—
O
O
O
—
O
O
O
I
50 to 500
2k to 10k
50 to 500
10
11
12
13
14
15
18
19
21
22
23
24
OUT C
N.C.
OUT B
CDS
Signal output B channel
DC output for CDS
50 to 500
500 to 5k
OUT A
XDL2
XDL1
ABCN
IN A
Signal output A channel
Clock pulse input 2
50 to 500
> 100k
Clock pulse input 1
> 100k
I
Autobias DC output for C signal
Signal input A channel
DC bias input for A and B channel
Signal input B channel
– 2 –
2k to 20k
O
I
> 100k (at no clamp)
> 100k
DCAB
IN B
I
I
> 100k (at no clamp)
CXL1503M/1505M
– 3 –
CXL1503M/1505M
Notes)
1. Linearity testing
For A channel and B channel, set input bias E1 to ABCN + 0.2 [V] first, and then set it to ABCN [V] and ABCN
– 0.2 [V]. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes.
For C channel and D channel, set input bias E1 to ABBL – 0.4 [V] first, and then set it to ABBL – 0.2 [V] and
ABBL [V]. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes.
The maximum output amplitude for the respective A, B, C and D channels is taken as Sout max. and the
minimum output amplitude as Sout min. The linearity of the respective channels is defined as
Sout max – Sout min
Sout max + Sout min
Lin =
× 200 [%]
2. Calculation of insertion gain difference
As the max. insertion gain among A, B, C and D channels' is taken as Gmax and the min. as Gmin., the
insertion gain difference between channels becomes:
∆G = ABS (1 – 10(Gmax – Gmin) ) × 100 [%]
20
3. Calculation of linearity difference
Define A channel linearity as LA, and B channel linearity as LB. We obtain the difference ∆LAB as follows.
∆LAB = LA – LB [%]
Similarly we obtain the linearity difference ∆LCD of C channel and D channel as follows.
∆LCD = LC – LD [%]
4. Crosstalk calculation
We take CRTa as: A channel crosstalk value only during B channel input
CRTb as: B channel crosstalk value only during A channel input
CRTc as: C channel crosstalk value only during D channel input
CRTd as: D channel crosstalk value only during C channel input
The crosstalk value of respective channels becomes:
Crosstalk component
CRTa to d =
× 100 [%]
Each channel output value
– 4 –
CXL1503M/1505M
Clock Waveform Timing
(140)
210ns
(52.5)
87.5ns
10ns
10ns
90%
90%
50%
10%
XDL1
50%
10%
( ) is for CXL1505M.
(52.5)
17.5ns
87.5ns
10ns
10ns
90%
50%
10%
90%
50%
10%
XDL2
– 5 –
CXL1503M/1505M
Electrical Characteristics Test Circuit
No signal
a
c
b
100kHz, 100mVp-p sine wave
1MHz, 100mVp-p sine wave
5V
5V
SW1
3.3k
3.3k
a
a
a
a
V1
1µ
b
b
b
b
SW7 SW6 SW5 SW4
V4
16V
XDL1 XDL2
1µ
16V
a
b
c
d
SW3
19 18
13
17 16 15 14
24 23
22 21
20
5
×1
×1
LPF
5V
5V
3.3k
3.3k
1
4
6
7
8
9
12
2
3
10 11
(NC)
1µ
16V
1µ
16V
1µ
16V
V6
V5
V2
A1
V3
SW2
b
10k 10k 10k 10k
E1
a
VDD
5V
Application Circuit
5V
5V
3.3k
Input
B
Input
A
XDL XDL
Output A
Output B
VDD
1
2
4.7µ
16V
3.3k
0.1µ 0.1µ
16V 16V 16V
1µ
1µ
16V
100p
21
20
19
18
13
23
17
16
15
10
14
11
24
22
5V
5V
3.3k
3.3k
1
4
5
6
7
8
9
12
2
3
Output C
Output D
(NC)
1µ
16V
1µ
16V
0.1µ
16V
0.1µ
16V
1µ
16V
100p 4.7µ
16V
100p 4.7µ
16V
Input
C
Input CLP
Input
VDD
VDD
D
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 6 –
CXL1503M/1505M
Frequency response
–2
–3
–4
–5
–6
–7
10k
100k
1M
10M
Signal frequency [Hz]
Autobias center level vs. Supply voltage
Autobias black level vs. Supply voltage
3
2
3
2
1
1
4.5
5
5.5
4.5
5
5.5
VDD – Supply voltage [V]
VDD – Supply voltage [V]
Insertion gain vs. Supply voltage
Linearity vs. Supply voltage
0
10
–2.5
5
–5
0
4.5
5
5.5
4.5
5
5.5
VDD – Supply voltage [V]
VDD – Supply voltage [V]
– 7 –
CXL1503M/1505M
Frequency response vs. Supply voltage
Autobias center level vs. Ambient temperature
0
–1
–2
3
2
1
0
20
40
60
4.5
5
5.5
VDD – Supply voltage [V]
Ta – Ambient temperature [°C]
Autobias black level vs. Ambient temperature
Insertion gain vs. Ambient temperature
0
–2.5
–5
3
2
1
0
20
40
60
0
20
40
60
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
Linearity vs. Ambient temperature
Frequency response vs. Ambient temperature
10
0
5
0
–1
–2
0
20
40
60
0
20
40
60
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
– 8 –
CXL1503M/1505M
Package Outline
Unit: mm
24PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
15.0 – 0.1
0.15
24
13
+ 0.2
0.1 – 0.05
12
1
+ 0.1
1.27
0.45 ± 0.1
0.2 – 0.05
0.24
M
PACKAGE STRUCTURE
MOLDING COMPOUND
EPOXY RESIN
SOLDER PLATING
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
SOP-24P-L01
SOP024-P-0300
42/COPPER ALLOY
0.3g
JEDEC CODE
– 9 –
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