CXL5507M [SONY]
CMOS-CCD 1H Delay Line for NTSC; 对于NTSC CMOS , CCD 1H延时线型号: | CXL5507M |
厂家: | SONY CORPORATION |
描述: | CMOS-CCD 1H Delay Line for NTSC |
文件: | 总9页 (文件大小:107K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CXL5507M/P
CMOS-CCD 1H Delay Line for NTSC
Description
CXL5507M
8 pin SOP (Plastic)
CXL5507P
8 pin DIP (Plastic)
The CXL5507M/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
Features
• Single 5V power supply
• Low power consumption 50mW (Typ.)
• Built-in peripheral circuits
Functions
• 453-bit CCD register
• Clock driver
• Auto-bias circuit
• Input clamp circuit
• Sample-and-hold circuit
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
°C
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
PD
–10 to +60
–55 to +150 °C
Structure
CMOS-CCD
CXL5507M
CXL5507P
350
480
mW
mW
Recommended Operating Condition (Ta = 25°C)
Supply voltage VDD 5 ± 5%
V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
7.159090 MHz
• Input clock waveform Sine wave
• Clock frequency
fCLK
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 527mVp-p (Max.)
Blook Diagram and Pin Configuration (Top View)
(at internal clamp condition)
8
7
6
5
Auto-bias circuit
Bias circuit
Timing circuit
Clock driver
Bias circuit (A)
Bias circuit (B)
CCD
(453bit)
Output circuit
(S/H 1bit)
Clamp circuit
2
3
4
1
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E90908A7X-PS
CXL5507M/P
Pin Description
Pin No. Symbol
Description
Signal input
Impedance
I/O
I
> 10kΩ at no clamp
1
2
3
4
5
6
7
8
IN
VGB
OUT
VSS
CLK
VGA
VDD
AB
I
Gate control B
Signal output
GND
40 to 500Ω
> 100kΩ
O
—
I
Clock input
O
—
O
Gate control A
Power supply (5V)
Auto-bias DC output
600 to 200kΩ
Description of I/O Signals
Input signals are low level clamped and output signals are
inverted in relation to the input signals. Also, the clamp
condition of input signals are controlled by VGB (Pin 2)
conditions.
Input waveform
Output waveform
0V ........ Internal clamp condition
5V ........ Non internal clamp condition
Clamp
level
Center biased to approx. 2.1V by means of
the IC internal resistance (approx. 10kΩ).
In this mode, the input signal is limited to
APL 50% and the maximum input signal
amplitude is 200mVp-p.
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 7.159090MHz, VCLK = 500mVp-p, sine wave)
See "Electrical Characteristics Test Circuit"
Bias
condition
V1 (V)
SW condition
2
Item
Symbol
Test condition
Min. Typ. Max. Unit Note
1
a
3
b
4
a
5
10
0
15
2
mA
dB
1
2
—
5
Supply current
—
a
a
IDD
Low frequency
gain
200kHz,
500mVp-p, sine wave
b
b
a
–2
b
a
a
a
b
b
GL
a
Frequency
response
200kHz ←→ 2MHz,
150mVp-p, sine wave
b
c
2.1
2.1
–1
—
0
dB
3
–2
—
a
b
fg
S/H pulse
coupling
350 mVp-p
4
5
No signal input
No signal input
CP
—
56
40
20
60
—
43
22
64
dB
%
c
a
a
a
54
37
18
56
S/N ratio
b
a
a
a
a
b
b
b
b
a
a
a
SN
LIS
LIL
LIC
—
b
5-staircase wave
(For luminance
signals only)
—
6
Linearity
b
b
– 2 –
CXL5507M/P
Notes
(1) This is the IC supply current value during clock and signal input.
(2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
OUT pin output voltage [mVp-p]
GL = 20 log
[dB]
500 [mVp-p]
(3) Indicates the dissipation at 2MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 2MHz sine wave is fed to same, calculation is made
according to the following formula. Input bias is tested at 2.1V.
OUT pin otuput voltage (2MHz) [mVp-p]
fg = 20 log
[dB]
OUT pin output voltage (200kHz) [mVp-p]
(4) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested. Input bias is tested at 2.1V.
Test value
(mVp-p)
(5) Input no signal noise components are tested with the video noise meter at BPF 10kHz to 3MHz. This is
calculated from the output gain (GL), at the input of 200kHz, 500mVp-p and according to the following
formula.
Noise (mVrms)
0.5 • 10 GL/20
S/N = –20 • Iog
[dB]
(6) Respective outputs are tested at the input of the 5-staircase waves seen in the figure below (Iuminance
signals only) and calculated according to the formula below.
(However, output signals become inverted with regards to input.)
Va
Vs
Va
LIS =
× 100 [%]
100 IRE
40 IRE
Vc
Vp
Va
500mV
LIL =
LIC =
× 100 [%]
× 100 [%]
Vp
Vs
Vc
Va
– 3 –
CXL5507M/P
Clock
2fsc (7.159090MHz) sine wave
(0.5Vp-p typ.)
– 4 –
CXL5507M/P
– 5 –
CXL5507M/P
– 6 –
CXL5507M/P
Example of Representative Characteristics
Supply current vs. Supply voltage
Low frequency gain vs. Supply voltage
20
1.5
1
15
10
5
0.5
0
0
–0.5
4.75
5
5.25
4.75
5
5.25
5.25
5.25
Supply voltage [V]
Supply voltage [V]
Frequency response vs. Supply voltage
Linearity (LIS) vs. Supply voltage
0
–0.5
–1
44
40
36
32
–1.5
–2
4.75
5
5.25
4.75
5
Supply voltage [V]
Supply voltage [V]
Linearity (LIL) vs. Supply voltage
Linearity (LIC) vs. Supply voltage
30
25
20
15
10
70
66
62
58
54
50
4.75
5
5.25
4.75
5
Supply voltage [V]
Supply voltage [V]
– 7 –
CXL5507M/P
Supply current vs. Ambient temperature
Low frequency gain vs. Ambient temperature
20
15
10
5
1.5
1
0.5
0
0
–0.5
–20 –10
0
10 20 30 40 50 60 70
Ambient temperature [°C]
–20 –10
0
10 20 30 40 50 60 70
Ambient temperature [°C]
Frequency response vs. Ambient temperature
0
Linearity (LIS) vs. Ambient temperature
44
40
36
32
–0.5
–1
–1.5
–2
–20 –10
0
10 20 30 40 50 60 70
Ambient temperature [°C]
–20 –10
0
10 20 30 40 50 60 70
Ambient temperature [°C]
Linearity (LIL) vs. Ambient temperature
Linearity (LIC) vs. Ambient temperature
30
25
20
15
10
70
66
62
58
54
50
–20 –10
0
10 20 30 40 50 60 70
–20 –10
0
10 20 30 40 50 60 70
Ambient temperature [°C]
Ambient temperature [°C]
– 8 –
CXL5507M/P
Package Outline
CXL5507M
Unit: mm
8PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
6.1– 0.1
8
5
0.15
+ 0.2
0.1– 0.05
1
4
+ 0.1
0.2 – 0.05
0.45 ± 0.1
1.27
0.24
M
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
SONY CODE
EIAJ CODE
SOP-8P-L01
SOP008-P-0300
42/COPPER ALLOY
0.1g
PACKAGE MASS
JEDEC CODE
CXL5507P
8PIN DIP (PLASTIC)
+ 0.4
9.4 – 0.1
5
8
1
0° to 15°
4
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
DIP-8P-01
EIAJ CODE
DIP008-P-0300
COPPER ALLOY
0.5g
PACKAGE MASS
JEDEC CODE
– 9 –
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