CXP82900 [SONY]
CMOS 8-bit Single Chip Microcomputer; CMOS 8位单片机
| 型号： | CXP82900 |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS 8-bit Single Chip Microcomputer |
| 文件： | 总5页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP82900
Piggyback/
evaluator type
CMOS 8-bit Single Chip Microcomputer
Description
80 pin PQFP (Ceramic)
The CXP82900 is a CMOS 8-bit single chip micro-
computer of piggyback/evaluator combined type,
which is developed for evaluating the function of the
CXP82940/82948/82952/82960.
Features
• Wide-range instruction system (213 instructions)
to cover various types of data
— 16-bit operation/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation
122µs at 32kHz operation
• Applicable EPROM
LCC type 27C512 (Maximum 60K bytes are available.)
• Incorporated RAM capacity 2048 bytes (Including fluorescent display data area.)
• Peripheral functions
— A/D converter
— Serial interface
— Timer
8-bit, 8-channel, successive approximation method
(Conversion time of 20µs/16MHz)
Incorporated buffer RAM (Auto transfer for 1 to 32bytes), 1 channel
Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel
8-bit timer
8-bit timer/counter
19-bit time base timer
32kHz timer/counter
— Fluorescent display panel controller/driver
Maximum 196-segment display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
Pull-down function
Hardware key scan function (Maximum 12 × 8 key matrix compatible)
— I2C bus interface
— Remote control transmission circuit
Auto transmission for 1 to 32 bytes, restart function, carrier output function
— Remote control reception circuit
8-bit pulse measurement counter with on-chip 6-stage FIFO
16 factors, 15 vectors, multi-interruption possible
SLEEP/STOP
• Interruption
• Standby mode
• Package
80-pin ceramic QFP
Note) Mask option depends on the type of the CXP82900. Refer to the Products List for details.
Structure
Silicon gate CMOS IC
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95613-PP
CXP82900
Pin Configuration in Piggyback Mode
80 79 78 77 76 75 74 73 72
66 65
71 70 69 68 67
1
2
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5
T7
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
T8/S19
T9/S18
T10/S17
T11/S16
T12/S15
T13/S14
T14/S13
T15/S12
S11
3
4
5
PE6/RMCO
PE7/TO/ADJ
PB0
6
7
8
32
3
2
1
31 30
29
4
PB1/CS0
PB2/SCK0
PB3/SI0
9
A6
A5
A4
A3
A2
A1
A0
NC
D0
5
6
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
24
23
22
21
A9
S10
A11
NC
OE
A10
CE
D7
7
PB4/SO0
PB5/SCK1
PB6/SI1
S9
8
S8
9
PD7/S7
PD6/S6
PD5/S5
PD4/S4
PD3/S3
PD2/S2
PD1/S1
PD0/S0
VFDP
10
11
12
13
PB7/SO1
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
AVDD
D6
19
20
15 16
18
14
17
PC7/KR7
PC6/KR6
35
40
39
25 26 27 28 29 30
31
32 33
34
36 37 38
Note) NC (Pin 75) is always connected to VDD.
– 2 –
CXP82900
Pin Configuration in Evaluator Mode
80 79 78 77 76 75 74 73 72
66 65
71 70 69 68 67
1
2
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5
T7
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
T8/S19
T9/S18
T10/S17
T11/S16
T12/S15
T13/S14
T14/S13
T15/S12
S11
3
4
5
PE6/RMCO
PE7/TO/ADJ
PB0
6
7
8
32
3
2
1
31 30
29
4
PB1/CS0
PB2/SCK0
PB3/SI0
9
A6/D6
A5/D5
A4/D4
A3/D3
A2/D2
A1/D1
A0/D0
NC
5
6
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
24
23
22
21
A9
S10
A11
NC
7
PB4/SO0
PB5/SCK1
PB6/SI1
S9
8
S8
HALT
A10
E/P
I/T
9
PD7/S7
PD6/S6
PD5/S5
PD4/S4
PD3/S3
PD2/S2
PD1/S1
PD0/S0
VFDP
10
11
12
13
PB7/SO1
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
AVDD
RD
MON
19
20
15 16
18
14
17
PC7/KR7
PC6/KR6
35
36 37 38
40
39
25 26 27 28 29 30
31
32 33
34
Note) NC (Pin 75) is always connected to VDD.
– 3 –
CXP82900
EPROM Read Timing
(Ta = –20 to +75°C, Vcc = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
Min.
Max.
75
Unit
ns
Address → Data
Input delay time
A0 to A15
D0 to D7
t
t
ACC
Address → Data
Hold time
A0 to A15
D0 to D7
IH
0
ns
0.8VDD
0.2VDD
Address data
A0 to A15
tACC
tIH
0.8VDD
0.2VDD
D0 to D7
Input
data
Products List
Products
Option item
Mask type
Piggyback/evaluator product
CXP82900-U01Q
80-pin ceramic QFP
EPROM 60K bytes
CXP82940 CXP82948 CXP82952 CXP82960
80-pin plastic QFP
Package
ROM capacitance
40K bytes 48K bytes 52K bytes 60K bytes
Pull-up resistance for
reset pin
Existent/Non-existent
Existent/Non-existent
Existent
Pull-down resistance for
high voltage drive pin
Existent: T0 to T7, S8 to T8/S19
Non-existent: PD0/S0 to PD7/S7
– 4 –
CXP82900
Piggyback mode/evaluator mode can be switched as shown below.
Piggyback mode
Piggyback/evaluator product
Evaluator mode
Pin 1 marking
Pin 1 index
LCC type EPROM
Pin 1 marking
Note)
CPU Probe
Note) Evaluation cap should be
connected to CPU probe.
Package Outline
Unit: mm
80PIN PQFP (CERAMIC)
PIN No. 1 INDEX
INDEX
18.7
16.3 ± 0.2
PIN No. 1 INDEX
65
80
80
65
1
64
1
64
4.5
24
24
41
41
40
25
25
40
9.48
11.66
0.6
15.58 ± 0.2
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
CERAMIC
GOLD PLATING
SONY CODE
EIAJ CODE
PQFP-80C-L01
AQFP080-C-0000-A
42 ALLOY
5.7g
JEDEC CODE
PACKAGE WEIGHT
– 5 –
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