CXP846P48Q-1 [SONY]
8-Bit Microcontroller ; 8位微控制器\n
| 型号： | CXP846P48Q-1 |
| 厂家： | 
SONY CORPORATION |
| 描述： | 8-Bit Microcontroller
|
| 文件： | 总28页 (文件大小：461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP846P48
CMOS 8-bit Single Chip Microcomputer
Description
The CXP846P48 is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer/counter, I2C bus interface, remote
control reception circuit, PWM output, and 32kHz
timer/counter besides the basic configurations of 8-bit
CPU, PROM, RAM, and I/O port.
80 pin QFP (Plastic)
The CXP846P48 also provides a sleep/stop function
that enables lower power consumption.
The CXP846P48 is the PROM-incorporated version
of the CXP846P48 with built-in mask ROM. This
provides the additional feature of being able to write
directly into the program, Thus, it is most suitable for
evaluation use during system development and for
small-quantity production.
Structure
Silicon gate CMOS IC
Features
• Wide range instruction system (213 instructions) to cover various of data.
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation (4.5 to 5.5V)
333ns at 12MHz operation (3.0 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
48K bytes
• Incorporated PROM capacity
• Incorporated RAM capacity
• Peripheral functions
2048 bytes
— A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time 20µs/16MHz)
— Serial interface
Srart-stop synchronization (UART), 1 channel
Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel
Incorporated 8-bit, 10-stage FIFO
(Auto transfer for 1 to 10 bytes), 1 channel
8-bit clock syncronization (MSB/LSB first selectable), 1 channel
8-bit timer, 8-bit timer/counter, 19-bit time base timer,
16-bit capture timer/counter, 32kHz timer/counter
— Timer
— I2C bus interface
— Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
— PWM output circuit
• Interruption
• Standby mode
12 bits, 2 channels
21 factors, 15 vectors, multi-interruption possible
SLEEP/STOP
• Package
80-pin plastic QFP
• Piggyback/evaluation chip
CXP84600 80-pin ceramic QFP
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E96308-ST
CXP846P48
P P P P P P P P O R T H P O R T I
V p p
S S V
D D V
R S T
X T A L
E X T A L
T X
T E X
I N T 4
I N T 3
I N T 2
I N T 1
I N T 0
N M I
I N T E R R U P T C O N T R O L L E R
R E F A V
S S A V
– 2 –
CXP846P48
Pin Assignment (Top View)
80 79 78 77 76 75 74 73 72
71 70 69 68 67
66 65
PF3/SDA0
PF4/PWM0
PF5/PWM1
PF6/TxD
PF7/RxD
PD0
1
2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PI4/INT4
PI3/INT3
PI2/INT2
PI1/INT1
PI0/INT0
3
4
5
6
PE5/TO/ADJ
PE4
PD1
7
PD2
8
PE3/NMI
PE2/RMC
PE1/EC1
PE0/EC0
PB7/SO1
PB6/SI1
PD3
9
PD4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PD5
PD6
PD7
PC0
PB5/SCK1
PB4/SO0
PB3/SI0
PC1
PC2
PC3
PB2/SCK0
PB1/CS0
PB0/CINT
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PC4
PC5
PC6
PC7
PH0
PH1
PH2
35
36 37 38
40
39
25 26 27 28 29 30
31
32 33
34
Note) Vpp (Pin 73) must be connected VDD.
– 3 –
CXP846P48
Pin Description
Pin code
I/O
Functions
(Port A)
8-bit I/O port. I/O can be
set in a unit of signle bits.
Incorporation of the pull- Analog inputs to A/D converter.
up resistance can be set (8 pins)
through the software in a
unit of 4 bits.
PA0/AN0
to
PA7/AN7
I/O/Analog input
(8 pins)
External capture input to 16-bit timer/counter.
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
I/O/Input
I/O/Input
I/O/I/O
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
(Port B)
I/O can be set in a unit
of single bits for lower
7 bits. Incorporation of
pull-up resistor can be
set through the software
in a unit of 4 bits.
(8 pins)
Serial data input (CH0).
I/O/Input
I/O/Output
I/O/I/O
Serial data output (CH0).
Serial clock I/O (CH1).
PB4/SO0
PB5/SCK1
PB6/SI1
Serial data input (CH1).
I/O/Input
I/O/Output
Serial data output (CH1).
PB7/SO1
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving
12mA sync current. Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
PC0 to PC7
PD0 to PD7
I/O
I/O
(8 pins)
(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-
up resistor can be set through the software in a unit of 4 bits.
(8 pins)
Input/Input
Input/Input
Input/Input
Input/Input
Output
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
PE4
External event inputs for timer/counter.
(2 pins)
(Port E)
Remote control reception circuit input.
6-bit port. Lower 4 bits
are for inputs; upper
2 bits are for outputs.
(6 pins)
Non-maskable interruption request input.
Output/Output/
Output
Rectangular wave output for 16-bit timer/counter.
Output for 32kHz oscillation frequency division.
PE5/TO/
ADJ
Transfer clock I/O for I2C bus interface.
(2pins)
PF0/SCL0
PF1/SCL1
Output/I/O
Output/I/O
(Port F)
Lower 7 bits are for
output; of which lower
4 bits are large current
(12mA) N-ch open
drain output.
The uppermost bit
(PF7) is for input.
(8pins)
Transfer data I/O for I2C bus interface.
(2pins)
PF2/SDA0
PF3/SDA1
Output/Output
Output/Output
Output/Output
Input/Input
PF4/PWM0
PF5/PWM1
PF6/TxD
PWM outputs.
(2pins)
UART transmission data output.
UART reception data input.
PF7/RxD
– 4 –
CXP846P48
Pin code
I/O
Functions
(Port G)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-
up resistor can be set through the software in a unit of 4 bits.
(8 pins)
PG0 to PG7
I/O
I/O
(Port H)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-
up resistor can be set through the software in a unit of 4 bits.
(8 pins)
PH0 to PH7
(Port I)
PI0/INT0
to
PI4/INT4
External interruption request inputs.
(5 pins)
8-bit I/O port. I/O can be
set in a unit of single
bits. Incorporation of
pull-up resistor can be
set through the software
in a unit of 4 bits.
I/O/Input
Serial clock I/O. (CH2)
I/O/I/O
PI5/SCK2
PI6/SI2
Serial data input. (CH2)
Serial data output. (CH2)
I/O/Input
I/O/Output
Input
(8 pins)
PI7/SO2
EXTAL
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
Output
Input
XTAL
TEX
TX
Crystal connectors for 32kHz timer/counter clock oscillation. For usage
as event counter, input to TEX, and open TX.
Output
Input
Low-level active, system reset.
RST
Positive power supply pin for built-in PROM writing.
Connect to VDD for normal operation.
Vpp
AVREF
AVss
VDD
Input
Reference voltage input for A/D converter.
A/D converter GND.
Positive power supply.
GND.
Vss
– 5 –
CXP846P48
I/O Circuit Format for Pins
Pin
When reset
Circuit format
Port A
Pull-up resistance
“0” when reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
“0” when reset
Input protection
circuit
IP
Hi-Z
Data bus
RD (Port A)
Port A function
selection
Input multiplexer
“0” when reset
A/D converter
8 pins
Pull-up transistors
approx. 100kΩ
Port B
Port I
Pull-up resistance
“0” when reset
Port B, I data
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
PI6/SI2
Port B, I direction
“0” when reset
Hi-Z
IP
Schmitt input
Data bus
RD (Port B, I)
CINT
CS0
SI0
Pull-up transistors
SI1
approx. 100kΩ
5 pins
Port B
Port I
Pull-up resistance
“0” when reset
SCK OUT
Serial clock output enable
Port B, I function selection
“0” when reset
PB2/SCK0
PB5/SCK1
PI5/SCK2
IP
Port B, I data
Hi-Z
Port B, I direction
“0” when reset
Schmitt input
Data bus
RD (Port B, I)
SCK in
Pull-up transistors
approx. 100kΩ
3 pins
– 6 –
CXP846P48
Pin
When reset
Circuit format
Port B
Port I
Pull-up resistance
“0” when reset
SO
Serial data output enable
Port B, I function selection
“0” when reset
PB4/SO0
PB7/SO1
PI7/SO2
IP
Port B, I data
Hi-Z
Port B, I direction
“0” when reset
Data bus
RD (Port B, I)
Pull-up transistors
approx. 100kΩ
3 pins
Port C
2
Pull-up resistance
“0” when reset
Port C data
PC0 to PC7
Hi-Z
1
Port C direction
“0” when reset
IP
Data bus
RD (Port C)
1
Large current 12mA
2
8 pins
Pull-up transistors
approx. 100kΩ
Port E
Port F
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
PF7/RxD
Schmitt input
Hi-Z
IP
EC0, EC1, RMC, NMI, RxD
Data bus
5 pins
RD (Port E, F)
Port E
PE4
Port E data
High level
“1” when reset
Data bus
1 pin
RD (Port E)
– 7 –
CXP846P48
Pin
When reset
Circuit format
Port E
Internal reset signal
00
Port E data
“1” when reset
01
10
11
TO
MPX
1
ADJ16K
2
High level
with approx.
150kΩ
1
PE5/TO/ADJ
ADJ2K
resistor
when reset
(
)
Port E function selection (upper)
Port E function selection (lower)
“00” when reset
1 ADJ signals are frequency dividing output for
32kHz oscillation frequency adjustment.
ADJ2K provides usage as buzzer output.
TO output enable
2 Pull-up transistor approx. 150kΩ
1 pin
Port D
Port G
Port H
Pull-up resistance
“0” when reset
Port D, G, H data
PD0 to PD7
PG0 to PG7
PH0 to PH7
Hi-Z
Port D, G, H direction
“0” when reset
IP
Data bus
RD (Port D, G, H)
24 pins
Pull-up transistors
approx. 100kΩ
Port I
Pull-up resistance
“0” when reset
Port I data
PI0/INT0
to
PI4/INT4
Port I direction
“0” when reset
IP
Hi-Z
Data bus
RD (Port I)
INT0
INT1
INT2
INT3
INT4
Pull-up transistors
approx. 100kΩ
5 pins
– 8 –
CXP846P48
Pin
When reset
Circuit format
Port F
SCL, SDA
I2C output enable
(“0” when reset)
PF0/SCL0
PF1/SCL1
PF2/SDA0
PF3/SDA1
Port F data
IP
Hi-Z
“1” when reset
Schmitt input
SCL, SDA
(To I2C circuit)
BUS SW
To internal I2C pin
(SCL1 for SCL0)
Large current 12mA
4 pins
Port F
PWM
Port F output selection
“0” when reset
PF4/PWM0
PF5/PWM1
High level
Port F data
“1” when reset
Data bus
RD (Port F)
2 pins
Port F
UART transmission circuit
Port F output selection
“0” when reset
PF6/TxD
1 pin
High level
Port F data
“1” when reset
Data bus
RD (Port F)
Port H
Port H data
“0” when reset
Port H direction
PH0 to PH7
IP
Data bus
Hi-Z
RD (Port H)
Edge detection
Standby release
Data bus
8 pins
RD (Port H direction)
– 9 –
CXP846P48
Pin
When reset
Circuit format
• Diagram shows circuit
composition during oscillation.
• Feedback resistor is removed
during stop, and XTAL
EXTAL
XTAL
EXTAL
XTAL
IP
IP
Oscillation
becomes High level.
2 pins
• Diagram shows circuit
composition during oscillation.
TEX
TX
TEX
TX
IP
IP
Oscillation
• When the operation of the oscillation
circuit is stopped by the software,
the feedback resistor is removed,
and TEX and TX become Low level
and High level respectively.
2 pins
Pull-up resistor
RST
1 pin
Mask option
IP
Low level
OP
Schmitt input
– 10 –
CXP846P48
Absolute Maximum Ratings
(Vss = 0V reference)
Item
Symbol
VDD
Rating
–0.3 to +7.0
–0.3 to +0.3
–0.3 to +7.0
–0.3 to +7.0
–5
Unit
V
Remarks
Supply voltage
V
AVSS
VIN
1
1
V
Input voltagte
V
Output voltage
VOUT
IOH
mA Output (value per pin)
mA Total for all output pins
High level output current
–50
High level total output current ∑IOH
All pins excluding large current
outputs (value per pin)
15
mA
IOL
Low level output current
2
20
100
mA
Large current outputs (value per pin)
IOLC
mA Total for all output pins
Low level total output current ∑IOL
–10 to +75
–55 to +150
600
°C
°C
Operating temperature
Storage temperature
Topr
Tstg
PD
mW
Allowable power dissipation
1
VIN and VOUT must not exceed VDD + 0.3V.
2
The large current output is for each pin of Port C (PC), Port F0 (PF0) to Port 3 (PF3).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 11 –
CXP846P48
Recommended Operating Conditions
(Vss = 0V reference)
Item
Symbol
Min.
4.5
Max.
5.5
Unit
V
Remarks
Guaranteed operation
range for 1/2 and 1/4
frequency dividing clock.
fc = 16MHz or less
fc = 12MHz or less
3.0
5.5
V
Guaranteed operation range for 1/16
frequency dividing clock or SLEEP mode
V
V
V
2.7
2.7
2.5
5.5
5.5
5.5
VDD
Supply voltage
Guaranteed operation range by TEX clock
Guaranteed data hold operation range
during STOP
1,
1,
5
0.7VDD
0.8VDD
0.8VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
V
V
V
°C
VIH
6
HIgh level input
voltage
2
VIHS
VIHEX
Hysteresis input
3,
5
4,
4,
5
6
VDD – 0.4 VDD + 0.3
VDD – 0.2 VDD + 0.2
EXTAL pin
EXTAL pin
TEX pin
TEX pin
3,
6
1,
5
0
0
0.3VDD
0.2VDD
0.2VDD
0.4
VIL
1,
6
Low level input
voltage
2
VILS
VILEX
Topr
0
Hysteresis input
3,
5
4,
4,
5
6
–0.3
–0.3
–10
EXTAL pin
EXTAL pin
TEX pin
TEX pin
3,
6
0.2
Operating temperature
+75
1
Normal input port (each pin of PA, PB4, PB7, PC, PF0 to PF4, PG, PH and PI7)
2
Each pin of RST, CINT, CS0, SCK0, SCK1, SCK2, SI0, SI1, SI2, EC0, EC1, RMC, NMI, RxD, INT0, INT1,
INT2, INT3 and INT4
3
4
5
6
It is specified only when the external clock is input.
It is specified only when the external event count clock is input.
This case applies to the range of 4.5 to 5.5V supply voltage (VDD).
This case applies to the range of 3.0 to 5.5V supply voltage (VDD).
– 12 –
CXP846P48
Electrical Characteristics
DC Characteristics
Supply voltage (VDD) 4.5 to 5.5V
(Ta = –10 to +75°C, Vss = 0V reference)
Item
Symbol
Pins
Conditions
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
Min.
4.0
Typ.
Max.
Unit
V
High level
output voltage
PA to PD,
PE4, PE5,
PF4, PF5,
PF6,
VOH
3.5
V
0.4
0.6
1.5
0.4
0.6
40
V
PG to PI
V
Low level
output voltage
PC, PF0 to PF3 VDD = 4.5V, IOL = 12.0mA
V
VOL
PF0 to PF3
(SCL0, SCL1,
SDA0, SDA1)
VDD = 4.5V, IOL = 3.0mA
VDD = 4.5V, IOL = 4.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V
VDD = 5.5V, VIL = 0.4V
V
V
0.5
–0.5
0.1
µA
µA
µA
µA
µA
µA
µA
IIHE
IILE
IIHT
IILT
IILR
EXTAL
TEX
–40
10
–0.1
–1.5
–10
–400
–45
Input current
1
RST
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
2
PA to PD ,
PG to PI
IIL
IIZ
2
–2.78
2
PA to PD ,
VDD = 5.5V
VI = 0, 5.5V
I/O lealage
current
2
±10
10
µA
µA
PG to PI ,
1
RST
Open drain
PF0 to PF3
(SCL0, SCL1,
SDA0, SDA1)
VDD = 5.5V
VOH = 5.5V
output leakage
current (N-ch
Tr off state)
ILOH
RBS
I2C bus switch
connection
impedance
(Output Tr off
state)
VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V
SCL0: SCL1
SDA0: SDA1
120
Ω
– 13 –
CXP846P48
Item
Symbol
Pins
Conditions
Min.
Typ.
31
Max.
Unit
mA
1/2 frequency dividing clock operation
IDD1
50
1.2
10
V
DD = 5.5V, 16MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation;
and termination of 16MHz
oscillation (C1 = C2 = 47pF)
0.6
2.5
8
mA
mA
IDD2
SLEEP mode
Supply
VDD
3
IDDS1
current
V
DD = 5.5V, 16MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation;
and termination of 16MHz
oscillation (C1 = C2 = 47pF)
IDDS2
IDDS3
30
30
µA
µA
STOP mode
VDD = 5.5V, termination of 16MHz
and 32kHz crystal oscillation
PA to PC,
PE0 to PE5,
PF to PI,
Clock 1MHz
0V for all pins excluding measured
pins
Input
capacity
pF
10
20
CIN
EXTAL,
TEX, RST
1
2
3
RST specifies the input current when pull-up resistance has been selected; leakage current when no
resistance has been selected.
PA to PD, and PG to PI specify the input current when pull-up resistance has been selected; leakage
current when no resistance has been selected.
When all pins are open.
– 14 –
CXP846P48
Electrical Characteristics
DC Characteristics
Supply voltage (VDD) 3.0 to 3.6V
(Ta = –10 to +75°C, Vss = 0V reference)
Item
Symbol
Pins
Conditions
VDD = 3.0V, IOH = –0.15mA
VDD = 3.0V, IOH = –0.5mA
VDD = 3.0V, IOL = 1.2mA
VDD = 3.0V, IOL = 1.6mA
Min.
2.7
Typ.
Max.
Unit
V
High level
output voltage
VOH
PA to PD,
PE4, PE5,
PF4, PF5,
PF6
2.3
V
0.3
0.5
1
V
V
Low level
output voltage
PC, PF0 to PF3 VDD = 3.0V, IOL = 5.0mA
V
VOL
PF0 to PF3
(SCL0, SCL1,
SDA0, SDA1)
VDD = 3.0V, IOL = 2.0mA
VDD = 3.0V, IOL = 2.5mA
VDD = 3.6V, VIH = 3.6V
VDD = 3.6V, VIL = 0.3V
VDD = 3.6V, VIL = 3.6V
VDD = 3.6V, VIL = 0.4V
0.3
0.5
20
V
V
0.3
–0.3
0.1
µA
µA
µA
µA
µA
µA
µA
IIHE
IILE
IIHT
IILT
IILR
EXTAL
TEX
–20
10
–0.1
–0.9
–10
–200
–20
Input current
1
RST
VDD = 3.6V, VIL = 0.3V
VDD = 3.0V, VIL = 2.7V
2
PA to PD ,
IIL
IIZ
2
PG to PI
–1.0
2
PA to PD ,
VDD = 3.6V
VI = 0, 3.6V
I/O lealage
current
2
±10
10
µA
µA
PG to PI ,
1
RST
Open drain
PF0 to PF3
(SCL0, SCL1,
SDA0, SDA1)
VDD = 3.6V
VOH = 3.6V
output leakage
current (N-ch
Tr off state)
ILOH
RBS
I2C bus switch
connection
impedance
(Output Tr off
state)
VDD = 3.0V
VSCL0 = VSCL1 = 1.5V
VSDA0 = VSDA1 = 1.5V
SCL0: SCL1
SDA0: SDA1
300
Ω
– 15 –
CXP846P48
Item
Symbol
Pins
Conditions
Min.
Typ.
11
Max.
Unit
mA
1/2 frequency dividing clock operation
IDD1
25
V
DD = 3.6V, 12MHz crystal oscillation
(C1 = C2 = 15pF)
SLEEP mode
Supply
current
VDD
mA
µA
0.5
3
2.5
20
IDDS1
IDDS3
VDD = 3.6V, 12MHz crystal oscillation
(C1 = C2 = 15pF)
STOP mode
VDD = 3.6V, termination of 16MHz
and 32kHz crystal oscillation
PA to PC,
PE0 to PE5,
PF to PI,
Clock 1MHz
0V for all pins excluding measured
pins
Input
capacity
CIN
pF
10
20
EXTAL,
TEX, RST
1
2
3
RST specifies the input current when pull-up resistance has been selected; leakage current when no
resistance has been selected.
PA to PD, and PG to PI specify the input current when pull-up resistance has been selected; leakage
current when no resistance has been selected.
When all pins are open.
– 16 –
CXP846P48
AC Characteristics
(1) Clock timing
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Conditions
Min.
1
Typ.
Max.
16
Unit
VDD = 4.5 to 5.5V
XTAL
EXTAL
fC
Fig. 1, Fig. 2
MHz
System clock frequency
1
12
VDD = 4.5 to 5.5V
28
t
XL
Fig. 1, Fig. 2
System clock input pulse
width
ns
EXTAL
EXTAL
tXH
External clock drive
37.5
t
CR
CF
Fig. 1, Fig. 2
System clock input
rise time, fall time
ns
ns
200
20
t
External clock drive
t
EH
EL
Event count input clock
pulse width
EC0
EC1
1
4tsys
Fig. 3
Fig. 3
t
t
ER
EF
Event count input clock
rise time, fall time
EC0
EC1
ms
t
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock applied
condition)
TEX
TX
fC
kHz
System clock frequency
32.768
t
TL
Event count input clock
input pulse width
µs
10
TEX
TEX
Fig. 3
Fig. 3
tTH
tTR
TF
Event count input clock
rise time, fall time
ms
20
t
1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control
clock register (CLC: 00FEH).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (Upper two bits = “11”)
1/fc
Fig. 1. Clock timing
VDD – 0.4V (VDD = 4.5 to 5.5V)
VDD – 0.3V
EXTAL
0.4V (VDD = 4.5 to 5.5V)
0.3V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
32kHz clock applied condition
Crystal oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HC04
C1
C2
Fig. 3. Event count clock timing
TEX
EC0
EC1
0.8VDD
0.2VDD
tEH
tTH
tEF
tTF
tEL
tTL
tER
tTR
– 17 –
CXP846P48
(2) Serial transfer (CH0)
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pin
Condition
Min.
Max.
Unit
ns
CS↓ → SCK
delay time
Chip select transfer mode
(SCK = output mode)
SCK0
tsys + 200
t
DCSK
CS↑ → SCK
floating delay time
Chip select transfer mode
(SCK = output mode)
SCK0
SO0
SO0
CS0
tsys + 200
tsys + 200
tsys + 200
ns
ns
ns
t
t
t
t
DCSKF
DCSO
CS↓ → SO delay time
Chip select transfer mode
Chip select transfer mode
CS↓ → SO floating
delay time
DCSOF
WHCS
CS High level width
Chip select transfer mode
Input mode
tsys + 200
2tsys + 200
16000/fc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY
SCK cycle time
SCK0
SCK0
SI0
Output mode
Input mode
tsys + 100
8000/fc – 100
–tsys + 100
200
t
KH
KL
SCK High and Low
level widths
t
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(against SCK↑)
t
t
t
SIK
2tsys + 100
100
SI input hold time
(against SCK↑)
KSI
SI0
2tsys + 200
100
SCK↓ → SO
delay time
KSO
SO0
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
– 18 –
CXP846P48
Serial transfer (CH0)
(Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Item
Symbol Pin
Condition
Min.
Max.
Unit
ns
CS↓ → SCK
delay time
Chip select transfer mode
(SCK = output mode)
t
DCSK
SCK0
tsys + 250
CS↑ → SCK
floating delay time
Chip select transfer mode
(SCK = output mode)
t
t
t
t
DCSKF
DCSO
SCK0
SO0
SO0
CS0
tsys + 200
tsys + 250
tsys + 200
ns
ns
ns
CS↓ → SO delay time
Chip select transfer mode
Chip select transfer mode
CS↓ → SO floating
delay time
DCSOF
WHCS
CS High level width
Chip select transfer mode
Input mode
tsys + 200
2tsys + 200
16000/fc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY
SCK cycle time
SCK0
SCK0
SI0
Output mode
Input mode
tsys + 100
8000/fc – 150
–tsys + 100
200
t
KH
KL
SCK High and Low
level widths
t
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(against SCK↑)
t
t
t
SIK
2tsys + 100
100
SI input hold time
(against SCK↑)
KSI
SI0
2tsys + 250
125
SCK↓ → SO
delay time
KSO
SO0
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.
– 19 –
CXP846P48
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tDCSKF
tKL
tKH
0.8VDD
0.8VDD
0.2VDD
SCK0
tSIK
tKSI
0.8VDD
0.2VDD
Input data
SI0
tDCSO
tKSO
tDCSOF
0.8VDD
Output data
SO0
0.2VDD
– 20 –
CXP846P48
Serial transfer (CH1, CH2)
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pin
SCK1
Condition
Input mode
Min.
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK cycle time
tKCY
SCK2
Output mode
Input mode
SCK1
SCK2
SCK High and Low
level widths
t
KH
KL
t
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI1
SI2
SI input setup time
(against SCK↑)
t
t
t
SIK
200
tsys + 200
100
SI1
SI2
SI input hold time
(against SCK↑)
KSI
tsys + 200
100
SO1
SO2
KSO
SCK↓ → SO delay time
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) SCK, SI and SO represent SCK1, SI1, and SO1, respectively for CH1; they represent SCK2, SI2 and
SO2, respectively for CH2.
Note 3) The load of SCK1 and SCK2 output modes and SO1 and SO2 output delay times is 50pF+1TTL.
Serial transfer (CH1, CH2)
(Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Item
Symbol Pin
SCK1
Condition
Input mode
Min.
2tsys + 200
16000/fc
tsys + 100
8000/fc – 150
100
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK cycle time
tKCY
SCK2
Output mode
Input mode
SCK1
SCK2
SCK High and Low
level widths
t
KH
KL
t
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI1
SI2
SI input setup time
(against SCK↑)
t
t
t
SIK
200
tsys + 200
100
SI1
SI2
SI input hold time
(against SCK↑)
KSI
tsys + 250
125
SO1
SO2
KSO
SCK↓ → SO delay time
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) SCK, SI and SO represent SCK1, SI1, and SO1, respectively for CH1; they represent SCK2, SI2 and
SO2, respectively for CH2.
Note 3) The load of SCK1 and SCK2 output modes and SO1 and SO2 output delay times is 50pF.
– 21 –
CXP846P48
Fig. 5. Serial transfer CH1 and CH2 timing
tKCY
tKL
tKH
0.8VDD
0.2VDD
SCK1
SCK2
tSIK
tKSI
0.8VDD
0.2VDD
SI1
SI2
Input data
tKSO
0.8VDD
SO1
SO2
Output data
0.2VDD
– 22 –
CXP846P48
(3) A/D converter characteristics
(Ta = –10 to +75°C, VDD = 3.0 to 5.5V, AVREF = 2.7 to VDD, Vss = AVSS = 0V reference)
Item
Resolution
Symbol
Pin
Condition
Min.
Typ.
Max.
8
Unit
Bits
LSB
±3
Linearity errror
Ta = 25°C
VDD = AVREF = 5.0V
VSS = AVSS = 0V
Zero
transition voltage
1
VZT
–50
10
70
mV
Full-scale transition
voltage
2
VFT
4910
4970
5030
±5
mV
LSB
mV
Linearity errror
Zero
transition voltage
Ta = 25°C
VDD = AVREF = 3.3V
VSS = AVSS = 0V
1
VZT
–10
6.5
110
Full-scale transition
voltage
2
VFT
4870
3280
mV
5070
3
µs
µs
V
t
CONV
SAMP
Convertion time
Sampling time
160/fADC
12/fADC
3
t
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
VDD
VDD
VDD – 0.5
VDD – 0.3
0
Reference input
voltage
VREF
VIAN
AVREF
V
AN0 to AN7
AVREF
1.0
Analog input voltage
V
VDD = 5.5V
Operation
mA
0.6
0.4
IREF
mode
mA
VDD = 3.6V
0.7
AVREF current
AVREF
SLEEP mode
IREFS
STOP mode
10
µA
32kHz operation mode
Fig.6. Definition of A/D converter terms
1
VZT: Value at which the digital conversion value changes
from 00H to 01H and vice versa.
FFH
FEH
2
3
VFT: Value at which the digital conversion value changes
from FEH to FFH and vice versa.
fADC indicates the below values due to the contents of bit 6
(CKS) of the A/D control register (ADC: 00F9H) and bits 7
(PCK1) and 6 (PCK0) of the clock control register (CLC:
00FEH).
Linearity error
CKS
0(φ/2 selection)
1(φ selection)
01H
00H
PCK1, PCK0
fADC = fC/2
fADC = fC/4
fADC = fC/16
00 (φ = fEX/2)
01 (φ = fEX/4)
11 (φ = fEX/16)
fADC = fC
VZT
VFT
Analog input
fADC = fC/2
fADC = fC/8
– 23 –
CXP846P48
(4) Interruption, reset input (Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
INT0
Condition
Min.
Max.
Unit
INT1
INT2
INT3
INT4
NMI
External interruption
HIgh, Low level width
t
IH
IL
1
µs
t
Reset input Low level width
32/fc
µs
tRSL
RST
Fig. 7. Interruption input timing
tIH
tIL
INT0
0.8VDD
INT1
INT2
0.2VDD
INT3
tIL
tIH
INT4
NMI
(NMI is specified only for
the falling edge)
Fig. 8. RST input timing
tRSL
RST
0.2VDD
– 24 –
CXP846P48
(5) I2C bus timing
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
SCL
Condition
Min.
0
Max.
100
Unit
kHz
µs
SCL clock frequency
fSLC
BUF
Bus-free time before starting transfer
Hold time for starting transfer
Clock Low level width
Clock High level width
Setup time for repetitive transfers
Data bold time
t
t
t
t
t
t
t
t
t
t
SDA, SCL
SDA, SCL
SCL
4.7
4.0
4.7
4.0
4.7
HD; STA
LOW
µs
µs
HIGH
SCL
µs
SU; STA
HD; DAT
SU; DAT
R
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
µs
1
0
µs
Data setup time
250
ns
SDA, SCL rise time
1
µs
SDA, SCL fall time
F
300
ns
Setup time for transfer completion
SU; STO
4.7
µs
1
The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into
consideration.
Fig. 9. I2C bus transfer timing
SDA
tBUF
tR
tF
tHD; STA
SCL
tHD; STA
tSU; STO
tSU; STA
P
S
St
P
tLOW
tHD; DAT
tHIGH
tSU; DAT
Fig. 10. Recommended circuit example for I2C device
I2C
device
I2C
device
RS
RS RS
RS RP
RP
SDA0
(or SDA1)
SCL0
(or SCL1)
• Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• Serial resistance (Rs = 300Ω or less) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise caused
by CRT flash-over.
– 25 –
CXP846P48
Appendix
Fig. 11. SPC700 Series recommended oscillation circuit
(i)
(ii)
EXTAL
XTAL
Rd
TEX
TX
Rd
C2
C1
C2
C1
Circuit
example
Manufacturer
Model
fc (MHz)
C1 (pF)
10
C2 (pF)
10
Rd (Ω)
8.00
10.00
12.00
16.00
8.00
RIVER
ELETEC
CO., LTD.
0
HC-49/U03
(i)
5
5
16 (12)
16 (12)
12
16 (12)
16 (12)
12
0
10.00
12.00
HC-49/U (-S)
P3
(i)
0
0
KINSEKI LTD.
16.00
12
12
32.768kHz
(ii)
30
18
470k
Mask option table
Option item
Mask
80-pin plastic QFP
CXP846P48-1-
Package
80-pin plastic QFP
PROM 48K bytes
Existent
ROM capacity
32K/40K/48K bytes
Reset pin pull-up resistance
Existent/Non-existent
– 26 –
CXP846P48
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25°C, Typical)
IDD vs. VDD
(fc = 12MHz, Ta = 25°C, Typical)
50.0
50.0
1/2 frequency mode
1/4 frequency mode
1/16 frequency mode
1/2 frequency mode
1/4 frequency mode
1/16 frequency mode
10.0
5.0
10.0
32kHz mode
(instruction)
5.0
SLEEP mode
SLEEP mode
1.0
0.5
1.0
0.5
0.1
0.1
(100µA)
(100µA)
0.05
0.05
(50µA)
(50µA)
32kHz
SLEEP mode
0.01
0.01
(10µA)
(10µA)
3
4
5
6
3
4
5
6
VDD–Supply voltage [V]
VDD–Supply voltage [V]
IDD vs. fc
(VDD = 5.0V, Ta = 25°C, Typical)
IDD vs. fc
(VDD = 3.3V, Ta = 25°C, Typical)
30
30
20
1/2 frequency mode
20
10
0
1/2 frequency mode
1/4 frequency mode
1/4 frequency mode
10
0
1/16 frequency mode
SLEEP mode
1/16 frequency mode
SLEEP mode
1
5
10
15 16
1
5
10
15 16
fc–System clock [MHz]
fc–System clock [MHz]
– 27 –
CXP846P48
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
0.15
64
41
65
40
A
+ 0.2
0.1 – 0.05
80
25
1
24
+ 0.15
+ 0.35
2.75 – 0.15
0.8
0.35 – 0.1
0.12
M
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
EIAJ CODE
QFP-80P-L01
QFP080-P-1420-A
COPPER / 42 ALLOY
1.6g
JEDEC CODE
PACKAGE WEIGHT
– 28 –
相关型号：
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