ICX406_技术文档

CXD3408GA

Timing Generator and Signal Processor for Frame Readout CCD Image Sensor

Description

96 pin LFLGA (Plastic)

The CXD3408GA is a timing generator and CCD

signal processor IC for the ICX406 CCD image sensor.

Features

• Timing generator functions

• Horizontal drive frequency 18MHz

(base oscillation frequency 36MHz)

• Supports frame readout/draft (quadruple speed)

/AF (auto-focus)

Absolute Maximum Ratings

• High-speed/low-speed shutter function

• Horizontal and vertical drivers for CCD image

sensor

• Supply voltage

V^DDa, VDDb, VDDc, VDDd

VSS – 0.3 to +7.0

VSS – 0.3 to +4.0

–10.0 to VSS

V

VDDe, VDDf, VDDg

• CCD signal processor functions

• Correlated double sampling

• Programmable gain amplifier (PGA) allows gain

adjustment over a wide range (–6 to +42dB)

• 10-bit A/D converter

VL

VH

VL – 0.3 to +26.0

• Input voltage (analog)

V^IN

VSS – 0.3 to VDD + 0.3

V

• Input voltage (digital)

• Chip Scale Package (CSP):

CSP allows vast reduction in the CCD camera

block footprint

VI

• Output voltage

VO1

VSS – 0.3 to VDD + 0.3

VL – 0.3 to VSS + 0.3

VL – 0.3 to VH + 0.3

V

VO2

Applications

V^O3

• Operating temperature

Topr

Digital still cameras

–20 to +75

°C

Structure

• Storage temperature

Tstg

Silicon gate CMOS IC

–55 to +125

Applicable CCD Image Sensors

Recommended Operating Conditions

ICX406 (1/1.8", 3980K pixels)

• Supply voltage

V^DDb

3.0 to 5.25

V

VDDa, VDDc, VDDd, VDDe, VDDf, VDDg

3.0 to 3.6

V

VM

0.0

VH

14.5 to 15.5

–7.0 to –8.0

VL

• Operating temperature

Topr

–20 to +75

°C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E01341A26

CXD3408GA

Block Diagram

A1 A2 C7 D8 D7

B8 B6 B9 A6 C5

A3 A4 B4 A5 C4 B5

E2 F2 F3 E3 F1

C4

AVDD5

AVSS6

C7

C8

A9

A8

B7

A7

C6

C9

E9

E8

D9

E7

F9

F8

F7

G9

G8

G7

H7

H8

K7

K8

K9

H9

D0 (LSB)

B3

B2

B1

C3

C2

C1

D3

D2

D1

E1

Serial Port

Register

DAC

D1

D2

C8

D3

C9

D4

CDS

PGA

ADC

CCDIN

AVDD1

AVDD2

AVSS1

Latch

D5

D6

D7

D8

AVSS2

XSHPI

D9 (MSB)

Dummy Pixel

Black Level

Auto Zero

XSHDI

PBLKI

XSHP

XSHD

PBLK

ADCLKI

CLPOBI

CLPDMI

Preblanking

G1

G2

G3

L3

Auto Zero

VSS4

ADCLK

CLPOB

CLPDM

H1

H2

H3

XRS

VDD4

VDD2

RG

VSS5

J3

OSCI

L1

K1

J1

VSS2

VDD3

OSCO

CKI

Pulse Generator

H1

H2

J8

J9

CKO

J2

1/2

MCKO

K2

VSS3

J7

ID/EXP

WEN

N9

M9

SNCSL

N8

Selector

Latch

SSI1

L2

M1

N1

Serial Port

Register

SCK1

SEN1

VH

VM

VL

M5

L4

V Driver

M6

SSGSL

L8

SSG

M8 M3 M7

L5 N5 M4 L6 N6 N4 N7

N2 M2

L9 K3 L7 N3

– 2 –

CXD3408GA

Pin Configuration (Top View)

A

B

C

D

E

F

NC

D2

NC

D1

SCK2

D0

SSI2

SEN2

TEST4

TEST3

TEST5

AVSS5

AVSS4

AVDD4

C9

C8

C7

AVSS6

AVDD3

C4

AVDD5

AVSS3

CCDIN

AVSS1

AVDD1

XSHPI

XSHP

VDD3

D5

D4

D3

C3

D8

D7

D6

C1

C2

D9

DVDD1

DVSS3

DVSS1

DVDD2

AVSS2

PBLKI

PBLK

XRS

AVDD2

XSHDI

XSHD

VDD4

DVSS2

G

H

ADCLKI CLPOBI CLPDMI

ADCLK CLPOB CLPDM

J

CKI

CKO

MCKO

SSI1

VD

VSS5

VDD5

VSS3

VDD2

H1

RG

H2

K

L

OSCO

OSCI

SCK1

VSS2

VDD1

WEN

VSS4

VM

V2

V1A

VH

V3A

VL

VSS1

SSGSL

RST

M

N

TEST1

TEST2

SEN1

1

HD

2

VSS6

V4

4

V1B

5

V3B

6

SUB

7

SNCSL

8

ID/EXP

9

3

– 3 –

CXD3408GA

Pin Description

Symbol

No.

I/O

Description

A1 NC

—

I

No connected. (Open)

A2 NC

A3 SCK2

A4 SSI2

A5 TEST3

CCD signal processor block serial interface clock input. (Schmitt trigger)

CCD signal processor block serial interface data input. (Schmitt trigger)

CCD signal processor block test input 3. Connect to DVSS.

CCD signal processor block analog GND.

Capacitor connection.

I

A6

AVSS4

—

O

I

A7 C8

A8

A9

AVSS6

AVDD5

CCD signal processor block analog GND.

CCD signal processor block analog power supply.

ADC output.

B1 D2

B2 D1

ADC output.

B3 D0

ADC output (LSB).

B4 SEN2

B5 TEST5

CCD signal processor block serial interface enable input. (Schmitt trigger)

CCD signal processor block test input 5. Connect to DV^DD.

CCD signal processor block analog power supply.

Capacitor connection.

I

B6

AV^DD4

—

O

I

B7 C7

B8

B9

AVDD3

AVSS3

CCD signal processor block analog power supply.

CCD signal processor block analog GND.

ADC output.

C1 D5

C2 D4

ADC output.

C3 D3

ADC output.

C4 TEST4

CCD signal processor block test input 4. Connect to DVSS.

CCD signal processor block analog GND.

Capacitor connection.

C5

AVSS5

—

I

C6 C9

C7 C3

C8 C4

C9 CCDIN

D1 D8

D2 D7

D3 D6

D7 C1

D8 C2

Capacitor connection.

CCD output signal input.

O

—

O

—

ADC output.

Capacitor connection.

D9

E1 D9

E2

AVSS1

CCD signal processor block analog GND.

ADC output (MSB).

DVDD1

CCD signal processor block digital power supply. (Power supply for ADC)

– 4 –

CXD3408GA

No.

Symbol

I/O

Description

CCD signal processor block digital GND.

E3

E7

E8

E9

F1

F2

F3

F7

F8

F9

DVSS1

AVSS2

AVDD2

AVDD1

DVSS2

DVSS3

DVDD2

PBLKI

XSHDI

XSHPI

—

I

CCD signal processor block analog GND.

CCD signal processor block analog power supply.

CCD signal processor block digital GND.

CCD signal processor block digital power supply.

Pulse input for horizontal and vertical blanking period pulse cleaning. (Schmitt trigger)

CCD data level sample-and-hold pulse input. (Schmitt trigger)

CCD precharge level sample-and-hold pulse input. (Schmitt trigger)

Clock input for analog/digital conversion. (Schmitt trigger)

CCD optical black signal clamp pulse input. (Schmitt trigger)

CCD dummy signal clamp pulse input. (Schmitt trigger)

Pulse output for horizontal and vertical blanking period pulse cleaning.

CCD data level sample-and-hold pulse output.

I

G1 ADCLKI

G2 CLPOBI

G3 CLPDMI

G7 PBLK

I

O

—

I

G8 XSHD

G9 XSHP

H1 ADCLK

H2 CLPOB

H3 CLPDM

H7 XRS

CCD precharge level sample-and-hold pulse output.

Clock output for analog/digital conversion.

CCD optical black signal clamp pulse output.

CCD dummy signal clamp pulse output.

Sample-and-hold pulse output for analog/digital conversion phase alignment.

Timing generator block digital power supply. (Power supply for CDS block)

Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2)

Inverter input.

H8

H9

J1

J2

J3

J7

J8

J9

V^DD4

VDD3

CKI

CKO

VSS5

VSS3

H1

O

—

O

—

O

—

I

Inverter output.

Timing generator block digital GND.

CCD horizontal register clock output.

H2

CCD horizontal register clock output.

K1 OSCO

K2 MCKO

Inverter output for oscillation. When not used, leave open or connect a capacitor.

System clock output for signal processor IC.

K3

K7

VDD5

VDD2

Timing generator block digital power supply. (Power supply for common logic block)

Timing generator block digital power supply. (Power supply for RG)

CCD reset gate pulse output.

K8 RG

K9

L1

VSS2

Timing generator block digital GND.

OSCI

Inverter input for oscillation. When not used, fix to low.

– 5 –

CXD3408GA

No.

Symbol

I/O

I

Description

Timing generator block serial interface data input.

Schmitt trigger input/No protective diode on power supply side.

L2 SSI1

L3

VSS4

—

O

Timing generator block digital GND.

Timing generator block digital GND. (GND for vertical driver)

CCD vertical register clock output.

Timing generator block digital GND.

Internal SSG enable.

L4 VM

L5 V1A

L6 V3A

O

L7

L8 SSGSL

L9

VSS1

—

I

—

I

High: Internal SSG valid, Low: External sync valid

(With pull-down resistor)

VDD1

Timing generator block digital power supply. (Power supply for common logic block)

Timing generator block serial interface clock input.

Schmitt trigger input/No protective diode on power supply side.

M1 SCK1

M2 VD

I

Vertical sync signal input.

Timing generator block test input 1.

Normally fix to GND.

M3 TEST1

I

(With pull-down resistor)

M4 V2

M5 VH

M6 VL

O

—

CCD vertical register clock output.

Timing generator block 15.0V power supply. (Power supply for vertical driver)

Timing generator block –7.5V power supply. (Power supply for vertical driver)

Timing generator block test input 2.

M7 TEST2

I

Normally fix to GND.

(With pull-down resistor)

Timing generator block reset input.

High: Normal operation, Low: Reset control

Normally apply reset during power-on.

M8 RST

I

Schmitt trigger input/No protective diode on power supply side

M9 WEN

N1 SEN1

N2 HD

O

I

Memory write timing pulse output.

Timing generator block serial interface strobe input.

Schmitt trigger input/No protective diode on power supply side

I

Horizontal sync signal input.

N3

VSS6

—

O

Timing generator block digital GND.

CCD vertical register clock output.

CCD electronic shutter pulse output.

Control input used to switch sync system.

N4 V4

N5 V1B

N6 V3B

N7 SUB

N8 SNCSL

N9 ID/EXP

I

High: CKI sync, Low: MCKO sync

(With pull-down resistor)

Vertical direction line identification pulse output/exposure time identification pulse

output.

O

Switching possible using the serial interface data. (Default: ID)

– 6 –

CXD3408GA

Electrical Characteristics

Timing Generator Block Electrical Characteristics

DC Characteristics

(Within the recommended operating conditions)

Item

Pins

Symbol

Conditions

Min.

3.0

Typ. Max. Unit

Supply voltage 1

Supply voltage 2

Supply voltage 3

Supply voltage 4

VDD2

VDD3

VDD4

3.3

3.6

5.25

3.6

V

V^DDa

VDDb

VDDc

VDDd

V^{I +}

3.0

VDD1, VDD5

3.0

3.6

0.8V^DDd

Input

voltage 1

RST, SCK1,

SSI1, SEN1

1

VI –

0.2VDDd

0.3VDDd

0.2VDDd

0.4

V

VIH1

VIL1

0.7VDDd

0.8VDDd

Input

voltage 2

TEST1, TEST2

SNCSL, SSGSL

2

VIH2

VIL2

Input/Output

voltage

VD, HD

VOH1

VOL1

VOH2

VOL2

VOH3

VOL3

Feed current where I^OH= –1.2mA V^DDd – 0.8

Pull-in current where IOL = 2.4mA

Feed current where IOH = –22.0mA VDDb – 0.8

Pull-in current where IOL = 14.4mA

Output

voltage 1

H1, H2

RG

0.4

Feed current where IOH = –3.3mA VDDa – 0.8

Pull-in current where IOL = 2.4mA

Output

voltage 2

0.4

XSHP, XSHD,

XRS, PBLK,

CLPOB,

CLPDM,

ADCLK

Feed current where IOH = –3.3mA

V

V^OH4

V^OL4

V^DDc – 0.8

Output

voltage 3

Pull-in current where IOL = 2.4mA

0.4

VOH5

VOL5

VOH6

VOL6

VOH7

VOL7

IOL

Feed current where IOH = –6.9mA VDDd – 0.8

Pull-in current where IOL = 4.8mA

V

Output

voltage 4

CKO

0.4

Feed current where IOH = –3.3mA VDDd – 0.8

Pull-in current where IOL = 2.4mA

V

Output

voltage 5

MCKO

V

Feed current where IOH = –2.4mA VDDd – 0.8

Pull-in current where IOL = 4.8mA

V

Output

voltage 6

ID/EXP,

WEN

0.4

V

V1A/B, V2, V3A/B, V4 = –8.25V

V1A/B, V2, V3A/B, V4 = –0.25V

V1A/B, V3A/B = 0.25V

V1A/B, V3A/B = 14.75V

SUB = –8.25V

10.0

mA

V1A, V1B,

V3A, V3B,

V2, V4

IOM1

IOM2

IOH

–5.0

–7.2

–4.0

Output

current 1

5.0

IOSL

IOSH

5.4

Output

current 2

SUB

SUB = 14.75V

1

This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC.

These input pins are with pull-down resistor in the IC.

2

Note) This table indicates conditions at 3.3V drive.

– 7 –

CXD3408GA

Inverter I/O Characteristics for Oscillation

(Within the recommended operating conditions)

Item

Pins

Symbol

LVth

V^IH

Conditions

Min.

Typ.

Max. Unit

Logical Vth OSCI

V^DDd/2

V

0.7V^DDd

Input

OSCI

voltage

VIL

0.3VDDd

V

VOH

VOL

Feed current where IOH = –3.6mA V^DDd – 0.8

Output

OSCO

voltage

Pull-in current where IOL = 2.4mA

0.4

5M

Feedback

resistor

OSCI, OSCO RFB

VIN = VDDd or VSS

500k

20

2M

Ω

Oscillation

frequency

OSCI, OSCO

f

50

MHz

Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment

(Within the recommended operating conditions)

Item

Pins

Symbol

LVth

V^IH

Conditions

Min.

Typ.

Max.

Unit

V

Logical Vth

VDDd/2

0.7V^DDd

V

Input

voltage

CKI

V^IL

0.3VDDd

V

Input

amplitude

VIN

fmax 50MHz sine wave

0.3

Vp-p

Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude

is the input amplitude characteristics in the case of input through a capacitor.

Switching Characteristics

(VH = 15.0V, VM = GND, VL = –7.5V)

Item

Symbol

Conditions

Min.

200

30

Typ.

350

60

Max.

500

90

Unit

ns

V

TTLM VL to VM

TTMH VM to VH

TTLH VL to VH

TTML VM to VL

TTHM VH to VM

TTHL VH to VL

VCLH

Rise time

Fall time

200

30

350

60

500

90

1.0

VCLL

V

Output noise voltage

VCMH

V

VCML

V

Notes)

1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for

measures to prevent electrostatic discharge.

2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between

each power supply pin (VH, VL) and GND.

3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.

– 8 –

CXD3408GA

Switching Waveforms

TTMH

90%

TTHM

90%

VH

VM

V1A (V1B, V3A, V3B)

TTLM

10%

90%

TTML

10%

90%

10%

VL

TTLM

TTML

VM

90%

V2 (V4)

10%

VL

TTLH

TTHL

VH

90%

SUB

10%

VL

Waveform Noise

VM

VCMH

VCML

VCLH

VCLL

VL

– 9 –

CXD3408GA

C 9

P B L K

X S H D

X S H P

S S 5 A V

T E S T 4

D 3

D 4

S S V 4

C L P O B

C L P D M

X R S

D 5

D D 3 A V

S S 3 A V

C 7

D D V 4

D D V 3

C K I

D D 4 A V

T E S T 5

C K O

S E N 2

D 0

S S V 5

S S V 3

H 1

D 1

D 2

H 2

D D 5 A V

D D V 5

S S 6 A V

C 8

O S C I

O S C O

S S 4 A V

D D V 2

R G

S S V 2

T E S T 3

S S I 2

S C K 2

N C

M C K O

S S I 1

N C

S S V 6

– 10 –

CXD3408GA

AC Characteristics

AC characteristics between the serial interface clocks

0.8VDDd

SSI1

SCK1

SEN1

0.2VDDd

0.8VDDd

ts1

th1

ts2

0.2VDDd

ts3

0.8VDDd

(Within the recommended operating conditions)

Symbol

ts1

Definition

Min.

20

Typ.

Max.

Unit

ns

SSI1 setup time, activated by the rising edge of SCK1

SSI1 hold time, activated by the rising edge of SCK1

SCK1 setup time, activated by the rising edge of SEN1

SEN1 setup time, activated by the rising edge of SCK1

20

ns

th1

ts2

ts3

20

ns

20

ns

Serial interface clock internal loading characteristics (1)

Example: During frame mode

VD

HD

V1A

Enlarged view

HD

0.2VDDd

ts1

V1A

th1

0.8VDDd

SEN1

0.2VDDd

Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal period

during which V1A/B and V3A/B values take the ternary value and during that horizontal period.

(Within the recommended operating conditions)

Symbol

ts1

th1

Definition

SEN1 setup time, activated by the falling edge of HD

SEN1 hold time, activated by the falling edge of HD

– 11 –

Min.

0

Typ.

Max.

Unit

ns

µs

110

CXD3408GA

Serial interface clock internal loading characteristics (2)

Example: During frame mode

VD

HD

Enlarged view

VD

HD

0.2VDDd

ts1

th1

0.8VDDd

SEN1

0.2VDDd

Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.

(Within the recommended operating conditions)

Symbol

ts1

th1

Definition

Min.

0

Typ.

Max.

Unit

ns

SEN1 setup time, activated by the falling edge of VD

SEN1 hold time, activated by the falling edge of VD

200

ns

Serial interface clock output variation characteristics

Normally, the serial interface data is loaded to the CXD3408GA at the timing shown in "Serial interface clock

internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is

loaded to the CXD3408GA and controlled at the rising edge of SEN1. See "Description of Operation".

0.8VDDd

SEN1

Output signal

tpdPULSE

(Within the recommended operating conditions)

Symbol

Definition

Min.

5

Typ.

Max.

100

Unit

ns

tpdPULSE Output signal delay, activated by the rising edge of SEN1

– 12 –

CXD3408GA

RST loading characteristics

0.8VDDd

RST

0.2VDDd

tw1

(Within the recommended operating conditions)

Symbol

Definition

Min.

25

Typ.

Max.

Unit

ns

RST pulse width

tw1

VD and HD phase characteristics

VD

HD

0.2VDDd

ts1

th1

0.2VDDd

(Within the recommended operating conditions)

Symbol

Definition

Min.

100

Typ.

Max.

Unit

ns

VD setup time, activated by the falling edge of HD

VD hold time, activated by the falling edge of HD

ts1

th1

20

ns

HD loading characteristics

HD

0.2VDDd

ts1

th1

0.8VDDd

MCKO

MCKO load capacitance = 10pF

Symbol

(Within the recommended operating conditions)

Definition

Min.

20

5

Typ.

Max.

Unit

ns

HD setup time, activated by the rising edge of MCKO

HD hold time, activated by the rising edge of MCKO

ts1

th1

ns

– 13 –

CXD3408GA

Output variation characteristics

0.8VDDd

MCKO

WEN, ID/EXP

tpd1

WEN and ID/EXP load capacitance = 10pF

(Within the recommended operating conditions)

Symbol

tpd1

Definition

Min.

20

Typ.

Max.

60

Unit

ns

Time until the above outputs change after the rise of MCKO

– 14 –

CXD3408GA

CCD Signal Processor Block Electrical Characteristics

DC Characteristics

(Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)

Item

Pins

Symbol

V^DDe

Conditions

Min.

3.0

Typ. Max. Unit

Supply voltage 1 DVDD1

Supply voltage 2 DVDD2

3.3 3.6

V

VDDf

3.0

AVDD1,

AVDD2,

Supply voltage 3 AVDD3,

AVDD4,

VDDg

3.0

3.3 3.6

V

AVDD5

Analog input

CCDIN

CIN

VI +

15

pF

V

capacitance

SCK2, SSI2,

1.8

SEN2, TEST3,

TEST4, XSHDI,

XSHPI, ADCLKI,

CLPOBI,

Input voltage

VI –

1.1

V

CLPDMI, PBLKI

A/D clock duty ADCLKI

50

%

V

VOH

VOL

Feed current where I^OH= –2.0mA V^DDe – 0.9

Output voltage D0 to D9

Pull-in current where IOL = 2.0mA

0.4

V

Analog Characteristics

(Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)

Item

Symbol

Conditions

Min. Typ. Max. Unit

CCDIN input voltage amplitude

PGA maximum gain

V^IN

PGA gain = 0dB, output full scale

PGA gain setting data = "3FFh"

PGA gain setting data = "000h"

900

1100 mV

Gmax

Gmin

42

–6

10

dB

PGA minimum gain

ADC resolution

bit

ADC maximum conversion rate

ADC integral non-linearity error

Fc max

18

MHz

EL

PGA gain = 0dB

±1.0 ±5.0 LSB

±0.5 ±1.0 LSB

ADC differential non-linearity error ED

CCDIN input connected to GND

via a coupling capacitor

PGA gain = 0dB

1

Signal-to-noise ratio

SNR

62

dB

CCDIN input voltage clamp level

CLP

OB

1.5

32

V

CCD optical black signal clamp

level

OBLVL = "8h"

PGA gain = 0dB

LSB

1

SNR = 20 log (full-scale voltage/rms noise)

– 15 –

CXD3408GA

AC Characteristics

AC characteristics between the serial interface clocks

0.8VDD

SSI2

0.2VDD

0.8VDD

ts1

SCK2

th1

SEN2

0.2VDD

ts3

0.8VDD

ts2

The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise of

SEN2.

(Fc = 18MSPS, DV^DD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)

Symbol

tp1

Definition

Min.

100

30

Typ.

Max.

Unit

ns

SCK2 clock period

SSI2 setup time, activated by the rise of SCK2

SSI2 hold time, activated by the rise of SCK2

SCK2 setup time, activated by the rise of SEN2

SEN2 setup time, activated by the rise of SCK2

ns

ts1

th1

ts2

ts3

30

ns

30

ns

30

ns

– 16 –

CXD3408GA

CDS/ADC Timing Chart

N

N + 1

N + 2

N + 3

CCDIN

XSHPI

XSHDI

tw1

ADCLKI

D0 to D9

DL

N – 10

N – 9

N – 8

N – 7

Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0".

(Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)

Symbol

tw1

Definition

Min.

54

Typ.

Max.

Unit

ADCLKI clock period

ADCLKI clock duty

Data latency

ns

%

50

9

DL

clocks

Preblanking Timing Chart

PBLKI

11 Clocks

ADCLKI

D0 to D9

11 Clocks

All "0"

– 17 –

CXD3408GA

Description of Operation

Pulses output from the CXD3408GA's timing generator block are controlled mainly by the RST pin and by the

serial interface data. The Pin Status Table is shown below, and the details of serial interface control are

described on page 20 and thereafter.

Pin Status Table

No.

Symbol CAM SLP

STB

RST

Symbol CAM SLP

STB

RST

—

A1 NC

D3 D6

A2 NC

D7 C1

A3 SCK2

A4 SSI2

A5 TEST3

A6 AV^SS4

A7 C8

D8 C2

D9 AVSS1

E1 D9

E2 DVDD1

E3 DVSS1

E7 AVSS2

E8 AVDD2

E9 AVDD1

F1 DVSS2

F2 DVSS3

F3 DVDD2

F7 PBLKI

F8 XSHDI

F9 XSHPI

G1 ADCLKI

G2 CLPOBI

G3 CLPDMI

G7 PBLK

G8 XSHD

G9 XSHP

H1 ADCLK

H2 CLPOB

H3 CLPDM

H7 XRS

A8 AVSS6

A9 AVDD5

B1 D2

B2 D1

B3 D0

B4 SEN2

B5 TEST5

B6 AVDD4

B7 C7

B8 AVDD3

B9 AVSS3

C1 D5

ACT

L

H

C2 D4

ACT

H

C3 D3

C4 TEST4

C5 AVSS5

C6 C9

H

C7 C3

ACT

C8 C4

—

C9 CCDIN

D1 D8

H8 VDD4

H9 VDD3

ACT ACT ACT

ACT

D2 D7

J1 CKI

– 18 –

CXD3408GA

No.

Symbol CAM SLP

STB

RST

Symbol

CAM SLP

ACT ACT

STB

L

RST

J2 CKO

J3 V^SS5

J7 VSS3

J8 H1

ACT L9 VDD1

M1 SCK1

—

ACT ACT ACT

DIS

H

1

M2 VD

ACT

L

ACT

L

ACT M3 TEST1

ACT M4 V2

ACT M5 VH

ACT M6 VL

M7 TEST2

—

J9 H2

ACT

VM

K1 OSCO

K2 MCKO

K3 VDD5

K7 VDD2

K8 RG

ACT ACT ACT

—

ACT ACT

L

—

M8 RST

ACT ACT ACT

ACT

ACT ACT ACT

L

ACT

L

ACT M9 WEN

N1 SEN1

L

K9 VSS2

L1 OSCI

L2 SSI1

L3 VSS4

L4 VM

—

DIS

H

1

ACT ACT ACT

ACT N2 HD

ACT

L

ACT ACT ACT

DIS

N3 VSS6

N4 V4

—

ACT

VM

VH

VM

VH

VL

VM

VL

N5 V1B

N6 V3B

N7 SUB

N8 SNCSL

L5 V1A

L6 V3A

L7 VSS1

L8 SSGSL

ACT

VH

VM

VL

—

ACT ACT ACT

ACT

L

ACT ACT ACT

ACT N9 ID/EXP

L

¹It is for output. For input, all items are "ACT".

Note) ACT means that the circuit is operating, and DIS means that loading is stopped.

L indicates a low output level, and H a high output level in the controlled status.

Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L4) and VL (Pin M6),

respectively, in the controlled status.

– 19 –

CXD3408GA

Timing Generator Block Serial Interface Control

The CXD3408GA's timing generator block basically loads and reflects the timing generator block serial

interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion

specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value.

Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the

rising edge of SEN1.

00 01 02 03 04 05 06 07

41 42 43 44 45

46 47

SSI1

SCK1

SEN1

There are two categories of timing generator block serial interface data: CXD3408GA timing generator block

drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data").

The details of each data are described below.

– 20 –

CXD3408GA

Control Data

Data

Symbol

Function

Data = 0

Data = 1

RST

D00

to

D07

All

0

10000001 → Enabled

Other values → Disabled

CHIP

CTG

Chip enable

D08,

D09

All

0

Category switching

See D08 to D09 CTG.

D10

to

D12

All

0

MODE

Drive mode switching

See D10 to D12 MODE.

1

D13 SMD

Electronic shutter mode switching

0

OFF

ON

1

D14 HTSG

HTSG control switching

D15,

D16

All

0

—

D17 NTPL

SSG function switching

0

NTSC

PAL

D18

to

D31

All

0

—

D32 FGOB

D33 EXP

Wide OBCLP generation switching

ID/EXP output switching

0

OFF

ID

ON

EXP

D34,

PTOB

D35

All

0

OBCLP waveform patterm switching

ADCLK logic phase adjustment

Standby control

See D34 to D35 PTOB.

See D36 to D37 LDAD.

See D38 to D39 STB.

1

0

D36,

LDAD

D37

D38,

STB

D39

All

0

D40

to

D47

All

0

—

1

See D13 SMD.

– 21 –

CXD3408GA

Shutter Data

Data

Symbol

Function

Data = 0

Data = 1

RST

D00

to

D07

10000001 → Enabled

Other values → Disabled

All

0

CHIP

CTG

SVD

Chip enable

D08,

D09

All

0

Category switching

See D08 to D09 CTG.

D10

to

D19

Electronic shutter vertical period

specification

All

0

See D10 to D19 SVD.

See D20 to D31 SHD.

See D32 to D41 SPL.

D20

to

D31

Electronic shutter horizontal period

specification

All

0

SHD

SPL

D32

to

D41

High-speed shutter position

specification

All

0

D42

to

D47

All

0

—

– 22 –

CXD3408GA

Detailed Description of Each Data

Shared data: D08 , D09 CTG [Category]

Of the data provided to the CXD3408GA by the serial interface, the CXD3408GA loads D10 and subsequent

data to each data register as shown in the table below according to the combination of D08 and D09 .

D09

0

D08

0

Description of operation

Loading to control data register

Loading to shutter data register

Test mode

0

1

X

Note that the CXD3408GA can apply these categories consecutively within the same vertical period. However,

care should be taken as the data is overwritten if the same category is applied.

Control data: D10 to D12 MODE [Drive mode]

The CXD3408GA timing generator block drive mode can be switched as follows. However, the drive mode bits

are located to the CXD3408GA and reflected at the falling edge of VD.

D12

0

D11

0

D10

0

Description of operation

Draft mode (default)

AF1 mode

D12

1

D11

0

D10

0

Description of operation

Draft mode

0

1

0

1

Frame mode (A field read out)

Frame mode (B field read out)

Test mode

0

1

0

AF2 mode

1

0

1

Frame mode

1

Draft mode is the pulse eliminator drive mode called octuple speed mode in the ICX406. This is a high frame

rate drive mode that can be used for purposes such as monitoring and auto focus (AF).

AF1 and AF2 modes are the pulse eliminator drive modes called by the same names in the ICX406. These

drive modes are based on draft mode, and are used to increase the frame rate for auto focus (AF). In these

modes, the screen is swept in the vertical direction and the center portion lines are cut out.

Frame mode is the ICX406 drive mode in which the data for all lines are read. This drive mode is comprised of

A and B Fields, so when it is established, repeated drive is performed in the manner of A → B → A → and so

on.

Frame mode (A or B Field) is the drive mode in which each field can be specified separately.

Control data: D17 NTPL [SSG function switching]

The CXD3408GA internal SSG output pattern can be switched as follows. However, the SSG function switching

bits are loaded to the CXD3408GA and reflected at the falling edge of VD.

D17

0

Description of Operation

NTSC equivalent pattern output

PAL equivalent pattern output

1

VD period in each pattern is defined as follows.

Frame mode

Draft mode

AF1 mode

AF2 mode

56H + 686ck

67H + 1178ck

112H + 1372ck

134H + 2354ck

NTSC equivalent pattern

PAL equivalent pattern

1012H + 1672ck 224H + 1372ck × 2

944H + 464ck

269H + 2039ck

See the Timing Charts for the actual operation.

– 23 –

CXD3408GA

Control data: D32 FGOB [Wide CLPOB generation]

This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual

operation. The default is "OFF".

D32

0

Description of operation

Wide CLPOB generation OFF

Wide CLPOB generation ON

1

Control data: D34 , D35 PTOB [CLPOB waveform pattern]

This indicates the CLPOB waveform pattern. The default is "Normal".

D35

0

D34

0

Waveform pattern

(Normal)

(Shifted rearward)

0

1

(Shifted forward)

(Wide)

1

0

1

Control data: D36 , D37 LOAD [ADCLK logical phase]

This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.

D37

0

D36 Degree of adjustment (°)

0

1

0

1

0

90

1

180

270

1

Control data: D38 , D39 STB [Standby]

The operating mode is switched as follows. However, the standby bits are loaded to the CXD3408GA and

control is applied immediately at the rising edge of SEN1.

D39

X

D38 Symbol

Operating mode

Normal operating mode

Sleep mode

0

1

CAM

SLP

STB

0

1

Standby mode

See the Pin Status Table for the pin status in each mode.

– 24 –

CXD3408GA

Control data/shutter data: [Electronic shutter]

The CXD3408GA realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG

and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.

These functions are described in detail below.

First, the various modes are shown below.

These modes are switched using control data D13 SMD.

D13

0

Description of operation

Electronic shutter stopped mode

Electronic shutter mode

1

The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.

However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.

MSB

LSB

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20

X

0

1

0

1

↓

SHD is expressed as 1C3h .

1

C

3

[Electronic shutter stopped mode]

During this mode, all shutter data items are invalid.

SUB is not output in this mode, so the shutter speed is the accumulation time for one field.

[Electronic shutter mode]

During this mode, the shutter data items have the following meanings.

Symbol

SVD

Data

Description

D10 to D19 Number of vertical periods specification (000h ≤ SVD ≤ 3FFh)

D20 to D31 Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh)

D32 to D41 Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)

SHD

SPL

Note) The bit data definition area is assured in terms of the CXD3408GA functions, and does not assure the

CCD characteristics.

The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure

time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the

operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.

(Exposure time) = SVD + {(number of HD per 1V) – (SHD + 1)}

Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed

shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this

period is finished.

The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of

horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).

– 25 –

CXD3408GA

VD

SHD

SVD

V1A

SUB

WEN

EXP

SMD

SVD

SHD

1

002h

10Fh

000h

050h

Exposure time

Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the

low-speed shutter period.

In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.

SPL

000

001

002

VD

SVD

SHD

V1A

SUB

WEN

EXP

SMD

SPL

SVD

SHD

1

001h

002h

10Fh

000h

0A3h

Exposure time

Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD.

Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed

shutter to high-speed shutter or vice versa.

– 26 –

CXD3408GA

[HTSG control mode]

This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG.

D14

0

Description of operation

Readout pulse (SG) normal operation

HTSG control mode

1

VD

V1A

SUB

Vck

WEN

EXP

HTSG

SMD

0

1

0

1

Exposure time

[EXP pulse]

The ID/EXP pin (N9) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The

default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time

when it is high. The transition point is the last SUB pulse falling edge, and midpoint value (1338ck) of each

V1A/B and V3A/B ternary out put falling edge. When there is no SUB pulse, the later ternary output falling

edge (1416ck) is used. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for

an image of operation.

Note that the above specification is based on draft mode. For frame mode, the former value is 1260ck and the

latter value is 1416ck.

– 27 –

CXD3408GA

1 7 1 9

1 5 4 7

1 7 1 5

1 7 1 3

1 7 1

1

1 7 0 9

1 7 2 0

1 7 1 8

1 7 1 6

1 7 1 4

1 7 1 2

– 28 –

CXD3408GA

1 7 1 7 1 7 1 3

1 7 1 0 1 7 0 6

1 7 1 7 1 7 1 3

1 7 1 0 1 7 0 6

– 29 –

CXD3408GA

– 30 –

CXD3408GA

– 31 –

CXD3408GA

– 32 –

CXD3408GA

– 33 –

CXD3408GA

– 34 –

CXD3408GA

– 35 –

CXD3408GA

2 8 4

2 5 2

2 2 0

1 8 8

1 5 6

1 2 4

1 2 9 2

1 2 6 0

1 2 0 2

1 2 0 0

1 1 6 8

1 1 3 6

1 1 0 4

– 36 –

CXD3408GA

1 8 0

1 6 4

1 4 8

1 3 2

1 7 2

1 5 6

1 4 0

1 2 4

1 0 8

9 2

6 1 1

1 0 0

8 4

6 8

7 6

6 0

1 4 1 6

1 3 5 8

1 2 0 2

1 3 5 6

1 3 2 4

1 2 9 2

1 2 6 0

1 2 0 0

1 1 6 8

1 1 3 6

1 1 0 4

– 37 –

CXD3408GA

3 0 8

2 9 2

2 7 6

2 6 0

2 4 4

2 2 8

2 1 2

1 9 6

1 8 0

1 6 4

1 4 8

1 3 2

3 0 0

2 8 4

2 6 8

2 5 2

2 3 6

2 2 0

2 0 4

1 8 8

1 7 2

1 5 6

1 4 0

1 2 4

1 0 8

9 2

6 1 1

1 0 0

8 4

6 8

7 6

6 0

1 5 6 8

1 5 5 2

1 5 3 6

1 5 2 0

1 5 0 4

1 4 8 8

1 4 7 2

1 4 5 6

1 5 6 0

1 5 4 4

1 5 2 8

1 5 1 2

1 4 9 6

1 4 8 0

1 4 6 4

1 4 4 8

1 4 1 6

1 3 5 8

1 3 5 6

1 3 2 4

1 2 9 2

1 2 6 0

1 2 0 2

1 2 0 0

1 1 6 8

1 1 3 6

1 1 0 4

– 38 –

CXD3408GA

– 39 –

CXD3408GA

– 40 –

CXD3408GA

CCD Signal Processor Block Serial Interface Control

The CXD3408GA's CCD signal processor block basically loads the CCD signal processor block serial interface

data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the

operation 6 ADCLKI clocks after that.

CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect

the serial interface data to operation, so this should normally be performed when the timing generator block is

in the normal operation mode.

00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15

SSI2

SCK2

SEN2

There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain

setting data, OB clamp level setting data, and input pulse polarity setting data.

Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is

valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for

each category and wait until the setting value 6 ADCLKI clocks after that has been reflected to operation, then

transmit the next category.

The detail of each data are described below.

Standby Control Data

Data

Symbol

Function

Data = 0

Data = 1

D00 TEST

D01

Test code

Set to 0.

to

D03

CTG

Category switching

D01 to D03 CTG

Set to All 0.

D04

to

FIXED

—

D14

D15 STB

Standby control

Normal operating mode

Standby mode

PGA Gain Setting Data

Data

Symbol

Function

Data = 0

Data = 1

D00 TEST

D01

Test code

Set to 0.

to

D03

CTG

Category switching

—

D01 to D03 CTG

Set to All 0.

D04,

D05

FIXED

GAIN

D06

to

PGA gain setting data

See D06 to D15 GAIN.

D15

– 41 –

CXD3408GA

OB Clamp Level Setting Data

Data Symbol

Function

Data = 0

Data = 1

D00 TEST

D01

Test code

Set to 0.

to

D03

CTG

Category switching

—

D01 to D03 CTG

Set to All 0.

D04

to

D11

FIXED

OBLVL

D12

to

OB clamp level setting data

See D12 to D15 OBLVL.

D15

Input Pulse Polarity Setting Data

Data Symbol

Function

Data = 0

Data = 1

D00 TEST

D01

Test code

Set to 0.

to

CTG

Category switching

D01 to D03 CTG

D03

D04

to

D12

FIXED

POL

—

Set to All 0.

D13

to

Input pulse polarity setting data

D15

– 42 –

CXD3408GA

Detailed Description of Each Data

Shared data: D01 to D03 CTG [Category]

Of the data provided to the CXD3408GA by the CCD signal processor block serial interface, the CXD3408GA

loads D04 and subsequent data to each data register as shown in the table below according to the combination

of D01 to D03 .

D01 D02 D03

Description of operation

Loading to standby control data register

Loading to PGA gain setting data register

Loading to OB clamp level setting data register

Loading to input pulse polarity setting data register

Access prohibited

0

1

0

1

X

0

1

0

1

X

Standby control data: D15 STB [Standby]

The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor

block is in standby mode, only the serial interface is valid.

D15

0

Description of operation

Normal operating mode

Standby mode

1

PGA gain setting data: D06 to D15 GAIN [PGA gain]

The CXD3408GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by

using PGA gain setting data D06 to D15 GAIN.

The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN.

MSB

LSB

D06 D07 D08 D09 D10 D11 D12 D13 D14 D15

0

1

0

1

↓

GAIN is expressed as 1C3h .

1

C

3

For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting

values are –6dB, 0dB, +20dB, +34dB and +42dB.

– 43 –

CXD3408GA

OB clamp level setting data: D12 to D15 OBLVL [OB clamp level]

The CXD3408GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal

processor block control data D12 to D15 OBLVL.

The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL.

MSB

LSB

D12 D13 D14 D15

0

1

0

↓

OBLVL is expressed as 6h .

6

For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values

are 0LSB, 4LSB, 32LSB and 60LSB.

– 44 –

CXD3408GA

S C K 2

S E N 2

S S I 2

C 9

C 8

C 7

F µ 0 . 1

S C K 1

S E N 1

S S I 1

A D C L K I

A D C L K

C L P O B

C L P D M

T E S

P B L K

X S H D

X S H P

C L P O B I

C L P D M I

P B L K I

O S C I

X S H D I

X S H P I

O S C

C K I

– 45 –

CXD3408GA

Notes on Operation

1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the

figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In

addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pin and CCD signal processor

block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either

before or at the same time as the VH pin power supply is started up.

15.0V

t1

20%

0V

20%

t2

–7.5V

t2 ≥ t1

2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator

block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by

initializing the serial data.

3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor

block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pins.

Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this

pin from other power supplies is recommended to avoid affecting the internal analog circuits.

4. The difference in potential between the timing generator block VDD4 pin supply voltage 3 VDDc and the CCD

signal processor block DV^DD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe,

2 V^DDf and 3 VDDg should be 0.1V or less.

5. The timing generator block and CCD signal processor block ground pins should use a shared ground which

is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the

timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to

the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4,

V^SS5, VSS6 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4,

AVSS5 and AVSS6 should be 0.1V or less.

6. Do not perform serial communication with the CCD signal processor block during the effective image

period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which

are used by the CCD signal processor block, use of the dedicated ports is recommended. When using

these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the

effects on picture quality before use.

– 46 –

CXD3408GA

Package Outline

Unit: mm

0.2

S

A

96PIN LFLGA

Oita Ass'y

8.0

X

PIN 1 INDEX

1.3 MAX

0.10MAX

x4

0.15

DETAIL X

96 -φ0.45 ± 0.05

(0.3)

0.5

0.8

A

S

A B

φ0.08 M

N

M

L

K

J

B

H

G

F

E

D

C

B

3 – φ0.50

A

1

2

3 4 5 6 7 8 9

PACKAGE STRUCTURE

0.5

(0.3)

0.8

0.5

PACKAGE MATERIAL

TERMINAL TREATMENT

TERMINAL MATERIAL

PACKAGE MASS

ORGANIC SUBSTRATE

GOLD PLATING

NICKEL PLATING

0.3 g

LFLGA-96P-02

SONY CODE

EIAJ CODE

P-LFLGA96-12X8-0.8

JEDEC CODE

0.2

S

A

96PIN LFLGA

HITACHI TOKYO Ass'y

8.0

X

PIN 1 INDEX

1.3 MAX

0.10MAX

x4

0.15

DETAIL X

96 -φ0.45 ± 0.05

(0.3)

0.5

0.8

A

M

S A B

φ0.08

N

M

L

K

J

B

H

G

F

E

D

C

B

3 – φ0.50

A

1

2

3 4 5 6 7 8 9

PACKAGE STRUCTURE

0.5

(0.3)

0.8

0.5

PACKAGE MATERIAL

TERMINAL TREATMENT

TERMINAL MATERIAL

PACKAGE MASS

ORGANIC SUBSTRATE

NICKEL & GOLD PLATING

COPPER

LFLGA-96P-051

P-LFLGA96-12.0X8.0-0.8

SONY CODE

EIAJ CODE

JEDEC CODE

0.3g

– 47 –

Sony Corporation


型号：	ICX406
厂家：	SONY CORPORATION
描述：	Timing Generator and Signal Processor for Frame Readout CCD Image Sensor 时序发生器和信号处理器的帧读出CCD图像传感器传感器图像传感器 CD
文件：	总47页 (文件大小：403K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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