LCX018AK [SONY]
1.8cm (0.7-inch) NTSC/PAL/WID Color LCD Panel; 1.8厘米（ 0.7英寸）的NTSC / PAL / WID彩色LCD面板
| 型号： | LCX018AK |
| 厂家： | 
SONY CORPORATION |
| 描述： | 1.8cm (0.7-inch) NTSC/PAL/WID Color LCD Panel |
| 文件： | 总22页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LCX018AK
1.8cm (0.7-inch) NTSC/PAL/WID Color LCD Panel
For the availability of this product, please contact the sales office.
Description
The LCX018AK is a 1.8cm diagonal active matrix
TFT-LCD panel addressed by the polycrystalline
silicon super thin film transistors with built-in
peripheral driving circuit. This panel provides full-
color representation in NTSC/PAL/WID mode. RGB
dots are arranged in a delta pattern featuring high
picture quality of no fixed color patterns, which is
inherent in vertical stripes and mosaic pattern
arrangements.
Features
• Number of active dots: 240,000 (0.7-inch; 1.8cm in diagonal)
• Horizontal resolution: 400 TV lines
• High optical transmittance: 4.4% (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V driving circuit (built-in input level conversion circuit, TTL drive possible)
• High quality picture representation with RGB delta arranged color filters
• Full-color representation
• NTSC/PAL/WID compatible
• Up/down and/or right/left inverse display function
• Side-black function
• 16:9 and 4:3 aspect switching function
Element Structure
• Dots
16:9 display: 1068.5 (H) × 225 (V) = 240,412
4:3 display: 803.5 (H) × 225 (V) = 180,787
• Built-in peripheral driving circuit using the polycrystalline silicon super thin film transistors.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E98521-PS
LCX018AK
Block Diagram
13
6
19
2
9
10 11
7
8
16 15 14
18
17
12
5
4
3
1
Input Signal
Level Shifter
H Shift Register (Bidirectional Scanning)
COM
Pad
– 2 –
LCX018AK
Absolute Maximum Ratings (Vss = 0V)
• H driver supply voltage
• V driver supply voltage
• H driver input pin voltage
HVDD
–1.0 to +17
–1.0 to +17
–1.0 to +17
V
V
V
VVDD
HST, HCK1, HCK2
RGT
• V driver input pin voltage
VST, VCK1, VCK2
CLR, EN
–1.0 to +17
V
• Video signal input pin voltage GREEN, RED, BLUE –1.0 to +15
V
°C
°C
• Operating temperature
• Storage temperature
Topr
Tstg
–10 to +70
–30 to +85
Operating Conditions (Vss = 0V)
• Supply voltage
HVDD
VVDD
13.5 ± 0.5
13.5 ± 0.5
V
V
• Input pulse voltage (Vp-p of all input pins except video signal input pins)
Vin
3.0V or more
Pin Description
Pin
Description
Symbol
No.
1
2
COM
PSIG
SIG1
SIG2
SIG3
HVDD
WID
Common voltage of panel
Improvement signal for uniformity
Video signal (Green) to panel
Video signal (Red) to panel
Video signal (Blue) to panel
Power supply for H driver
3
4
5
6
7
Aspect-ratio switching (H: 16:9, L: 4:3)
8
RGT
HST
Drive direction pulse for H shift register (H: normal, L: reverse)
Start pulse for H shift register drive
Clock pulse for H shift register drive
Clock pulse for H shift register drive
GND (H, V drivers)
9
10
11
12
13
14
15
16
17
18
19
20
HCK1
HCK2
VSS
EN
Enable pulse for gate selection
VCK2
VCK1
VST
Clock pulse for V shift register drive
Clock pulse for V shift register drive
Start pulse for V shift register drive
Drive direction pulse for V shift register (H: normal, L: reverse)
Improvement pulse for uniformity
DWN
PCG
VVDD
SOUT
Power supply for V driver
H, V shift register drive confirmation
– 3 –
LCX018AK
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. The equivalent circuit of each input pin is
shown below. (The resistor value: typ.)
(1) SIG1, SIG2, SIG3, SID
HVDD
From H driver
Input
1MΩ
Signal line
(2) HCK1, HCK2
VVDD
250Ω
250Ω
HCK1
HCK2
Level conversion circuit
(2-phase input)
1MΩ
250Ω
1MΩ
250Ω
(3) HST
HVDD
250Ω
250Ω
1MΩ
Level conversion circuit
(single-phase input)
Input
(4) RGT, WID
HVDD
2.5kΩ
2.5kΩ
1MΩ
Level conversion circuit
(single-phase input)
Input
(5) VCK1, VCK2
VVDD
250Ω
250Ω
VCK1
VCK2
Level conversion circuit
(2-phase input)
1MΩ
250Ω
1MΩ
250Ω
(6) VST, DWN, EN
VVDD
2.5kΩ
2.5kΩ
1MΩ
Level conversion circuit
(single-phase input)
Input
(7) PCG
VVDD
250Ω
250Ω
1MΩ
Level conversion circuit
(single-phase input)
Input
(8) COM
VVDD
Input
LC
1MΩ
– 4 –
LCX018AK
Input Signals
1.Input signal voltage conditions (Vss = 0V)
Item
Symbol
VHIL
Min.
–0.30
2.7
Typ.
Max.
0.30
Unit
V
(Low)
0.0
H driver input voltage
(HST, HCK1, HCK2, RGT, WID)
(High)
3
VHIH
VVIL
5.5
V
(Low)
0.0
–0.30
2.7
0.3
V
V driver input voltage
(VST, VCK1, VCK2, DWN, PCG, EN)
(High)
3
6.0
VVIH
VVC
5.5
V
Video signal center voltage
Common voltage of panel
5.8
6.2
V
VVC – 0.25
VCOM
VVC – 0.4
VVC – 0.1
V
Item
Symbol
Vsig
Min.
Typ.
Max.
Unit
V
1
(VDD = 12.0V)
Video signal input range
VVC + 4.0
VVC + 4.0
VVC – 4.0
VVC – 4.0
Uniformity improvement signal PSIG input voltage
Vpsig
V
Video signal and uniformity improvement signal
input white level
VsigL
V
0.5
1
Video input signal should be symmetrical to VVC.
Supplement) Video signal and uniformity improvement signal input range are set within the range shown
below for VDD and VSS.
Also, video signal white level is defined for VVC as shown below.
VDD
VDD – 1.8
VsigL
Video signal input range
Max. VDD – 1.8 [V]
Min. VSS + 1.3 [V]
White level
VsigL
VVC
VDD + 1.3
VSS
– 5 –
LCX018AK
2. Clock timing conditions (Ta = 25°C)
Item
Symbol
trHst
Min.
Typ.
Max.
30
Unit
Hst rise time
Hst fall time
HST
tfHst
30
Hst data set-up time
Hst data hold time
Hckn 2 rise time
tdHst
35
80
45
90
55
thHst
100
30
trHckn
tfHckn
to1Hck
to2Hck
trVst
ns
Hckn 2 fall time
HCK
30
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Vst rise time
–15
–15
0
0
15
15
100
100
14.5
69
Vst fall time
VST
tfVst
Vst data set-up time
Vst data hold time
Vckn 2 rise time
tdVst
–5.5
49
4.5
59
µs
thVst
trVckn
tfVckn
to1Vck
to2Vck
trEnb
tfEnb
100
100
20
Vckn 2 fall time
VCK
Vck1 fall to Vck2 rise time
Vck1 rise to Vck2 fall time
Enb rise time
–20
–20
—
0
0
20
—
100
100
2250
6050
20
Enb fall time
ENB
—
—
ns
Vck rise/fall to Enb rise time
tdEnb
twEnb
trPcg
2150
5950
—
2200
6000
—
Enb pulse width
Pcg rise time
Pcg fall time
PCG
tfPcg
—
—
20
Pcg fall to Vck rise/fall time
toVck
twPcg
–1050
2450
–1000
2500
–950
2550
Pcg pulse width
2
Hckn and Vckn mean Hck1, Hck2 and Vck1, Vck2. (fHckn = 3.72MHz, fVckn = 7.81kHz)
– 6 –
LCX018AK
<Horizontal Shift Register Driving Waveform>
Item
Symbol
trHst
Waveform
Conditions
2
90%
90%
• Hckn
Hst rise time
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hst
10%
50%
10%
tfHst
Hst fall time
tfHst
trHst
HST
50%
50%
Hst data set-up time
tdHst
Hst
2
• Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
50%
Hck1
Hst data hold time
thHst
tdHst
thHst
90%
10%
2
• Hckn
90%
10%
Hckn 2 rise time
Hckn 2 fall time
trHckn
tfHckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 60ns
thHst = –120ns
2
Hckn
trHckn
tfHckn
HCK
3
50%
50%
Hck1 fall to
Hck2 rise time
Hck1
to1Hck
to2Hck
• tdHst = 60ns
thHst = –120ns
50%
50%
Hck2
Hck1 rise to
Hck2 fall time
to2Hck
to1Hck
– 7 –
LCX018AK
<Vertical Shift Register Driving Waveform>
Item
Symbol
trVst
Waveform
Conditions
90%
90%
2
• Vckn
Vst rise time
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
Vst
10%
50%
10%
50%
Vst fall time
tfVst
trVst
tfVst
3
VST
Vst
Vst data set-up time
tdVst
2
50%
• Vckn
50%
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
Vck1
Vckn
Vst data hold time
Vckn 2 rise time
Vckn 2 fall time
thVst
tdVst
thVst
2
• Vckn
90%
10%
90%
10%
trVckn
tfVckn
to1Vck
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
tdVst = 32µs
thVst = –32µs
trVckn
tfVckn
50%
VCK
3
50%
Vck1 fall to
Vck2 rise time
Vck1
• tdVst = 32µs
thVst = –32µs
50%
50%
Vck1 rise to
Vck2 fall time
Vck2
to2Vck
to2Vck
90%
to1Vck
90%
trEnb
tfEnb
Enb rise time
Enb fall time
10% 10%
Enb
tfEn
trEn
ENB
Vck
50%
Vck rise/fall to
Enb rise time
tdEnb
twEnb
50%
50%
Enb
Enb pulse width
twEnb
4
tdEnb
trPcg
tfPcg
Pcg rise time
Pcg fall time
Vck
50%
PCG
Pcg fall to
Pcg
toVck
twPcg
50%
50%
twPcg
Vck rise/fall time
toVck
Pcg pulse width
4
3 Definitions: The right-pointing arrow (
The left-pointing arrow (
) means +.
) means –.
The black dot at an arrow (
) indicates the start of measurement.
– 8 –
LCX018AK
Electrical Characteristics (Ta = 25°C, HVDD = 13.5V, VVDD = 13.5V)
1. Horizontal drivers
Item
Input pin capacitance Hckn
Hst
Symbol
CHckn
CHst
Min.
Typ.
8
Max.
13
Unit
pF
Condition
8
13
pF
Input pin current
Hck1
Hck2
IHck1
IHck2
IRgt
–450
–900
–130
–190
–200
–25
µA
µA
µA
Hck1 = GND
Hck2 = GND
Hst, Wid, Rgt
Hst, Wid, Rgt = GND
Video signal input pin
capacitance
Csig
IH
150
3.5
200
6
pF
Current consumption
mA
Hckn: Hck1, Hck2 (3.72MHz)
2. Vertical drivers
Item
Input pin capacitance Vckn
Vst
Symbol
CVckn
CVst
Min.
Typ.
8
Max.
13
Unit
pF
Condition
13
8
pF
Input pin current
Vck1
Vck2
–450
–900
–190
–200
µA
µA
IVck1
IVck2
Vck1 = GND
Vck2 = GND
IVst,
IEn
Vst, En, Dwn, Pcg
Current consumption
–130
–25
1.0
µA
Vst, En, Dwn, Pcg = GND
Vckn: Vck1, Vck2 (7.87kHz)
2.0
mA
IV
3. Total power consumption of the panel
Item
Symbol
Min.
Typ.
60
Max. Unit
Total power consumption of the panel (NTSC) PWR
120
mW
4. COM input resistance
Item
Symbol
Min.
0.5
Typ.
1
Max. Unit
COM – Vss input resistance
Rcom
MΩ
5. Improvement signal for uniformity
Item
Symbol
Min.
—
Typ.
7
Max. Unit
Improvement signal for uniformity
CPSIGon
10
nF
– 9 –
LCX018AK
Electro-optical Characteristics
(Ta = 25°C, NTSC mode)
Measurement
method
Max.
Unit
Item
Symbol
Min.
Typ.
80
80
200
200
4.4
—
—
25°C
60°C
CR25
—
%
Contrast ratio
1
2
CR60
T
Optical transmittance
R
3.8
—
0.580
0.300
0.250
0.550
0.105
0.070
1.1
0.620
0.340
0.290
0.590
0.140
0.110
1.5
0.660
0.380
0.330
0.630
0.175
0.150
2.2
X
Y
Rx
Ry
X
Gx
CIE
standards
Chromaticity
G
B
3
Y
Gy
X
Bx
Y
By
25°C
60°C
25°C
60°C
25°C
60°C
R vs. G
B vs. G
0°C
V90-25
V90-60
V50-25
V50-60
V10-25
V10-60
V50RG
V50BG
ton0
ton25
toff0
toff25
F
V90
V50
V10
1.0
1.3
2.1
1.5
2.0
2.5
V-T
characteristics
4
V
1.4
1.8
2.4
2.2
2.7
3.2
2.1
2.5
3.1
—
–0.10
0.10
25
–0.25
0.45
100
40
Half tone color
reproduction range
5
6
V
—
—
ON time
—
8
25°C
0°C
Response time
Flicker
ms
—
65
150
60
OFF time
—
20
25°C
60°C
60min.
7
8
9
—
—
–40
20
dB
s
—
—
Image retention time
YT60
Vcomopt
5.60
5.75
5.90
V
Optimum Vcom voltage
– 10 –
LCX018AK
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 13.5V, VVDD = 13.5V
VVC = 6.0V, Vcom = 5.75V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of screen unless otherwise specified.
(4) Measurement systems
Two types of measurement system are used as shown below.
(5) RGB input signal voltage (Vsig)
Vsig = 6 ± VAC [V]
(VAC: signal amplitude)
Measurement system I
Back
light
Luminance
Meter
Measurement
Equipment
3.5mm
Back light: color temperature 8500K, +0.004uV (25°C)
Back light spectrum (reference) is listed on another page.
LCD panel
Measurement system II
Optical fiber
Measurement
Equipment
Light receptor lens
Light Detector
LCD panel
Drive Circuit
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
L (White)
L (Black)
CR =
... (1)
L (White): Surface luminance of the TFT-LCD panel at the RGB signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.5V
Both luminosities are measured by System I.
– 11 –
LCX018AK
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
L (White)
T =
× 100 [%] ... (2)
Luminance of Back Light
L (White) is the same expression as defined in the "Contrast Ratio" section.
3. Chromaticity
Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses
Chromaticity of x and y on the CIE standards here.
Signal amplitudes (VAC) supplied to each input
R input
0.5
G input
4.5
B input
4.5
R
G
B
4.5
4.5
4.5
0.5
0.5
4.5
(Unit: V)
4. V-T Characteristics
V-T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II. V90, V50 and V10 correspond to
the each voltage which defines 90%, 50% and 10% of
transmittance respectively.
90
50
10
5. Half Tone Color Reproduction Range
V90 V50 V10
Half tone color reproduction range of the LCD panels is
characterized by the differences between the V-T
characteristics of R, G and B. The differences of these
V-T characteristics are measured by System II. System
II defines signal voltages of each R, G, B raster modes
which correspond to 50% of transmittance, V50R, V50G
and V50B respectively. V50RG and V50BG, the voltage
differences between V50R and V50G, V50B and V50G, are
simply given by the following formula (3) and (4)
respectively.
VAC – Signal amplitude [V]
100
50
0
V50RG
V50BG
G raster
B raster
R raster
V50RG = V50R – V50G ... (3)
V50BG = V50B – V50G ... (4)
V50R V50B
V50G
VAC – Signal amplitude [V]
– 12 –
LCX018AK
6. Response Time
Input signal voltage (waveform applied to the measured pixels)
Response time ton and toff are defined by
the formula (5) and (6) respectively.
ton = t1 – tON ... (5)
4.5V
6V
0.5V
toff = t2 – tOFF ... (6)
t1: time which gives 10% transmittance of
the panel.
0V
t2: time which gives 90% transmittance of
the panel.
Light transmission
output waveform
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
100%
90%
10%
0%
tON t1
ton
tOFF t2
toff
7. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
component
AC
F [dB] = 20 log
{
}
... (7)
DC component
R, G, B input signal condition for gray raster mode is given by
Vsig = 6 ± V50 [V]
where: V50 is the signal amplitude which gives 50% of
transmittance in V-T curve.
8. Image Retention Time
Image retention time is given by the following procedures:
Apply monoscope signal to the LCD panel for 60 minutes and then change monoscope signal to gray scale
signal (Vsig = 6 ± VAC (V); VAC = 3 to 4V) so as to give the maximum image retention. Hold input signal VAC.
The time of the residual image to disappear gives the image retention time.
Monoscope signal conditions:
Black level
Vsig = 6 ± 4.5 or 6 ± 2.0 [V]
4.5V
White level
(shown in the right figure)
Vcom = 5.6V
2.0V
6V
0V
2.0V
4.5V
Vsig waveform
– 13 –
LCX018AK
9. Method of Measuring the Optimum Vcom
There are two methods of measuring the optimum Vcom using the photoelectric element.
9-1. Method of Measuring Flicker
In the field invert drive mode, adjust the flicker level of the half tone (Vsig = 1.5 to 2.5V) using the
photoelectric element and oscilloscope so that its 30Hz component becomes minimum. The Vcom value
at this time is taken to be the optimum Vcom.
9-2. Method of Measuring Contrast
In the normal 1H invert drive mode, adjust the optical output voltage of the half tone (Vsig = 1.5 to 2.5V) so
that it becomes minimum. The Vcom value at this time is taken to be the optimum Vcom.
Example of Back Light Spectrum (Reference)
0.6
0.4
0.2
0
380
480
580
680
780
Wave length 380 – 780 [nm]
– 14 –
LCX018AK
) m m 5 7 7 . 8 e v i t c e f f E (
s t o d 5 2 2
s t o d 2
s t o d 2
– 15 –
LCX018AK
) m m 5 7 7 . 8 e v i t c e f f E (
s t o d 5 2 2
s t o d 2
s t o d 2
– 16 –
LCX018AK
2. LCD Panel Operations
[Description of basic operations]
The basic operations of the LCD panel are shown below based on the wide-display mode.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 225 gate lines sequentially in every single horizontal scanning period.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuit,
applies selected pulses to every 1068.5 signal electrodes sequentially in a single horizontal scanning period.
• Vertical and horizontal shift registers address one pixel, and then dot Thin Film Transistors (TFTs; two TFTs
for one dot) turn on to apply a video signal to the dot. The same procedures lead to the entire 480 × 1068.5
dots to display a picture in a single vertical scanning period.
• The LCD pixel dots are arranged in a delta pattern, where the dots connected to the identical signal line are
positioned with 1.5-dot offset against those of the adjacent horizontal line. Horizontal Start Pulse (HST) is
generated with 1.5-bit offset between the horizontal lines to regulate the above offset. HCK and sample-hold
(S/H) pulses follow the same 1.5-bit offset scheme.
• The video signal must be input with polarity-inverted system in every horizontal cycle.
• Timing diagrams of the vertical and the horizontal display cycle are shown below.
(1) Vertical display cycle (down-direction scanning)
VD
VST
1
2
3
223 224 225
VCK1
VCK2
Vertical display cycle
(2) Horizontal display cycle (16:9)
BLK
HST
HCK1
HCK2
1
2
3
355 356 357
Horizontal display
cycle
(3) Horizontal display cycle (4:3)
BLK
HST
HCK1
HCK2
1
2
3
267 268 269
Horizontal display cycle
– 17 –
LCX018AK
[Description of operating mode]
The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
• 4:3 display mode with side-black display
These modes are controlled by three signals (RGT, DWN, and WID). The setting mode is shown below:
WID RGT
Mode
16:9 right scan
DWN
Mode
Down scan
Up scan
H
H
L
H
L
H
L
16:9 left scan
4:3 right scan
4:3 left scan
H
L
L
The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin
block upside.
• The analog signal (PSIG) to display side-black shall be input by 1H inversion synchronized with the signal.
3. 3-dot Simultaneous Sampling (RGB Simultaneous Sampling)
Horizontal driver samples SIG1, SIG2 and SIG3 signal simultaneously, which requires the phase matching
between SIG1, SIG2, and SIG3 signals to prevent horizontal resolution from deteriorating. Thus phase
matching between each signal is required using an external signal delaying circuit before applying video
signal to the LCD panel.
The block diagram of the delaying procedure using sample-and-hold method is as follows.
The LCX018 has the right/left inverse function. The following phase relationship diagram indicates the phase
setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be
inverted between SIG2 and SIG3 signals.
SIG2
S/H
S/H
CK3
S/H
AC Amp
4
SIG2
CK2
SIG1
SIG3
3
5
SIG1
SIG3
S/H
AC Amp
AC Amp
CK1
CK3
S/H
CK3
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK2
CK1
CK3
– 18 –
LCX018AK
Example of Color Filter Spectrum (Reference)
100
Color Filter Spectrum
R
80
60
40
G
B
20
0
400
500
600
700
Wavelength [nm]
– 19 –
LCX018AK
Color Display System Block Diagram
+12.0V
+4.5V
+3.0V
+13.5V
PSIG
RED
Composite video
Y/C
Buff.
Y/color difference
GREEN
BLUE
COM
HST
HCK1
HCK2
VST
LCD panel
NT/PAL/WID
LCX018AK
CXA2543R
Serial data
VCK1
VCK2
ENB
PCG
DWN
WID
RGT
(Refer to CXA2543R data sheet.)
Control circuit
– 20 –
LCX018AK
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective
sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily
deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in high temperature or in high humidity, which results in panel damages.
– 21 –
LCX018AK
Package Outline
Unit: mm
2.9 ± 0.15
Thickness of the connector 0.3 ± 0.05
1.3 ± 0.3
10.5 ± 0.05
4
1
3
5
2
6
Incident light
Polarizing Axis
Output light
Polarizing Axis
Incident
light
Active Area
6
No
1
Description
F P C
(15.5)
11.0 ± 0.25
22.0 ± 0.15
Molding material
Outside frame
2
3
P 0.5 ± 0.02 × 19 = 9.5 ± 0.03
+ 0.04
Reinforcing board
0.35 – 0.03
4
0.5 ± 0.1
PIN1
PIN 20
5
Reinforcing material
Polarizing film
6
weight 2g
electrode (enlarged)
The rotation angle of the active area relative to H and V is ± 1°.
– 22 –
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