MB90F983PMC1_技术文档

FUJITSU MICROELECTRONICS

DATA SHEET

DS07-13742-2E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90980 Series

MB90982/MB90F983/MB90V485B

■ DESCRIPTION

The MB90980 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in con-

sumer devices and other applications requiring high-speed real-time processing.

The F²MC-16LX CPU core instruction set retains the AT architecture of the F²MC*¹family, with additional instruc-

tions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete

bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing.

The MB90980 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial inter-

face, UART, 10-bitA/Dconverter, 16-bitI/Otimer, 8/16-bitup/down-counter, PWCtimer, I²Cinterface, DTP/external

interrupt, chip select, and 16-bit reload timer.

*1 : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURES

• Clock

• Minimum instruction execution time:

40.0 ns/6.25 MHz base frequency multiplied × 4 (25 MHz internal operating frequency/3.3 V 0.3 V)

62.5 ns/4 MHz base frequency multiplied × 4 (16 MHz internal operating frequency/3.0 V 0.3 V)

PLL clock multiplier

• Maximum memory space

• 16 Mbytes

(Continued)

The information for microcontroller supports is shown in the following homepage.

Be sure to refer to the "Check Sheet" for the latest cautions on development.

"Check Sheet" is seen at the following support page

"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in

system development.

http://edevice.fujitsu.com/micom/en-support/

2008.8

MB90980 Series

• Instruction set optimized for controller applications

• Supported data types (bit, byte, word, or long word)

• Typical addressing modes (23 types)

• Enhanced signed multiplication/division instruction and RETI instruction functions

• 32-bit accumulator for enhanced high-precision calculation

• Instruction set designed for high-level language (C) and multi-task operations

• System stack pointer adopted

• Instruction set compatibility and barrel shift instructions

• Enhanced execution speed

• 4 byte instruction queue

• Enhanced interrupt functions

• 8 levels setting with programmable priority, 8 external interrupt pins

• Data transmission function (µDMAC)

• Up to 16 channels

• Embedded ROM

• Flash versions : 192 Kbytes, Mask versions : 128 Kbytes

• Embedded RAM

• Flash versions : 12 Kbytes, Mask versions : 10 Kbytes

• General purpose ports

• Up to 48 ports

(10 ports with output open-drain settings)

• 8/10-bit A/D converter

• 8-channel RC sequential comparison type (10-bit resolution, 3.68 µs conversion time (at 25 MHz) )

• I²C interface

• 1 channel, P76/P77 N-ch open drain pin (without P-ch)

• UART

• 1 channel

• Extended I/O serial interface (SIO)

• 2 channels

• 8/16-bit PPG

• 2 channels (with 8-bit × 4 channels/16-bit × 2 channels mode switching function)

• 8/16-bit up/down timer

• 1 channel (with 8-bit × 2 channels/16-bit × 1-channel mode switching function)

• 16-bit PWC

• 2 channels (Capable of compare the inputs)

• 16-bit reload timer

• 1 channel

• 16-bit I/O timer

• 2 channels input capture, 4 channels output compare, 1 channel free run timer

• On chip dual clock generator system

• Low-power consumption (standby) mode

• With stop mode, sleep mode, CPU intermittent operation mode, watch timer mode, timebase timer mode

• Packages

• LQFP 64

• Process

• CMOS technology

• Power supply voltage

3 V, single source (some ports can be operated by 5 V power supply.)

2

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MB90980 Series

■ PRODUCT LINEUP

Part number

Item

MB90982

MB90F983

MB90V485B

Classification

ROM size

Mask ROM product

128 Kbytes

Flash memory product

192 Kbytes

Evaluation product

⎯

RAM size

10 Kbytes

12 Kbytes

16 Kbytes

Number of instructions

Instruction bit length

Instruction length

Data bit length

Minimum execution time

: 351

: 8-bit, 16-bit

: 1 byte to 7 bytes

: 1-bit, 8-bits, 16-bits

: 40 ns (25 MHz machine clock)

CPU function

Ports

General-purpose I/O ports: up to 48

General-purpose I/O ports (CMOS output)

General-purpose I/O ports (with pull-up resistance Input)

General-purpose I/O ports (N-ch open drain output)

UART

1 channel, start-stop synchronized

8-bit × 6 channels/

16-bit × 3 channels

8/16-bit PPG

8-bit × 4 channels/16-bit × 2 channels

8/16-bit up/down

counter/timer

6 event input pins, 8-bit up/down counters : 2

8-bit reload/compare registers : 2

16-bit free run

timer

Number of channels : 1

Overflow interrupt

Number of channels : 6

Pin input factor : A match

signal of compare register

16-bit

I/O timers (OCU)

Output compare Number of channels : 4

Pin input factor : A match signal of compare register

Input capture

(ICU)

Number of channels : 2

Rewriting a register value upon a pin input (rising, falling, or both edges)

DTP/external interrupt circuit Number of external interrupt channels : 8 (edge or level detection)

Extended I/O serial interface 2 channels, embedded

I²C interface*²

PWC

1 channel

2 channels

3 channels

18-bit counter

Timebase timer

A/D converter

Watchdog timer

Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator)

Conversion resolution : 8/10-bit, switchable

One-shot conversion mode (converts selected channel 1 time only)

Scan conversion mode (conversion of multiple consecutive channels,

programmable up to 8 channels)

Continuous conversion mode (repeated conversion of selected channels)

Stop conversion mode (conversion of selected channels with repeated pause)

Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(minimum value, at 4 MHz base oscillator)

Low-power consumption

(standby) modes

Sleep mode, stop mode, CPU intermittent mode, watch timer mode, timebase timer

mode

Process

CMOS

Flash model 3V/5V

power supply*¹

Mask model 3V/5V

power supply*¹

Type

3V/5V power supply*¹

Yes

Emulator power supply*³

⎯

(Continued)

DS07-13742-2E

3

MB90980 Series

(Continued)

*1 : 3V/5V I/F pin : All pins should be for 3 V power supply without P24 to P27, P30 to P37, P40 to P42,

P70 to P74, P76, and P77.

*2 : P76/P77 pins are N-ch open drain pins (without P-ch) at built-in I²C.

*3 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the hardware manual of MB2147-01 or MB2147-20 (“3.3 Emulator-dedicated Power Supply

Switching”) about details.

Note : Ensure that you must write to Flash at V^CC= 3.13 V to 3.60 V (3.3 V + 10%, −5%) .

4

DS07-13742-2E

MB90980 Series

■ PIN ASSIGNMENT

(TOP VIEW)

AV^CC

AVRH

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VSS

2

X1

P27/PPG3

P26/PPG2

P25/PPG1

P24/PPG0

P37/PWC1

P36/PWC0

P35/ZIN1

P34/BIN1

P33/AIN1

P32/ZIN0

P31/BIN0

P30/AIN0

P42/SCK2

3

X0

4

MOD2

5

MOD1

6

MOD0

7

P84/IRQ4

P85/IRQ5

P86/IRQ6

P87/IRQ7

P90/SIN1

P91/SOT1

P92/SCK1

P93/FRCK/ADTG

P96/IN0

8

9

10

11

12

13

14

15

16

V

CC5

VSS

(FPT-64P-M24)

Notes : • I²C pin P76 and P77 are N-ch open drain pin (without P-ch) .

• P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76 and P77 also used as 3 V/5 V I/F pin.

DS07-13742-2E

5

MB90980 Series

■ PIN DESCRIPTIONS

I/O Circuit

type*

Pin No.

Pin name

Function

46

47

50

49

51

X0

X1

A

B

Oscillator pin

X0A

32 kHz oscillator pin

Reset input pin

X1A

RST

P27 to P24

PPG3 to PPG0

P30

General purpose I/O port

PPG timer output pin

General purpose I/O port

E

3 to 6

14

(CMOS/H)

E

(CMOS/H)

AIN0

8/16-bit up/down timer counter input pin (ch.0)

General purpose I/O port

P31

E

13

(CMOS/H)

BIN0

8/16-bit up/down timer counter input pin (ch.0)

General purpose I/O port

P32

E

12

(CMOS/H)

ZIN0

8/16-bit up/down timer counter input pin (ch.0)

General purpose I/O port

P33

E

11

(CMOS/H)

AIN1

8/16-bit up/down timer counter input pin (ch.1)

General purpose I/O port

P34

E

10

(CMOS/H)

BIN1

8/16-bit up/down timer counter input pin (ch.1)

General purpose I/O port

P35

E

9

(CMOS/H)

ZIN1

8/16-bit up/down timer counter input pin (ch.1)

General purpose I/O port

P37, P36

PWC1, PWC0

P40

E

7, 8

19

(CMOS/H)

PWC input pin

General purpose I/O port

G

(CMOS/H)

SIN2

Simple serial I/O 2-input pin

General purpose I/O port

P41

F

18

(CMOS)

SOT2

P42

Simple serial I/O 2-output pin

General purpose I/O port

G

15

(CMOS/H)

SCK2

P63 to P60

AN3 to AN0

P67 to P64

AN7 to AN4

P70

Simple serial I/O 2-clock I/O pin

General purpose I/O port

H

60 to 63

56 to 59

26

(CMOS)

Analog input pin

General purpose I/O port

F

(CMOS)

Analog input pin

General purpose I/O port

G

(CMOS/H)

SIN0

UART data input pin

P71

General purpose I/O port

F

25

(CMOS)

SOT0

UART data output pin

(Continued)

6

DS07-13742-2E

MB90980 Series

I/O Circuit

type*

Pin No.

Pin name

Function

P72

SCK0

P73

General purpose I/O port

UART clock I/O pin

G

24

(CMOS/H)

General purpose I/O port

G

23

22

(CMOS/H)

TIN0

P74

16-bit reload timer event input pin

General purpose I/O port

F

(CMOS)

TOT0

P76

16-bit reload timer output pin

General purpose I/O port

I

This pin functions as the I²C interface clock I/O pin. Set port output to

21

20

(NMOS/H)

SCL

P77

SDA

Hi-Z during the I²C interface operation.

General purpose I/O port

I

This pin functions as the I²C interface data I/O pin. Set port output to

(NMOS/H)

Hi-Z during the I²C interface operation.

P83 to P80

IRQ3 to IRQ0

P87 to P84

IRQ7 to IRQ4

P90

General purpose I/O port

External interrupt input pin

General purpose I/O port

External interrupt input pin

General purpose I/O port

Simple serial I/O1-data input pin

General purpose I/O port

Simple serial I/O-1 data output pin

General purpose I/O port

Simple serial I/O-1 data I/O pin

General purpose I/O port

E

52 to 55

39 to 42

38

(CMOS/H)

E

(CMOS/H)

E

(CMOS/H)

SIN1

P91

D

37

(CMOS)

SOT1

P92

E

36

(CMOS/H)

SCK1

P93

When using free-run timer, this pin functions as the external clock in-

put pin.

FRCK

ADTG

E

35

(CMOS/H)

When using A/D converter, this pin fuctions as the external trigger

input pin.

P96

IN0

General purpose I/O port

E

34

31

(CMOS/H)

Input capture ch.0 trigger input pin

General purpose I/O port

P97

E

(CMOS/H)

IN1

Input capture ch.1 trigger input pin

General purpose I/O port

PA3 to PA0

OUT3 to OUT0

AV^CC

D

27 to 30

(CMOS)

Output compare event output pin

A/D converter power supply pin

A/D converter external reference power supply pin

A/D converter power supply pin

1

2

⎯

AVRH

64

AV^SS

J

43 to 45

32

MD0 to MD2

V^CC3

Operating mode selection input pins

(CMOS/H)

⎯

3.3 V 0.3 V power supply pins (VCC3)

(Continued)

DS07-13742-2E

7

MB90980 Series

(Continued)

I/O Circuit

type*

Pin No.

Pin name

V^CC5

Function

3 V/5 V power supply pin.

5 V power supply pin when P24 to P27, P30 to P37,

P40 to P42, P70 to P74, P76 and P77 are used as 5 V I/F pins.

Usually, use V^CC= VCC3 = VCC5 as a 3 V power supply (when the 3 V

power supply is used alone) .

16

⎯

17, 33,

48

V^SS

⎯

Power supply input pins (GND)

* : Refer to “■ I/O CIRCUIT TYPES” for I/O circuit types.

8

DS07-13742-2E

MB90980 Series

■ I/O CIRCUIT TYPES

Type

Circuit

Remarks

• Oscillator feedback resistance

X1, X0 : approx. 1 MΩ

X1, X1A

X1A, X0A : approx. 10 MΩ

• With standby control

X0, X0A

A

Hard/soft standby

control signal

Hysteresis input with pull-up resistance

B

HYS

• With input pull-up resistance control

• CMOS level input/output

CTL

P-ch

N-ch

C

CMOS

Standby control signal

CMOS level input/output

P-ch

N-ch

D

Standby control signal

• Hysteresis input

• CMOS level output

P-ch

N-ch

E

Standby control signal

(Continued)

DS07-13742-2E

9

MB90980 Series

(Continued)

Type

Circuit

Remarks

• CMOS level input/output

• With open drain control

P-ch

N-ch

Open drain

control signal

F

CMOS

Standby control signal

• CMOS level output

• Hysteresis input

• With open drain control

P-ch

Open drain

control signal

N-ch

G

Standby control signal

• CMOS level input/output

• Analog input

P-ch

N-ch

H

CMOS

Standby control signal

Analog input

• Hysteresis input

• N-ch open drain output

Digital output

I

HYS

Standby control signal

• CMOS level input

• With high voltage control for flash

testing

Flash memory model

Control signal

Mode input

J

Diffusion resistance

Hysteresis input

Mask ROM model

Hysteresis input

10

DS07-13742-2E

MB90980 Series

■ CAUTION OF USING DEVICES

1. Maximum rated voltages (preventing latchup)

In CMOS IC devices, a condition known as latchup may occur if voltages higher than VCC or lower than VSS are

applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between V^CCand

V^SSexceeds the rated voltage level.

When latchup occurs, the power supply current increases rapidly causing the possibility of thermal damage to

circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation.

Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply

voltages (AV^CCand AVRH) and analog input voltages do not exceed the digital power supply (VCC) .

2. Treatment of unused pins

Leavingunusedinputpinsunconnectedcancauseabnormaloperationor latchup, leadingtopermanentdamage.

Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/

output pins may be set to output mode and left open, or set to input mode and treated the same as unused input

pins.

3. Notes on Using External Clock

Even when using an external clock signal, an oscilltion stabilization delay is applied after a power-on reset or

when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper

frequency limit.

The following figure shows a sample use of external clock signals.

X0

OPEN

X1

4. Treatment of Power Supply Pins (VCC/VSS)

When multiple VCC pins or VSS pins are present, device design considerations for prevention of latch-up and

unwanted electromagnetic interference, abnormal storobe signal operation due to ground level rise, and con-

formity with total output current ratings require that all power supply pins must be externally connected to power

supply or ground.

Consideration should be given to connecting power supply sources to the V^CCpin or VSS pin of this device with

as low impedane as possible. It is also recommended that a bypass capacitor of approximately 0.1 µF be placed

between the V^CCand VSS lines as close to this device as possible.

5. Crystal Oscillator Circuits

Noise around the high-speed oscillation pins (X0 and X1) and low-speed oscillation pins (X0A and X1A) may

cause this device to operate abnormally. Design the printed circuit board so that the crystal oscillator (or ceramic

oscillator) and bypass capacitor to the ground are located as close to the high-speed oscillation pins and low-

speed oscillation pins as possible. Also, design the printed circuit board to prevent the wiring from crossing

another writing.

It is highly recommended to provide a printed circuit board artwork surrounding the high-speed oscillation pins

and low-speed oscillation pins with a ground area for stabilizing the operation.

DS07-13742-2E

11

MB90980 Series

6. Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

7. Proper power-on/off sequence

The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power

supply (V^CC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut

off before the digital power supply (V^CC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even

when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed

AV^CC.

8. Treatment of power supply pins on models with A/D converters

Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC,

and AV^SS= VSS.

9. Precautions when turning the power supply on

In order to prevent abnormal operation in the chip’s internal step-down circuits, a voltage rise time during power-

on of 50 µs (0.2 V to 2.7 V) or greater should be assured.

10. Supply Voltage Stabilization

Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation.

As a standard for power supply voltage stability, it is recommended that the peak-to-peak V^CCripple voltage at

commercial supply frequency (50 Hz/60 Hz) be 10 % or less of V^CC, and that the transient voltage fluctuation be

no more than 0.1 V/ms or less when the power supply is turned on or off.

11. Notes on Using Power Supply

Only the MB90980 series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V

power supply, P24 to P27, P30 to P37, P40 to P42 and P70 to P74, P76, P77 can be intefaced as 5 V power

supplies separately from the main 3 V power supply. Note that the analog power supplies (such as AV^CCand

AV^SS) for the A/D converter can be used only as 3 V power supplies.

12. Treatment of NC pins

NC (internally connected) pins should always be left open.

13. Writing to Flash memory

For serial writing to Flash memory, always ensure that the operating voltage VCC is between 3.13 V and 3.6 V.

For normal writing to Flash memory, always ensure that the operating voltage V^CCis between 3.0 V and 3.6 V.

12

DS07-13742-2E

MB90980 Series

■ BLOCK DIAGRAM

X0, X1, RST

X0A, X1A

MD2, MD1, MD0

CPU

Clock control

Circuit

F²MC16LX series core

8

RAM

Interrupt controller

ROM

2

PPG0, PPG1

PPG2, PPG3

8/16-bit PPG

2

AIN0, AIN1

BIN0, BIN1

ZIN0, ZIN1

8/16-bit

up/down counter

Communication

prescaler

2

SIN0

SOT0

SCK0

UART

Input/output timer

2

16-bit input capture ×

IN0, IN1

2 channels

2

SIN1, SIN2

SOT1, SOT 2

SCK1, SCK2

4

Extended I/O serial

interface × 2 channels

OUT0, OUT1,

OUT2, OUT3,

16-bit output compare

×

4 channels

16-bit free-run timer

2

AVCC

AVRH

AV^SS

ADTG

AN0 to AN7

TIN0

TOT0

16-bit reload timer

A/D converter

( 8/10-bit )

8

SCL

SDA

I²C interface

8

PWC0

PWC1

External interrupt

IRQ0 to IRQ7

PWC × 2 channels

I/O port

4

8

3

8

5

2

8

4

2

4

P24 P30 P40 P60 P70 P76, P80 P90 P96, PA0

P77

P97

to

PA3

P27 P37 P42 P67 P74

P87 P93

P40 to P42 ( × 3) : with an open drain setting register

I²C pin P77 and P76 are N-ch open drain pin (without P-ch) .

Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a

set of pins is used with an internal module, it cannot also be used as an I/O port.

DS07-13742-2E

13

MB90980 Series

■ MEMORY MAP

Single chip

FFFFFFH

ROM area

Address #1

FC0000H

010000H

ROM area,

Image of FF bank

Address #2

Address #3

RAM

Register

000100H

0000D0H

Peripheral

000000H

Internal access

No access

Model

Address #1

FC0000^H*¹

Address #2

004000H or 008000H,

Address #3

MB90F983

003100H

selected by the MS bit in

the ROMM register

MB90982

FD0000H*²

002900H

*1 : No memory cells from FC0000H to FC7FFFH and FE0000H to FE7FFFH.

*2 : No memory cells from FE0000^Hto FEFFFFH. The upper part of the 00 bank is set up to mirror the image of

FF bank ROM, to enable efficient use of small model C compilers. Because the lower 16-bit address of the FF

bank and the lower 16-bit address of the 00 bank is the same, enabling reference to tables in ROM without

the “far” pointer declaration.

For example, in accessing address 00C000^Hit is actually the contents of ROM at FFC000H that are accessed.

If the MS bit in the ROMM register is set to “0”, the ROM area in the FF bank will exceed 48 Kbytes and it is

notpossibletoreflecttheentireareaintheimageinthe00bank. ThereforetheimagefromFF4000^HtoFFFFFFH

is reflected in the 00 bank and the area from FF0000^Hto FF3FFFH can be seen in the FF bank only.

14

DS07-13742-2E

MB90980 Series

■ F²MC-16LX CPU PROGRAMMING MODEL

•Dedicated registers

AH

AL

Accumulator

USP

SSP

PS

User stack pointer

System stack pointer

Processor status

Program counter

PC

DPR

Direct page register

PCB

DTB

USB

SSB

ADB

Program counter bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

8-bit

16-bit

32-bit

•General purpose registers

MSB

LSB

16-bit

000180^H+ RP × 10H

RW0

RW1

RW2

RW3

RL0

RL1

R1

R0

R2

R4

R6

RW4

RW5

RW6

RW7

RL2

RL3

R3

R5

R7

•Processor status

PS

bit 15

bit 13 bit 12

bit 8 bit 7

bit 0

ILM

RP

CCR

DS07-13742-2E

15

MB90980 Series

■ I/O MAP

Abbreviated

Address

Register name

R/W

Resource name

Initial value

register name

000000^H,

000001^H

Reserved area

000002^H

000003H

000004H

000005H

000006^H

000007H

000008H

000009H

00000AH

PDR2

PDR3

PDR4

Port 2 data register

R/W

Port 2

Port 3

Port 4

XXXXXXXXB

Port 3 data register

Port 4 data register

R/W

Reserved area

R/W

PDR6

PDR7

PDR8

PDR9

PDRA

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port A data register

Port 6

Port 7

Port 8

Port 9

Port A

XXXXXXXXB

11XXXXXXB

XXXXXXXXB

- - - - XXXXB

R/W

Up/down timer

input control

00000BH

UDER

Up/down timer input enable register R/W

XX 0 0 0 0 0 0^B

00000CH

00000DH

00000EH

00000FH

ENIR

EIRR

Interrupt/DTP enable register

Interrupt/DTP source register

Request level setting register

R/W

0 0 0 0 0 0 0 0B

XXXXXXXXB

DTP/external

interrupts

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

ELVR

000010H,

000011^H

Reserved area

000012^H

000013H

000014H

000015H

000016^H

000017H

000018H

000019H

00001AH

DDR2

DDR3

DDR4

Port 2 direction register

Port 3 direction register

Port 4 direction register

R/W

Port 2

Port 3

Port 4

0 0 0 0 XXXXB

0 0 0 0 0 0 0 0B

R/W

Reserved area

R/W

DDR6

DDR7

DDR8

DDR9

DDRA

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

Port A direction register

Port 6

Port 7

Port 8

Port 9

Port A

0 0 0 0 0 0 0 0B

XX 0 0 0 0 0 0B

0 0 0 0 0 0 0 0B

0 0 XX 0 0 0 0B

- - - - 0 0 0 0B

R/W

Port 4

00001BH

ODR4

Port 4 output pin register

R/W

Reserved area

R/W

XXXXX 0 0 0B

(Open-drain control)

00001CH,

00001D^H

Port 7

(Open-drain control)

00001E^H

ODR7

Port 7 output pin register

XXX 0 0 0 0 0B

00001FH

000020H

ADER

SMR

Analog input enable register

Serial mode register

R/W

Port 6, A/D

1 1 1 1 1 1 1 1B

0 0 0 0 0 X 0 0B

W,

R/W

000021H

SCR

Serial control register

0 0 0 0 0 1 0 0^B

XXXXXXXXB

UART

000022H SIDR/SODR Serial input/output register

R/W

R,

R/W

000023H

000024H

000025^H

SSR

Serial status register

0 0 0 0 1 0 0 0^B

Reserved area

Communication prescaler control

register

Communication

prescaler (UART)

CDCR

R/W

0 0 - - 0 0 0 0^B

(Continued)

16

DS07-13742-2E

MB90980 Series

Abbreviated

register name

Address

Register name

R/W

Resource name

Initial value

000026^H

000027H

000028H

SMCS0

SDR0

Serial mode control status register 0

Serial data register 0

R, R/W

R/W

- - - - 0 0 0 0B

0 0 0 0 0 0 1 0B

XXXXXXXXB

SIO1 (ch.0)

Communication

prescaler

SIO1 (ch.0)

Communication prescaler control

register 0

000029H

SDCR0

R/W

0 - - - 0 0 0 0^B

00002AH

00002BH

00002CH

SMCS1

SDR1

Serial mode control status register 1

Serial data register 1

R, R/W

R/W

- - - - 0 0 0 0B

0 0 0 0 0 0 1 0B

XXXXXXXXB

SIO2 (ch.1)

Communication

prescaler

SIO2 (ch.1)

Communication prescaler control

register 1

00002DH

SDCR1

R/W

0 - - - 0 0 0 0^B

00002EH

00002FH

000030H

000031H

000032H

000033H

000034H

000035H

PRLL0

PRLH0

PRLL1

PRLH1

PRLL2

PRLH2

PRLL3

PRLH3

Reload register L (ch.0)

Reload register H (ch.0)

Reload register L (ch.1)

Reload register H (ch.1)

Reload register L (ch.2)

Reload register H (ch.2)

Reload register L (ch.3)

Reload register H (ch.3)

R/W

XXXXXXXXB

8/16-bit PPG

(ch.0 to ch.3)

000036H

to

Reserved area

000039^H

00003A^H

00003BH

00003CH

00003DH

PPGC0

PPGC1

PPGC2

PPGC3

PPG0 operating mode control register

PPG1 operating mode control register

PPG2 operating mode control register

PPG3 operating mode control register

R/W

0 X 0 0 0XX 1B

0 X 0 0 0 0 0 1B

0 X 0 0 0XX 1B

0 X 0 0 0 0 0 1B

8/16-bit PPG

(ch.0 to ch.3)

00003EH,

00003F^H

Reserved area

000040^H

000041H

000042^H

PPG01

PPG23

PPG0, PPG1 output control register

R/W

8/16-bit PPG

0 0 0 0 0 0 0 0B

Reserved area

PPG2, PPG3 output control register

000043H

to

Reserved area

000045^H

000046^H

000047H

000048H

000049H

ADCS1

ADCS2

ADCR1

ADCR2

R/W

W, R/W

R

0 0 0 0 0 0 0 0B

XXXXXXXXB

Control status register

Data register

8/10-bit

A/D converter

W, R

0 0 0 0 0 XXXB

(Continued)

DS07-13742-2E

17

MB90980 Series

Abbreviated

Address

Register name

R/W Resource name Initial value

register name

00004A^H

00004BH

00004CH

00004DH

00004EH

00004FH

000050H

000051H

Output compare register (ch.0) lower digits

Output compare register (ch.0) upper digits

Output compare register (ch.1) lower digits

Output compare register (ch.1) upper digits

Output compare register (ch.2) lower digits

Output compare register (ch.2) upper digits

Output compare register (ch.3) lower digits

Output compare register (ch.3) upper digits

0 0 0 0 0 0 0 0^B

OCCP0

OCCP1

OCCP2

OCCP3

R/W

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

R/W

16-bit I/O timer

0 0 0 0 0 0 0 0B

output compare

0 0 0 0 0 0 0 0^B

(ch.0 to ch.3)

R/W

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

R/W

0 0 0 0 0 0 0 0B

000052H

to

Reserved area

000055^H

Output compare control register (ch.0, ch.1)

lower digits

000056^H

000057H

000058H

000059H

R/W

0 0 0 0 - - 0 0^B

- - - 0 0 0 0 0^B

0 0 0 0 - - 0 0^B

- - - 0 0 0 0 0^B

OCS01

OCS23

Output compare control register (ch.0, ch.1)

upper digits

16-bit I/O timer

output compare

(ch.0 to ch.3)

Output compare control register (ch.2, ch.3)

lower digits

Output compare control register (ch.2, ch.3)

upper digits

00005AH,

00005B^H

Reserved area

00005C^H

00005DH

00005EH

00005FH

000060H

000061H

000062^H

000063H

000064H

000065H

000066H

000067H

000068H

000069H

00006AH

00006BH

Input capture data register (ch.0) lower digits

Input capture data register (ch.0) upper digits

Input capture data register (ch.1) lower digits

Input capture data register (ch.1) upper digits

Input capture control status register

Reserved area

R

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0B

IPCP0

16-bit I/O timer

input capture

(ch.0, ch.1)

R

IPCP1

ICS01

R

R/W

TCDT

TCCS

Timer counter data register lower digits

Timer counter data register upper digits

Timer counter control status register

Compare clear register lower digits

Compare clear register upper digits

Up/down count register (ch.0)

R/W

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 - - 0 0 0 0 0B

XXXXXXXX^B

16-bit I/O timer

free-run timer

CPCLR

R/W

XXXXXXXXB

UDCR0

UDCR1

RCR0

R

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

Up/down count register (ch.1)

Reload/compare register (ch.0)

W

8/16-bit up/

down counter/

timer

RCR1

Reload/compare register (ch.1)

W,

R/W

00006CH

00006DH

CCRL0

CCRH0

Counter control register (ch.0) lower digits

Counter control register (ch.0) upper digits

0 X 0 0 X 0 0 0^B

0 0 0 0 0 0 0 0B

(Continued)

R/W

18

DS07-13742-2E

MB90980 Series

Abbreviated

registername

Address

Register name

R/W

Resource name

Initial value

00006E^H

Reserved area

ROM mirroring

function

00006F^H

000070H

000071H

ROMM

CCRL1

ROM mirror function select register

R/W

- - - - - - 0 1^B

Counter control register (ch.1)

lower digits

0 X 0 0 X 0 0 0^B

8/16-bit up/down

counter/timer

Counter control register (ch.1)

upper digits

CCRH1

CSR0

R/W

- 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0B

000072H

000073H

000074^H

000075H

000076^H

000077H

000078H

000079H

00007AH

00007BH

00007CH

00007DH

Counter status register (ch.0)

Reserved area

R, R/W

Reserved area

CSR1

Counter status register (ch.1)

8/16-bit UDC

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 XB

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 XB

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

PWCSR0 PWC control/status register

PWCR0 PWC data buffer register

PWCSR1 PWC control/status register

PWCR1 PWC data buffer register

R, R/W

R/W

PWC timer (ch.0)

R, R/W

R/W

PWC timer (ch. 1)

00007EH

to

Reserved area

000081^H

000082^H

000083H

000084^H

DIVR0

DIVR1

Dividing ratio control register

R/W

Reserved area

R/W

PWC (ch.0)

PWC (ch.1)

- - - - - - 0 0B

000085H

to

Reserved area

000087^H

000088^H

000089H

00008AH

00008BH

00008CH

IBSR

IBCR

ICCR

IADR

IDAR

Bus status register

Bus control register

Clock control register

Address register

Data register

R

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

- - 0 X X X X XB

- X X X X X X XB

XXXXXXXXB

R/W

I²C

00008DH,

00008E^H

Reserved area

00008F^H

to

Disabled

00009B^H

00009C^H

00009DH

DSRL

DSRH

µDMAC status register

R/W

µDMAC

0 0 0 0 0 0 0 0B

Program address detection control

status resister

Address match

detection function

00009EH

00009FH

PACSR

DIRR

R/W

0 0 0 0 0 0 0 0^B

- - - - - - - 0B

Dilayed interrupt source generator/

cancel register

Delayed interruput

generator module

(Continued)

DS07-13742-2E

19

MB90980 Series

Abbreviated

Address

Register name

R/W

Resource name

Initial value

register name

Low-power consumption mode control

register

Low-power

operation

0000A0^H

0000A1H

LPMCR

CKSCR

W, R/W

0 0 0 1 1 0 0 0^B

Low-power

operation

Clock select register

R, R/W

1 1 1 1 1 1 0 0B

0000A2H

to

Reserved area

0000A7^H

0000A8^H

0000A9H

0000AAH

0000ABH

0000AC^H

0000ADH

0000AEH

0000AFH

0000B0^H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

WDTC

TBTC

WTC

Watchdog timer control register

Timebase timer control register

Watch timer control register

R, W

Watchdog timer XXXXX 1 1 1B

W, R/W Timebase timer 1 X X 0 0 1 0 0B

R, R/W

Watch timer

1 0 0 0 1 0 0 0B

Reserved area

DERL

DERH

FMCS

µDMAC enable register

R/W

µDMAC

0 0 0 0 0 0 0 0B

Flash memory control status register

W, R/W Flash memory I/F 0 0 0 X 0 0 0 0B

Disabled

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

W, R/W

0 0 0 0 0 1 1 1B

Interrupt controller

0000C0H

to

Reserved area

0000C9^H

0000CA^H

0000CBH

0000CCH

0000CDH

0000CEH

0 0 0 0 0 0 0 0^B

- - - - 0 0 0 0B

TMCSR

Timer control status register

R/W

16-bit reload timer

16-bit timer register/

16-bit reload register

TMR/TMRLR

XXXXXXXX^B

Reserved area

(Continued)

20

DS07-13742-2E

MB90980 Series

(Continued)

Abbreviated

register name

Address

Register name

R/W

Resource name

Initial value

Low-power

operation

0000CF^H

PLLOS

PLL output select register

W

- - - - - - 0 0^B

0000D0H

to

0000FF^H

External area

RAM area

000100^H

to

00000#^H

Program address detection resister 0

(Low order address)

001FF0^H

001FF1H

001FF2^H

001FF3^H

001FF4H

001FF5^H

Program address detection resister 0

(Middle order address)

Address match

detection function

PADR0

PADR1

R/W

XXXXXXXX^B

Program address detection resister 0

(High order address)

Program address detection resister 1

(Low order address)

Program address detection resister 1

(Middle order address)

Address match

detection function

Program address detection resister 1

(High order address)

Notes : • Descriptions for R/W

R/W : Enabled to read and write

: Read only

: Write only

R

W

• Descriptions for initial value

0

1

X

-

: The initila value of this bit is “0”.

: The initial value of this bit is “1”.

: The initial value of this bit is undefined.

: This bit is not used.

DS07-13742-2E

21

MB90980 Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

µDMAC

cnannel

number

Interrupt vector

Interrupt control register

Clear of

EI²OS

Interrupt source

Number Address

Number

Address

Reset

×

⎯

0

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

FFFFDC^H

FFFFD8^H

FFFFD4^H

FFFFD0^H

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

⎯

INT9 instruction

Exception

INT0 (IRQ0)

INT1 (IRQ1)

INT2 (IRQ2)

INT3 (IRQ3)

INT4 (IRQ4)

INT5 (IRQ5)

INT6 (IRQ6)

INT7 (IRQ7)

PWC1

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

×

⎯

1

PWC0

PPG0/PPG1 counter borrow

PPG2/PPG3 counter borrow

⎯

×

2

3

⎯

8/16-bit up/down counter/

timer (ch.0, ch.1) compare/

underflow/overflow/inversion

×

#25

FFFF98^H

ICR07

0000B7H

Input capture (ch.0) load

Input capture (ch.1) load

Output compare (ch.0) match

Output compare (ch.1) match

Output compare (ch.2) match

Output compare (ch.3) match

⎯

5

6

#26

#27

#28

#29

#30

#31

#32

#33

#34

FFFF94H

FFFF90H

FFFF8CH

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

ICR08

ICR09

ICR10

ICR11

0000B8H

0000B9H

0000BAH

0000BBH

8

9

10

×

⎯

11

⎯

UART sending completed

16-bit free run timer overflow,

16-bit reload timer underflow*²

12

#35

FFFF70H

ICR12

ICR13

0000BCH

UART receiving compleated

SIO1 (ch.0)

7

#36

#37

#38

FFFF6CH

FFFF68H

FFFF64H

13

14

0000BDH

SIO2 (ch.1)

(Continued)

22

DS07-13742-2E

MB90980 Series

(Continued)

Interrupt source

µDMAC

channel

number

Interrupt vector

Number Address

Interrupt control register

Clear of

EI²OS

Number

Address

I²C interface

×

#39

#40

FFFF60H

FFFF5CH

ICR14

0000BEH

8/10-bit A/D converter

15

Flash write/erase,

×

#41

#42

FFFF58H

FFFF54^H

timebase timer,watch timer *¹

ICR15

0000BFH

Delay interrupt generator

module

× : Interrupt request flag is not cleared by the interrupt clear signal.

: Interrupt request flag is cleared by the interrupt clear signal.

: Interrupt request flag is cleared by the interrupt clear signal (stop request present) .

*1 : Caution : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time.

*2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE = 1) to disable

(TMCSR : INTE = 0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to IL0 : 111^B) , then

set the INTE bit to 0.

Note : If there are two interrupt sources for the same interrupt number, the interrupt request flags of both resources

are cleared by the EI²OS/µDMAC. Therefore if either of the two sources uses the EI²OS/µDMAC function,

the other interrupt function cannot be used. The interrupt request enable bit for the resource that does not

use the EI²OS/µDMAC function should be set to “0” and the interrupt function should be handled by software

polling.

DS07-13742-2E

23

MB90980 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

VSS − 0.3

V^SS− 0.3

VSS − 0.3

V^SS− 0.3

VSS − 0.3

V^SS− 0.3

−2.0

Max

VSS + 4.0

VSS + 7.0

VSS + 4.0

VSS + 7.0

VSS + 4.0

VSS + 7.0

+2.0

VCC3

V^CC5

V

Power supply voltage*¹

AV^CC

AVRH

V

*2

V

*3

Input voltage*¹

VI

V

*3, *8, *9

V

*3

Output volatage*¹

VO

V

*3, *8, *9

Maximum clamp current

I^CLAMP

Σ⏐I^CLAMP⏐

I^OL

mA

mW

°C

*7

*4

*5

Total maximum clamp current

“L” level maximum output current

“L” level average output current

“L” level maximum total output current

“L” level total average output current

“H” level maximum output current

“H” level average output current

“H” level maximum total output current

“H” level total average output current

Power consumption

⎯

20

⎯

10

I^OLAV

ΣI^OL

⎯

3

⎯

60

ΣI^OLAV

I^OH

⎯

30

*6

*4

*5

⎯

−10

I^OHAV

ΣI^OH

⎯

−3

⎯

−60

ΣI^OHAV

P^D

⎯

−30

*6

⎯

320

Operating temperature

T^A

−40

+85

Storage temperature

Tstg

−55

+150

*1 : This parameter is based on VSS = AVSS = 0.0 V.

*2 : AV^CCand AVRH must not exceed VCC. Also, AVRH must not exceed AVCC.

*3 : V¹and V0 must not exceed VCC + 0.3 V. However, if the maximum current to/from input is limited by some

means with external components, the I^CLAMPrating supersedes the VI rating.

*4 : Maximum output current is defined as the peak value for one of the corresponding pins.

*5 : Average output current is defined as the average current flow in a 100 ms interval at one of the corresponding

pins.

*6 : Average total output current is defined as the average current flow in a 100 ms interval at all corresponding pins.

(Continued)

24

DS07-13742-2E

MB90980 Series

(Continued)

*7 : • Applicable to pins : P24 to P27, P30 to P37, P40 to P42, P60 to P67, P70 to P74, P76, P77,

P80 to P87, P90 to P93, P96, P97, PA0 to PA3

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The +B signal should always be applied with a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply

is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input

pins, etc.) cannot accept +B signal input.

• Sample recommended circuits:

• Input/Output Equivalent circuits

Protective diode

V^CC

Limiting

P-ch

resistance

+B input (0 V to 16 V)

N-ch

R

*8 : P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76, P77 pins can be used as 5 V I/F pin on applied 5 V

to V^CC5 pin.

P76 and P77 is N-ch open drain pin.

*9 : As for P76 and P77 (N-ch open drain pin) , even if using at 3 V simplicity (V^CC3 = VCC5) , the ratings are applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

DS07-13742-2E

25

MB90980 Series

2. Recommended Operating Conditions

(VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

2.7

1.8

2.7

1.8

Max

3.6

5.5

V

During normal operation

V^CC3

To maintain RAM state in stop mode

During normal operation*

Supply voltage

V^CC5

V^IH

To maintain RAM state in stop mode*

All pins other than V^IH2, VIHS, VIHM and

V^IHX

0.7 VCC

VCC + 0.3

V

VIH2

V^IHS

V^IHM

V^IHX

V^IL

0.7 VCC

0.8 VCC

VCC − 0.3

0.8 VCC

VSS − 0.3

−40

VSS + 5.8

VCC + 0.3

0.3 VCC

0.2 VCC

VSS + 0.3

0.1

V

°C

P76, P77 pins (N-ch open drain pins)

Hysteresis input pins

MD pin input

“H” level input voltage

X0A pin, X1A pin

All pins other than VILS, VILM and VIHX

Hysteresis input pins

MD pin input

VILS

V^ILM

V^ILX

T^A

“L” level input voltage

Operating temperature

X0A pin, X1A pin

+85

* : P24 to P27, P30 to P37, P40 to P42, P70 to P74, P76, P77 pins can be used as 5 V I/F pin on applied 5 V to

V^CC5 pin.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

26

DS07-13742-2E

MB90980 Series

3. DC Characteristics

(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Remarks

Parameter Symbol Pin name

Condition

Unit

Min

Typ

Max

V^CC= 2.7 V,

V^CC3 − 0.3

⎯

V

I^OH= −1.6 mA

“H” level

output voltage

All output

pins

V^OH

V^CC= 4.5 V,

I^OH= −4.0 mA

V^CC= 2.7 V,

I^OL= 2.0 mA

V^CC= 4.5 V,

I^OH= 4.0 mA

VCC = 3.3 V,

V^SS< VI < VCC

V^CC= 3.0 V,

at T^A= +25 °C

At using 5 V

power supply

V^CC5 − 0.5

⎯

53

⎯

0.4

+10

200

V

“L” level

output voltage

All output

pins

V^OL

At using 5 V

power supply

V

Input leakage

current

All input

pins

I^IL

−10

20

µA

kΩ

Pull-up

resistance

R^PULL

⎯

P40 to P42,

P70 to P74,

P76, P77

Open drain

output current

I^leak

⎯

0.1

45

55

17

10

60

70

35

µA

mA

At V^CC= 3.3 V,

internal 25 MHz operation,

normal operation

I^CC

⎯

At V^CC= 3.3 V,

internal 25 MHz operation,

Flash programming

At V^CC= 3.3 V,

internal 25 MHz operation,

sleep mode

I^CCS

⎯

Power supply

current

At V^CC= 3.3 V,

external 32 kHz,

internal 8 kHz operation,

sub clock operation

(T^A= +25 °C)

I^CCL

⎯

15

140

40

µA

At V^CC= 3.3 V,

external 32 kHz,

internal 8 kHz operation,

watch mode (T^A= +25 °C)

T^A= +25 °C, stop mode,

at V^CC= 3.3 V

I^CCT

⎯

1.8

I^CCH

C^IN

⎯

0.8

5

40

15

µA

Other than

AV^CC, AVSS,

V^CC, VSS

Input

capacitance

⎯

pF

Notes : • Pins P40 to P42, P70 to P74, P76, and P77 are N-ch open drain pins with control, which are usually

used as CMOS.

• P76 and P77 are open drain pins without P-ch.

• For use as a single 3 V power supply products, set V^CC= VCC3 = VCC5.

• When the device is used with dual power supplies, P24 to P27, P30 to P37, P40 to P42, P70 to P74,

P76 and P77 serve as 5 V pins while the other pins serve as 3 V I/O pins.

DS07-13742-2E

27

MB90980 Series

4. AC Characteristics

(1) Clock Timing

(V^SS= 0.0 V, TA = −40 °C to +85 °C)

Value

Typ

Sym-

Condi-

tion

Parameter

bol

Pin name

Unit

Remarks

Min

Max

External crystal

oscillator

⎯

3

⎯

25

⎯

3

4

⎯

50

25

External clock input

1 multiplied PLL

2 multiplied PLL

3 multiplied PLL

4 multiplied PLL

6 multiplied PLL

8 multiplied PLL

3

⎯

12.5

6.66

6.25

4.16

3.12

⎯

F^CH

X0, X1

MHz

kHz

Clock frequency

3

⎯

3

⎯

3

⎯

3

⎯

F^CL

X0A, X1A

X0, X1

⎯

20

⎯

32.768

⎯

t^C

333

⎯

ns *1

Clock cycle time

t^CL

X0A, X1A

30.5

µs

P^WH

X0

X0A

X0

⎯

5

⎯

15.2

⎯

5

ns

PWL

Input clock pulse width

P^WLH

⎯

µs *2

PWLL

t^cr

tcf

Input clock rise, fall time

ns With external clock

f^CP

f^CPL

t^CP

⎯

1.5

⎯

25

⎯

MHz *1

kHz

Internal operating clock

frequency

8.192

⎯

40.0

⎯

666

⎯

ns *1

µs

Internal operating clock

cycle time

t^CPL

122.1

*1 : Be careful of the operating voltage.

*2 : Duty raito should be 50 % 3 %.

28

DS07-13742-2E

MB90980 Series

• X0, X1 clock timing

t

C

0.8 VCC

0.2 VCC

X0

PWH

PWL

t

cf

tcr

• X0A, X1A clock timing

X0A

t

CL

0.8 VCC

0.1 V

P

WLH

PWLL

t

cf

tcr

DS07-13742-2E

29

MB90980 Series

• Range of warranted PLL operation

Internal operating clock frequency vs. Power supply voltage

3.6

Range of warranted PLL operation

3.0

2.7

Normal operating range

16

1.5

4

25

Internal clock fCP (MHz)

Notes: • Only at 1 multiplied PLL, use with more than f^CP= 4 MHz.

• For A/D operating frequency, refer to “5. A/D Converter Electrical Characteristics”.

Base oscillator frequency vs. Internal operating clock frequency

× 8*³

25

24

× 6*³

No multiplied

× 3*¹

20

× 2*^1,*²

× 1*¹

18

16

× 4

*^1,*²

12

9

8

6

4

1.5

3 4 5 6 8 10 12.5 16

20

25

32

40

50

Base oscillator clock F^CH(MHz)

*1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP ≤ 25 MHz, set

the PLLOS register to “DIV2 bit = 1” and “PLL2 bit = 1”.

[Example] When using the base oscillator frequency of 24 MHz at 1 multiplied PLL :

CKSCR register : CS1 bit = “0”, CS0 bit = “0” PLLOS register : DIV2 bit = “1”, PLL2 bit = “1”

[Example] When using the base oscillator frequency of 6 MHz at 3 multiplied PLL :

CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : DIV2 bit = “1”, PLL2 bit = “1”

*2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < f^CP≤ 25 MHz, the following

setting is also enabled.

2 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “0”

PLLOS register : DIV2 bit = “0”, PLL2 bit = “1”

4 multiplied PLL : CKSCR register : CS1 bit = “0”, CS0 bit = “1”

PLLOS register : DIV2 bit = “0”, PLL2 bit = “1”

*3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to “DIV2 bit = 0” and “PLL2 bit = 1”.

[Example] When using the base oscillator frequency of 4 MHz at 6 multiplied PLL :

CKSCR register : CS1 bit = “1”, CS0 bit = “0” PLLOS register : DIV2 bit = “0”, PLL2 bit = “1”

[Example] When using the base oscillator frequency of 3 MHz at 8 multiplied PLL :

CKSCR register : CS1 bit = “1”, CS0 bit = “1” PLLOS register : DIV2 bit = “0”, PLL2 bit = “1”

30

DS07-13742-2E

MB90980 Series

AC standards are set at the following measurement voltage values.

• Output signal waveform

• Input signal waveform

Hysteresis input pins

Output pins

0.8 VCC

0.2 VCC

2.4 V

0.8 V

• Pins other than hysteresis input/MD input

0.7 VCC

0.3 VCC

DS07-13742-2E

31

MB90980 Series

(2) Reset Input Standards

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Condi-

tions

Parameter

Symbol

Unit

Remarks

name

Min

Max

16 t^CP*¹

⎯

ns

Normal operation

Oscillator oscillation time*²

Reset input time

t^RSTL

RST

⎯

ms Stop mode

+ 4 tCP*¹

*1 : t^CPis internal operating clock cycle time. Refer to “ (1) Clock Timing”.

*2 : Oscillator oscillation time is the time to 90 % of amplitude. For a crystal oscillator this is on the order of several

milliseconds to tens of milliseconds. For a ceramic oscillator, this is several hundred microseconds to

several milliseconds. For an external clock signal the value is 0 ms.

• In stop mode

t

RSTL

RST

0.2 Vcc

90 % of

amplitude

X0

Internal

operating

clock

Oscillator

oscillation time

4 tCP

Oscillator stabilization wait time

Instruction execution

Internal reset

32

DS07-13742-2E

MB90980 Series

(3) Power-on Reset Standards

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min

⎯

1

Max

30

Power rise time

t^R

VCC

ms

*

⎯

Power down time

t^OFF

⎯

ms In repeated operation

* : Power rise time requires V^CC< 0.2 V.

Notes: • The above standards are for the application of a power-on reset.

• Within the device, the power-on reset should be applied by switching the power supply off and on again.

tR

2.7 V

VCC

0.2 V

tOFF

Rapid fluctuations in power supply voltage may trigger a power-on reset in some

cases. As shown below, when changing supply voltage during operation, it is

recommended that voltage changes be suppressed and a smooth restart be applied.

Main power supply voltage

VCC

The slope of voltage increase

should be kept within 50 mV/ms.

Sub power supply voltage

RAM data maintenance

VSS

DS07-13742-2E

33

MB90980 Series

(4) UART Timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Serial clock cycle time

SCK↓→SOT delay time

Symbol

t^SCYC

t^SLOV

⎯

Conditions

Unit Remarks

Min

8 t^CP*²

−80

−120

100

200

tCP*²

4 t^CP*²

4 tCP*²

⎯

Max

⎯

ns

+80

+120

⎯

ns

⎯

Internal shift clock

mode output pins :

C^L*¹= 80 pF + 1 TTL

ns f^CP= 8 MHz

ns

Valid SIN→SCK↑

t^IVSH

⎯

ns f^CP= 8 MHz

SCK↑→valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHIX

t^SHSL

t^SLSH

⎯

ns

⎯

ns

⎯

ns

150

200

⎯

ns

SCK↓→SOT delay time

Valid SIN→SCK↑

t^SLOV

t^IVSH

t^SHIX

⎯

External shift clock

mode output pins :

C^L*¹= 80 pF + 1 TTL

⎯

ns f^CP= 8 MHz

ns

60

120

60

⎯

ns f^CP= 8 MHz

ns

⎯

SCK↑→valid SIN hold time

120

⎯

ns f^CP= 8 MHz

*1 : C^Lis the load capacitance applied to pins for testing.

*2 : t^CPis internal operating clock cycle time. Refer to “ (1) Clock Timing”.

Note : AC ratings are for CLK synchronized mode.

34

DS07-13742-2E

MB90980 Series

• Internal shift clock mode

SCK

tSCYC

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 V^CC

0.2 VCC

0.8 VCC

0.2 VCC

• External shift clock mode

SCK

t

SLSH

tSHSL

0.8 VCC

0.2 VCC

t

SLOV

2.4 V

0.8 V

SOT

SIN

t

IVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

DS07-13742-2E

35

MB90980 Series

(5) Extended I/O Serial Interface Timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

name

Parameter

Serial clock cycle time

SCK↓→SOT delay time

Symbol

t^SCYC

Conditions

Unit Remarks

Min

8 t^CP*²

−80

−120

100

200

tCP*²

4 t^CP*²

4 tCP*²

⎯

Max

⎯

ns

+ 80

t^SLOV

Internal shift clock

mode output pins :

C^L*¹= 80 pF + 1 TTL

+ 120 ns f^CP= 8 MHz

⎯

ns

Valid SIN→SCK↑

t^IVSH

⎯

ns f^CP= 8 MHz

SCK↑→valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHIX

t^SHSL

t^SLSH

⎯

ns

⎯

ns

⎯

ns

150

200

⎯

ns

SCK↓→SOT delay time

Valid SIN→SCK↑

t^SLOV

t^IVSH

t^SHIX

⎯

External shift clock

mode output pins :

C^L*¹= 80 pF + 1 TTL

⎯

ns f^CP= 8 MHz

ns

60

120

60

⎯

ns f^CP= 8 MHz

ns

⎯

SCK↑→valid SIN hold time

120

⎯

ns f^CP= 8 MHz

*1 : C^Lis the load capacitance applied to pins for testing.

*2 : t^CPis internal operating clock cycle time. Refer to “ (1) Clock Timing”.

Notes : • AC ratings are for CLK synchronized mode.

• Values on this table are target values.

36

DS07-13742-2E

MB90980 Series

• Internal shift clock mode

SCK

tSCYC

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 V^CC

0.2 VCC

0.8 VCC

0.2 VCC

• External shift clock mode

SCK

t

SLSH

tSHSL

0.8 VCC

0.2 VCC

t

SLOV

2.4 V

0.8 V

SOT

SIN

t

IVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

DS07-13742-2E

37

MB90980 Series

(6) Timer Input Timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Min

Max

TIN0,

IN0, IN1,

PWC0, PWC1

t^TIWH

tTIWL

Input pulse width

⎯

4 t^CP*

⎯

ns

* : t^CPis internal operating clock cycle time. Refer to “ (1) Clock Timing”.

0.8 VCC

0.2 VCC

TIN0

IN0, IN1

0.2 VCC

PWC0, PWC1

tTIWH

tTIWL

(7) Timer Output Timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit Remarks

Min

Max

CLK↑→Tout change time

TOT0,

Load

PPG0 to PPG3 change time

t^TO

PPG0 to PPG3, conditions

OUT0 to OUT3 80 pF

30

⎯

ns

OUT0 to OUT3 change time

0.7 VCC

CLK

0.7 VCC

0.3 VCC

TOUT

PPG0 to PPG3

OUT0 to OUT3

tTO

38

DS07-13742-2E

MB90980 Series

(8) I²C Timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Standard-mode

Parameter

Symbol

Condition

Unit

Min

Max

SCL clock frequency

f^SCL

0

100

kHz

Hold time (repeated) START condition

SDA↓→SCL↓

t^HDSTA

4.0

⎯

µs

When power supply voltage of

external pull-up resistance is 5.5 V

R = 1.3 kΩ, C = 50 pF*²

When power supply voltage of

external pull-up resistance is 3.6 V

R = 1.6 kΩ, C = 50 pF*²

“L” width of the SCL clock

“H” width of the SCL clock

t^LOW

t^HIGH

4.7

4.0

⎯

µs

Set-up time (repeated) START

condition SCL↑→SDA↓

t^SUSTA

t^HDDAT

4.7

0

⎯

µs

Data hold time

SCL↓→SDA↓↑

3.45*³

When power supply voltage of

external pull-up resistance is 5.5 V

f^CP*¹≤ 20 MHz, R = 1.3 kΩ, C = 50 pF*²

When power supply voltage of

external pull-up resistance is 3.6 V

f^CP*¹≤ 20 MHz, R = 1.6 kΩ, C = 50 pF*²

250

200

⎯

ns

Data set-up time

SDA↓↑→SCL↑

t^SUDAT

When power supply voltage of

external pull-up resistance is 5.5 V

f^CP*¹> 20 MHz, R = 1.3 kΩ, C = 50 pF*²

When power supply voltage of

external pull-up resistance is 3.6 V

f^CP*¹> 20 MHz, R = 1.6 kΩ, C = 50 pF*²

Set-up time for STOP condition

SCL↑→SDA↑

When power supply voltage of

external pull-up resistance is 5.5 V

R = 1.3 kΩ, C = 50 pF*²

When power supply voltage of

external pull-up resistance is 3.6 V

R = 1.6 kΩ, C = 50 pF*²

t^SUSTO

4.0

4.7

⎯

µs

Bus free time between a STOP and

START condition

t^BUS

*1 : f^CPis internal operation clock frequency. Refer to “ (1) Clock Timing”.

*2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*3 : The maximum t^HDDATonly has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.

Note : V^CC= VCC3 = VCC5

SDA

t

HDSTA

t

SUDAT

t

BUS

t

LOW

SCL

t

HDSTA

t

HDDAT

t

HIGH

t

SUSTA

tSUSTO

DS07-13742-2E

39

MB90980 Series

(9) Trigger Input Timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Condi-

tions

Parameter

Symbol

Pin name

Unit

Remarks

Min

5 t^CP*

1

Max

⎯

ns

Normal operation

Stop mode

t^TRGH,

t^TRGL

ADTG,

IRQ0 to IRQ7

Input pulse width

⎯

µs

* : t^CPis internal operating clock cycle time. Refer to “ (1) Clock Timing”.

0.8 VCC

0.2 VCC

IRQ0 to IRQ7

ADTG

0.2 VCC

tTRGH

tTRGL

(10) Up-down Counter Timing

(V^CC= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min

Max

⎯

AIN input “H” pulse width

AIN input “L” pulse width

BIN input “H” pulse width

BIN input “L” pulse width

AIN↑→BIN↑ rise time

BIN↑→AIN↓ fall time

AIN↓→BIN↑ rise time

BIN↓→AIN↑ rise time

BIN↑→AIN↑ rise time

AIN↑→BIN↓ fall time

BIN↓→AIN↑ rise time

AIN↓→BIN↑ rise time

ZIN input “H” pulse width

ZIN input “L” pulse width

t^AHL

t^ALL

t^BHL

t^BLL

8 t^CP*

8 tCP*

4 tCP*

4 t^CP*

4 tCP*

ns

t^AUBU

t^BUAD

t^ADBD

t^BDAU

t^BUAU

t^AUBD

t^BDAD

t^ADBU

t^ZHL

AIN0, AIN1,

BIN0, BIN1

Load

conditions

80 pF

ZIN0, ZIN1

t^ZLL

* : t^CPis internal operating clock cycle time. Refer to “ (1) Clock Timing”.

40

DS07-13742-2E

MB90980 Series

tAHL

tALL

0.8 VCC

AIN

0.2 VCC

tBDAU

tAUBU

tBUAD

tADBD

0.8 VCC

BIN

0.2 VCC

tBHL

tBLL

0.8 VCC

BIN

0.2 VCC

tBDAD

0.2 VCC

tBUAU

tAUBD

tADBU

0.8 VCC

AIN

0.2 VCC

0.8 VCC

tZHL

ZIN

tZLL

0.2 VCC

DS07-13742-2E

41

MB90980 Series

5. A/D Converter Electrical Characteristics

(VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH, TA = −40 °C to +85 °C)

Value

Typ

⎯

Parameter

Resolution

Symbol Pin name

Unit

Remarks

Min

⎯

Max

10

⎯

bit

Total error

⎯

3.0

2.5

LSB

Non-linear error

⎯

Differential linearity

error

⎯

1.9

LSB

1 LSB =

(AVRH −

AVSS) /

1024

AN0 to

AN7

AV^SS−

1.5 LSB

AV^SS+

0.5 LSB

AV^SS+

2.5 LSB

Zero transition voltage

V^OT

V

1 LSB =

(AVRH −

AVSS) /

1024

Full scale transition

voltage

AN0 to

AN7

AVRH −

3.5 LSB

AVRH −

1.5 LSB

AVRH +

0.5 LSB

V^FST

V

Conversion time

⎯

3.68 *¹

⎯

µs

Analog port input

current

AN0 to

AN7

I^AIN

⎯

0.1

10

µA

AN0 to

AN7

Analog input voltage

Reference voltage

V^AIN

AV^SS

⎯

AVRH

V

⎯

I^A

AVRH

AVCC

AV^SS+ 2.2

⎯

1.4

⎯

AVCC

3.5

V

⎯

mA

µA

Power supply current

I^AH

I^R

AVCC

5 *²

150

5 *²

AVRH

94

⎯

Reference voltage

supply current

I^RH

Offset between

channels

AN0 to

AN7

⎯

4

LSB

*1 : At machine clock frequency of 25 MHz.

*2 : CPU stop mode current when A/D converter is not operating (at V^CC= AVCC = AVRH = 3.0 V) .

42

DS07-13742-2E

MB90980 Series

• About the external impedance of the analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision.

• Analog input circuit model

R

Analog input

Comparator

C

During sampling : ON

R

C

MB90982

MB90F983

2.5 kΩ (Max) 31.0 pF (Max)

1.9 kΩ (Max) 25.0 pF (Max)

Note: The values are reference values.

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

• The relationship between external impedance and minimum sampling time

(External impedance = 0 kΩ to 100 kΩ)

MB90F983 MB90982

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [µs]

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• About errors

As |AVRH − AV^SS| becomes smaller, values of relative errors grow larger.

Note : Concerning sampling time, and compare time

When 3.6 V ≥ AV^CC≥ 2.7 V, then

Sampling time : 1.92 µs, compare time : 1.1 µs

Settings should ensure that actual values do not go below these values due to operating frequency changes.

DS07-13742-2E

43

MB90980 Series

• Flash Memory Program/Erase Characteristics

Value

Typ

Parameter

Conditions

Unit

Remarks

Min

Max

Excludes 00^Hprogramming

prior erasure

Sector erase time

Chip erase time

⎯

1

7

15

s

T^A= + 25 °C,

V^CC= 3.0 V

Excludes 00^Hprogramming

prior erasure

⎯

Word (16-bit)

programming time

⎯

10000

10

16

⎯

3600

⎯

µs Excludes system-level overhead

cycle

year

Program/Erase cycle

⎯

Flash Memory Data

hold time

Average

T^A= + 85 °C

⎯

*

* : The value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at +85 °C) .

• Use of the X0/X1, X0A/X1A pins

When used with a crystal oscillator

X1

X0

X0A

X1A

Internal

damping

Pull-up

resistance 1

resistance 0

Damping

resistance 1

Damping

resistance 2

In normal use :

C2

C1

C3

C4

Internal damping resistance 1 : Typ 600 kΩ

Consult with the oscillator manufacturer.

Pull-up resistance 1,

Damping resistance 1, 2,

C1 to C4

•Sample use with external clock input

MB90980 series

X0

OPEN

X1

44

DS07-13742-2E

MB90980 Series

■ ORDERING INFORMATION

Model

Package

Remarks

MB90F983PMC1

MB90982PMC1

64-pin plastic LQFP

(FPT-64P-M24)

DS07-13742-2E

45

MB90980 Series

■ PACKAGE DIMENSIONS

64-pin plastic LQFP

Lead pitch

0.50 mm

10.0 × 10.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm MAX

0.32 g

Code

(Reference)

(FPT-64P-M24)

P-LFQFP64-10×10-0.50

64-pin plastic LQFP

(FPT-64P-M24)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

12.00±0.20(.472±.008)SQ

*

10.00±0.10(.394±.004)SQ

0.145±0.055

(.006±.002)

48

33

49

32

Details of "A" part

0.08(.003)

1.50 ⁺^–0⁰^.^.¹²⁰⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

INDEX

0.10±0.10

(.004±.004)

(Stand off)

0˚~8˚

64

17

"A"

0.25(.010)

0.50±0.20

(.020±.008)

1

16

LEAD No.

0.60±0.15

(.024±.006)

0.50(.020)

0.20±0.05

(.008±.002)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2005 FUJITSU LIMITED F64036S-c-1-1

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

46

DS07-13742-2E

MB90980 Series

■ MAIN CHANGES IN THIS EDITION

Page

Section

Change Results

Changed the package.

(FPT-64P-M03 → FPT-64P-M24)

⎯

■ ELECTRICAL CHARACTERISTICS Changed the item of "Zero transition voltage" and "Full-scale

42

5. A/D Converter Electrical

Characteristics

transition voltage".

■ ORDERING INFORMATION

■ PACKAGE DIMENSIONS

Changed the part number;

MB90982 →MB90982PMC1

MB90F983 →MB90F983PMC1

45

46

Changed the figure of package.

FPT-120P-M05 →FPT-120P-M24

The vertical lines marked in the left side of the page show the changes.

DS07-13742-2E

47

MB90980 Series

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0722, Japan

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE LTD.

151 Lorong Chuan, #05-08 New Tech Park,

Singapore 556741

Tel: +65-6281-0770 Fax: +65-6281-0220

http://www.fujitsu.com/sg/services/micro/semiconductor/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm.3102, Bund Center, No.222 Yan An Road(E),

Shanghai 200002, China

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen,

Germany

Tel: +86-21-6335-1560 Fax: +86-21-6335-1605

http://cn.fujitsu.com/fmc/

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road

Tsimshatsui, Kowloon

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

206 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Hong Kong

Tel: +852-2377-0226 Fax: +852-2376-3269

http://cn.fujitsu.com/fmc/tw

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-

ing the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited Business & Media Promotion Dept.


型号：	MB90F983PMC1
厂家：	SPANSION
描述：	Microcontroller, 16-Bit, FLASH, 25MHz, CMOS, PQFP64, 10 X 10 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-64 时钟微控制器外围集成电路
文件：	总49页 (文件大小：1143K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90F983PMC1 [SPANSION]

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