S71VS256RD0AHK3C3 [SPANSION]
Memory Circuit, Flash+PSRAM, CMOS, PBGA56,;
| 型号： | S71VS256RD0AHK3C3 |
| 厂家： | 
SPANSION |
| 描述： | Memory Circuit, Flash+PSRAM, CMOS, PBGA56, 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：794K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S71VS/XS-R Memory Subsystem
Solutions
MirrorBit® 1.8 Volt-Only Simultaneous Read/Write,
Burst Mode Multiplexed Flash Memory and Burst Mode
pSRAM
256/128/64 Mb (16/8/4 Mb x 16-bit) Flash,
128/64/32 Mb (8/4/2 Mb x 16-bit) pSRAM
S71VS/XS-R Memory Subsystem Solutions Cover Sheet
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71VS_XS-R_00
Revision 17
Issue Date October 2, 2012
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
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S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_17 October 2, 2012
S71VS/XS-R Memory Subsystem
Solutions
MirrorBit® 1.8 Volt-Only Simultaneous Read/Write,
Burst Mode Multiplexed Flash Memory and Burst Mode
pSRAM
256/128/64 Mb (16/8/4 Mb x 16-bit) Flash,
128/64/32 Mb (8/4/2 Mb x 16-bit) pSRAM
Data Sheet
Features
Power supply voltage of 1.7V to 1.95V
MCP BGA Packages
– 52 ball, 6.0 x 5.0 mm, 0.5 mm ball pitch
– 56 ball, 7.7 x 6.2 mm, 0.5 mm ball pitch
– 56 ball, 9.2 x 8.0 mm, 0.5 mm ball pitch
Flash / pSRAM Burst Speed: 108 MHz, 104 MHz, 83 MHz
Operating Temperature
– Wireless, –25°C to +85°C
– Industrial, –40°C to +85°C
General Description
The S71VS-R Series is a product line of stacked Multi-Chip Package (MCP) memory solutions and consists of the following
items:
One or more S29VS-R Flash memory die
One or more pSRAM
The products covered by this document are listed in the table below. For details about their specifications, please refer to their
individual data sheet for further details.
Flash Density
64 Mb
pSRAM Density
32 Mb
Product
S71VS064RB0
S71VS128RB0
S71VS128RC0
S71VS256RC0
S71VS256RD0
128 Mb
32 Mb
128 Mb
64 Mb
256 Mb
64 Mb
256 Mb
128 Mb
Publication Number S71VS_XS-R_00
Revision 17
Issue Date October 2, 2012
D a t a S h e e t
For detailed specifications, please refer to the individual data sheets:
Document
Publication Identification Number
S29VS_XS-R_00
S29VS/XS-R
S29VS/XS-R Supplement
S29VS_XS-R_SP
S29VS064R/XS064R
S29VS_XS064R_00
S29VS064R_XS064R_SP
pSRAM_39
S29VS064R/XS064R Supplement
128 Mb MUX pSRAM Type 5
32 Mb CellularRAM Address/Data multiplexed
32 Mb CellularRAM Address/Data multiplexed
64 Mb CellularRAM Address/Data multiplexed
128 Mb CellularRAM Address/Data multiplexed
128 Mb CellularRAM Address/Data multiplexed
SWM032D108M1R
SWM032D108M3R
SWM064D108M1R
SWM128D108M1R
SWM128D108M3R
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D a t a S h e e t
1. Ordering Information
The order number is formed by a valid combinations of the following:
S71VS
256
R
C
0
AH
K
4L
0
Packing Type
0
3
= Tray
= 13-inch Tape and Reel
Model Number
See Valid Combinations table below
Package Modifier
T
K
= 6.0 x 5.0, 52-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter)
7.7 x 6.2, 56-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter)
=
Package Type
AH = Very Thin Fine-Pitch Ball Grid Array (VFRBGA) — 1.0 mm max height with
0.5 mm pitch; Lead (Pb)-free Package; Low-Halogen
Chip Contents
0
= No content (default)
pSRAM Density
B
C
D
= 32 Mb
= 64 Mb
= 128 Mb
Process Technology
= 65 nm MirrorBit Technology
R
Flash Density
256 = 256 Mb
128 = 128 Mb
64 = 64 Mb
Product Family
S71VS = Multi-Chip Product 1.8 Volt-only Simultaneous Read/Write Burst Mode
Address and Data Multiplexed (ADM) Flash Memory + pSRAM
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D a t a S h e e t
1.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Base Ordering
Part Number
Packing
Type
Temperature
Range
Flash /
pSRAM Speed
Pinout and Package
Notes
Package Model Number
pSRAM Type
Flash Boot
0L
8L
3L
BL
Top
Bottom
Top
Pinout: S71VS-R 52-ball
Package: RSE052
Pinout: S71VS-R 52-ball
Package: RLG052
SWM032D108M1R
Wireless
Industrial
Bottom
Top
4L
S71VS064RB0
AHT
CL
108 MHz
Bottom
Top
Pinout: S71VS-R 52-ball
Package: RSE052
0M
8M
3M
BM
0L
Bottom
Top
SWM032D108M3R
SWM032D108M1R
Pinout: S71VS-R 52-ball
Package: RLG052
Bottom
Top
8L
Bottom
Top
Pinout: S71VS-R 56-ball
Package: RLA056
3L
S71VS128RB0
AHK
BL
108 MHz
0, 3
Bottom
Top
4L
Pinout: S71VS-R 56-ball
Package: RSD056
CL
Bottom
Top
4L
Pinout: S71VS-R 56-ball
Package: RSD056
S71VS128RC0
S71VS256RC0
AHK
CL
SWM064D108M1R
SWM064D108M1R
Wireless
108 MHz
108 MHz
108 MHz
Bottom
Top
4L
Pinout: S71VS-R 56-ball
Package: RLA056
AHK
CL
Bottom
Top
3L
BL
3C
Bottom
Top
SWM128D108M1R
83 MHz
108 MHz
Pinout: S71VS-R 56-ball
Package: RSD056
S71VS256RD0
AHK
BC
3M
40
Bottom
Top
SWM128D108M3R
MUX pSRAM Type 5
Industrial
Wireless
Top
108/104 MHz
C0
Bottom
Note:
If a choice exists, Spansion recommends Top Boot.
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D a t a S h e e t
2. Input/Output Descriptions
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
Description
Flash
RAM
X
AMAX – A16
Address inputs.
X
X
A/DQ15-A/DQ0 Multiplexed Address/Data.
X
Address Valid input. Indicates to device that the valid address is present on the address
inputs.
AVD#
CLK
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting
address to be latched.
X
X
X
X
High = device ignores address inputs
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK
increment the internal address counter. Should be at V or V while in asynchronous mode.
IL
IH
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Spansion for test or other purposes and is not intended for
connection to any host system signal. Any DNU signal related function will be inactive when
DNU
the signal is at V . The signal has an internal pull-down resistor and may be left
IL
unconnected in the host system or may be tied to V . Do not use these connections for
SS
PCB signal routing channels. Do not connect any host system signal to these connections.
Output Enable input. Asynchronous relative to CLK for the Burst mode.
OE#
X
X
X
F-CE#
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
Ready output; indicates the status of the Burst read.
Flash Memory RDY (using default “Active HIGH” configuration)
V
V
= data invalid
= data valid
OL
OH
Note: The default polarity for the pSRAM WAIT signal is opposite the default polarity of the
Flash RDY signal.
F-RDY/R-WAIT
X
X
pSRAM WAIT (using default “Active HIGH” configuration)
V
V
= data valid
OL
= data invalid
OH
To match polarities, change bit 10 of the pSRAM Bus Configuration Register to 0 (Active
LOW WAIT). Alternately, change bit 10 of the Flash Configuration Register to 0 (Active LOW
RDY).
F-RST#
Hardware reset input. Low = device resets and returns to reading array data
X
X
Accelerated input. At V , accelerates programming; automatically places device in unlock
HH
F-V
NC
bypass mode. At V , disables all program and erase functions. Should be at V for all other
PP
I
L
I
H
conditions.
Not Connected. No device internal signal is connected to the package connector nor is there
any future plan to use the connector for a signal. The connection may safely be used for
routing space for a signal on a Printed Circuit Board (PCB).
R-CE#
R-CRE
R-LB#
R-UB#
Chip-enable input for pSRAM.
Control Register Enable (pSRAM).
Lower Byte Control (pSRAM).
Upper Byte Control (pSRAM).
X
X
X
X
Reserved For Future Use. No device internal signal is currently connected to the package
connector but there is potential future use for the connector for a signal. It is recommended
to not use RFU connectors for PCB routing channels so that the PCB may take advantage of
future enhanced features in compatible footprint devices.
RFU
V
V
V
V
Flash and pSRAM 1.8 Volt-only single power supply.
Flash and pSRAM Input/Output Power Supply.
Ground.
X
X
X
X
X
X
X
X
X
X
CC
CCQ
SS
Input/Output Ground.
SSQ
WE#
Write Enable input.
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D a t a S h e e t
3. MCP Block Diagram
Figure 3.1 S71VS-R MCP Block Diagram
F-RST#
RST#
A/DQ15-A/DQ0
CLK
ADQ15-ADQ0
CLK
F-VPP
F-RDY/R-WAIT
F-CE#
VPP
RDY
CE#
OE#
WE#
AVD#
MUX
FLASH
MEMORY
VS-R
OE#
WE#
AVD#
Amax-A16
Amax-A16
VCC
VCC
VSS, VSSQ
VSS
VCCQ
VCCQ
VSSQ
R-UB#
R-LB#
R-CE#
UB#
LB#
A/DQ15-A/DQ0
CLK
MUX
pSRAM
MEMORY
CE#
OE#
WE#
ADV#
VSS
Amax-A16
VCC
VCCQ
VSSQ
WAIT
CRE
R-CRE
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D a t a S h e e t
4. Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71VS-R.
4.1
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
4.2
Connection Diagrams
Figure 4.1 S71VS-R 56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Legend
A
B
C
D
E
F
NC
NC
Not Connected
Do Not Use
NC
RFU
A21
A16
R-LB# R-UB#
RFU
A17
NC
A22
VSS
OE#
Reserved for Future Use
Flash/RAM Shared
F-RDY/
R-WAIT
VSS
CLK
VCC
WE#
F-VPP
A19
VCCQ
A20
AVD#
A23 F-RST# RFU
A18
F-CE#
Flash Only
VSS
A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8
G
A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0
RAM Only
H
J
NC
RFU
R-CE# R-CRE
RFU
NC
K
NC
NC
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D a t a S h e e t
Figure 4.2 S71VS-R 52-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
Legend
1
2
3
4
5
6
7
8
9
10
NC
A
B
C
D
E
F
NC
RFU
A21
R-LB#
VCC
RFU
R-UB#
WE#
RFU
Not Connected
Do Not Use
F-RDY/
R-WAIT
VSS
CLK
F-VPP
RFU
A19
A18
A17
RFU
VSS
OE#
ADQ0
NC
VCCQ
A16
A20
AVD#
F-RST#
F-CE#
ADQ8
ADQ1
RFU
Reserved for Future Use
Flash/RAM Shared
Flash Only
VSS
ADQ7
ADQ6 ADQ13 ADQ12 ADQ3
ADQ2
ADQ9
ADQ15 ADQ14
VSS
ADQ5
ADQ4 ADQ11 ADQ10 VCCQ
R-CE# R-CRE
NC
RFU
RAM Only
Notes:
1. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
2. and V must be connected together.
V
SS
SSQ
MCP
Flash-Only Addresses
Shared Addresses
A20-A16
Shared ADQ Pins
S71VS064RB0
S71VS128RB0
S71VS128RC0
S71VS256RC0
S71VS256RD0
A21
A22-A21
A22
A20-A16
A21-A16
A/DQ15-A/DQ0
A23-A22
A23
A21-A16
A22-A16
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D a t a S h e e t
4.3
Physical Dimensions
Figure 4.3 RLG052 - 52-ball VFRBGA 6.0 x 5.0 mm
NOTES:
PACKAGE
JEDEC
RLG 052
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
N/A
6.00 mm x 5.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL
MIN
NOM
---
MAX
NOTE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
A
A1
D
---
1.00
---
PROFILE
0.18
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
6.00 BSC.
5.00 BSC.
4.50 BSC.
2.50 BSC.
10
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME
E
BODY SIZE
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
6
52
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
ꢀb
0.25
0.30
0.35
BALL DIAMETER
e
0.50 BSC.
0.25 BSC.
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SE / SD
SOLDER BALL PLACEMENT
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3A,3F,4A,4F,7A,7F,8A,8F DEPOPULATED SOLDER BALLS
g1002-1 \ f16-038.63 \ 08.25.10
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D a t a S h e e t
Figure 4.4 RLA056 - 56-ball VFRBGA 7.7 x 6.2 mm
NOTES:
PACKAGE
JEDEC
RLA 056
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D X E
7.70 mm x 6.20 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL
MIN
NOM
---
MAX
NOTE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
A
A1
A2
D
---
1.00
---
PROFILE
0.18
0.62
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
---
0.74
BODY THICKNESS
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X E
7.70 BSC.
6.20 BSC.
6.50 BSC.
4.50 BSC.
14
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
10
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
56
b
0.25
0.30
0.35
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
eE
eD
SE SD
0.50 BSC.
0.50 BSC.
0.25 BSC.
BALL PITCH
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
BALL PITCH
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
g1007 \ f16-038.63 \ 08.18.10
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D a t a S h e e t
Figure 4.5 RSD056—56-ball VFRBGA 7.7 x 6.2 mm
NOTES:
PACKAGE
JEDEC
RSD 056
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
7.70 mm x 6.20 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
SPP-010.
SYMBOL
MIN
NOM
0.90
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
0.80
0.18
0.62
1.00
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
---
BALL HEIGHT
A2
---
0.74
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
D
7.70 BSC
6.20 BSC
6.50 BSC
4.50 BSC
14
E
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MD
ME
n
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
10
56
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Øb
eE
0.25
0.30
0.35
BALL DIAMETER
0.50 BSC
0.50 BSC
0.25 BSC
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eD
SE SD
BALL PITCH
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3719 \ f16-038.63 \ 1.26.9
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D a t a S h e e t
Figure 4.6 RSE052—52-ball VFRBGA 6.0 x 5.0 mm
NOTES:
PACKAGE
JEDEC
RSE 052
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D X E
6.00 mm x 5.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL
MIN
NOM
---
MAX
NOTE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
A
A1
D
---
1.00
---
PROFILE
0.18
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
6.00 BSC.
5.00 BSC.
4.50 BSC.
2.50 BSC.
10
BODY SIZE
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME
E
BODY SIZE
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
6
52
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
b
0.25
0.30
0.35
BALL DIAMETER
e
0.50 BSC.
0.25 BSC.
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SE / SD
SOLDER BALL PLACEMENT
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3A,3F,4A,4F,7A,7F,8A,8F DEPOPULATED SOLDER BALLS
g1004-1 \ f16-038.63 \ 08.25.10
14
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_17 October 2, 2012
D a t a S h e e t
5. Revision History
Section
Description
Revision 01 (August 25, 2008)
Initial release
Revision 02 (November 4, 2008)
Global
Added OPNs S71VS064RB0AHT00/04/80/84
Added S71VS-R 52-ball connection diagram
Added RSB052
Connection Diagrams
Physical Dimensions
General Description
Changed 128 Mb Mux pSRAM PID from TBD to pSRAM_39
Revision 03 (November 10, 2008)
General Description
Changed 64 Mb MUX pSRAM Type 3 PID from muxpsram_14 to muxpsram_15
Replaced NLD056 with NSD056
Revision 04 (January 13, 2009)
Physical Dimensions
Revision 05 (January 23, 2009)
Valid Combinations
Added OPN S71VS128RC0AHK20
Added RSD056
Physical Dimensions
Revision 06 (March 11, 2009)
Valid Combinations
Added 108 MHz speed grade to S71VS128RC0 and S71VS256RC0
Revision 07 (September 29, 2009)
General Description
Added S71VS128RB0; added muxpsram_10
Added OPN S71VS128RB0
Valid Combinations
Revision 08 (April 9, 2010)
Added SWM064D108M1R
General Description
Valid Combinations
Updated pSRAM documentation names
Added OPNs:
S71VS128RC0AHK4L
S71VS256RC0AHK4L
Removed Bottom Boot options
Updated VSSQ ball to VSS
Connection Diagrams
Revision 09 (May 4, 2010)
Added reference to S29VS064R data sheet
General Description
Removed CustComspec_01 for 32 Mb MUX pSRAM
Corrected pSRAM type for S71VS064RB0 from CustComspec_01 to SWM032D108M1R
Added OPNs:
Valid Combinations
S71VS064RB0AHT0L
S71VS256RD0AHK40
Revision 10 (June 14, 2010)
General Description
Removed S71XS256RD0 from table
Unified data sheet reference for S29VS/XS-R
Removed MUX pSRAM Type 3
Added SWM128D108M1R
Restored necessary bottom boot options.
Added OPNs: S71VS256RD0AHK3L/BL/3C/BC
Removed OPNs: S71VS064RB0AHT00/04
Updated MUX pSRAM Type 3 entries to the Common RAM type specifications
Removed table after Figure 4.3 S71XS-R 56-ball Fine-Pitch Ball Grid Array
Valid Combinations
October 2, 2012 S71VS_XS-R_00_17
S71VS/XS-R Memory Subsystem Solutions
15
D a t a S h e e t
Section
Revision 11 (July 28, 2010)
Features
Description
Corrected MCP BGA Packages information
Corrected Package Modifier information
Removed 7 inch Tape and Reel option
Ordering Information
Corrected package information for S71VS064RB0AHT0L
Added OPN S71VS064RB0AHT8L, S71VS128RC0AHKCL, S71VS256RC0AHKCL
Removed OPN S71VS256RD0AHK40
Valid Combinations
MCP Block Diagram
Removed figure S71XS-R MCP Block Diagram
Corrected figure S71VS-R 52-ball Fine-Pitch Ball Grid Array
Removed figure S71XS-R 56-ball Fine-Pitch Ball Grid Array
Connection Diagrams/Physical
Dimensions
Replaced figure RSB052—52-ball VFBGA 5.0 x 7.5 mm
with RSE052—52-ball VFRBGA 6.0 x 5.0 mm
Refreshed DNU/RFU/NC definitions
Revision 12 (August 27, 2010)
Corrected package information for S71VS128RB0AHK0L/8L (RLA056)
Corrected speed for OPNs S71VS256RD0AHK3L/BL to 108 MHz
Valid Combinations
Connection Diagrams
Physical Dimensions
Revision 13 (December 9, 2010)
Features
Reverted DNU balls to RFU
Added diagram for RLA056
Added Industrial temperature
Added references to S29VS_XS-R_SP, S29VS064R_XS064R_SP, SWM032D108M3R,
SWM128D108M3R
General Description
Added OPNs S71VS064RB0AHT3L/BL/0M/8M, S71VS128RB0AHK3L/BL, S71VS256RD0AHK3M,
S71VS256RD0AHK40/C0
Valid Combinations
Added Temperature Range Column
Revision 14 (April 13, 2011)
General Description
Removed SWM032D108M1N and SWM064D108M1N references
Removed OPNs S71VS064RB0AHT3M/BM, S71VS128RB0AHK2L/AL, S71VS128RC0AHK20,
S71VS128RC0ZHKxx, S71VS256RC0ZHKxx, S71VS256RD0ZHExx
Valid Combinations
Physical Dimensions: Removed NLB056 and NSD056 diagrams. Added diagram for RLG052
Added OPNs S71VS128RB0AHK4L/CL, , S71VS064RB0AHT4L/CL
Added OPNs S71VS064RB0AHT3M/BM
Revision 15 (June 20, 2011)
Valid Combinations
Revision 16 (June 29, 2012)
Valid Combinations
Revision 17 (October 2, 2012)
Valid Combinations
Updated the S71VS256RC0AHK4L/CL package from RSD056 to RLA056
16
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_17 October 2, 2012
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
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the prior authorization by the respective government entity will be required for export of those products.
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The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
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merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
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Copyright © 2008-2012 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and
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are for informational purposes only and may be trademarks of their respective owners.
October 2, 2012 S71VS_XS-R_00_17
S71VS/XS-R Memory Subsystem Solutions
17
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