S71WS128JB0BAIAA0 [SPANSION]
Memory Circuit, 8MX16, CMOS, PBGA84, 8 X 11.60 MM, 1.20 MM HEIGHT, FBGA-84;型号: | S71WS128JB0BAIAA0 |
厂家: | SPANSION |
描述: | Memory Circuit, 8MX16, CMOS, PBGA84, 8 X 11.60 MM, 1.20 MM HEIGHT, FBGA-84 |
文件: | 总183页 (文件大小:4594K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
S71WSxxxJ based MCPs
Stacked Multi-Chip Product (MCP)
128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory
with CellularRAM
PRELIMINARY
Distinctive Characteristics
Packages
— 8 x 11.6mm, 84 ball FBGA
MCP Features
Power supply voltage of 1.7 to 1.95V
Operating Temperature
— –25°C to +85°C
Speed: 66MHz
— –40°C to +85°C
General Description
The S71WS series is a product line of stacked Multi-Chip Product (MCP) packages
and consists of:
One or more flash memory die
CellularRAM-compatible pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheets for
further details:
Flash Memory Density
256Mb
128Mb
64Mb
64Mb
32Mb
16Mb
S71WS256JC0
S71WS128JC0
S71WS128JB0
S71WS128JA0
pSRAM
Density
S71WS064JB0
S71WS064JA0
Publication Number S71WS256/128/064J_00 Revision A Amendment 0 Issue Date November 10, 2004
P r e l i m i n a r y
Product Selector Guide
Flash Speed pSRAM Speed
Device-Model#
Flash Density pSRAM Density
(MHz)
(MHz/ns)
Supplier
Package
S71WS064JA0-2A
S71WS064JB0-26
S71WS064JB0-2A
S71WS128JA0-AA
S71WS128JB0-AA
S71WS128JC0-AA
S71WS128JC0-A6
S71WS256JC0-TA
S71WS256JC0-T6
16Mb
CellularRAM Type 2
Cellular RAM Type 1
Cellular RAM Type 2
Cellular RAM Type 2
Cellular RAM Type 2
Cellular RAM Type 2
Cellular RAM Type 1
Cellular RAM Type 2
Cellular RAM Type 1
64Mb
TLC080
32Mb
16Mb
32Mb
66
66/70
128Mb
256Mb
TLA084
FTA084
64Mb
2
S71WSxxxJ based MCPs
S71WS256/128/064J_00_A0 November 10, 2004
P r e l i m i n a r y
Figure 1. Temporary Sector Unprotect Operation ................... 39
Figure 2. In-System Sector Protection/Sector Unprotection
Algorithms........................................................................ 40
Table 7. SecSi™ Sector Addresses ...................................... 41
SecSi™ Sector Protection Bit ......................................................................42
Hardware Data Protection .........................................................................42
S71WSxxxJ based MCPs
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
Connection Diagram (CellularRAM Type-based) .7
Special Handling Instructions For FBGA Package ...................................8
Lookahead Connection Diagram . . . . . . . . . . . . . .9
Input/Output Descriptions . . . . . . . . . . . . . . . . . . 10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 11
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 14
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA)
Write Protect (WP#) .......................................................................................42
Low V Write Inhibit ................................................................................. 43
CC
Write Pulse “Glitch” Protection ...............................................................43
Logical Inhibit ...................................................................................................43
Power-Up Write Inhibit ...............................................................................43
Common Flash Memory Interface (CFI) . . . . . . .44
Table 8. CFI Query Identification String ................................ 44
Table 9. System Interface String ......................................... 45
Table 10. Device Geometry Definition................................... 45
Table 11. Primary Vendor-Specific Extended Query ................ 46
Table 12. WS128J Sector Address Table ............................... 47
Table 13. WS064J Sector Address Table ............................... 55
8 x 11.6 mm Package ........................................................................................... 14
FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ............................................................................................15
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 61
Reading Array Data ............................................................................................61
Set Configuration Register Command Sequence ......................................61
Figure 3. Synchronous/Asynchronous State Diagram.............. 62
Read Mode Setting .........................................................................................62
Programmable Wait State Configuration ...............................................62
Table 14. Programmable Wait State Settings ......................... 63
Standard wait-state Handshaking Option ...............................................63
Table 15. Wait States for Standard wait-state Handshaking .... 63
Read Mode Configuration ...........................................................................63
Table 16. Read Mode Settings ............................................. 64
Burst Active Clock Edge Configuration ..................................................64
RDY Configuration ........................................................................................64
Table 17. Configuration Register .......................................... 65
Reset Command .................................................................................................65
Autoselect Command Sequence ....................................................................65
Enter SecSi™ Sector/Exit SecSi™ Sector Command Sequence .............66
Program Command Sequence ........................................................................67
Unlock Bypass Command Sequence ........................................................67
Figure 4. Program Operation............................................... 68
Chip Erase Command Sequence ...................................................................68
Sector Erase Command Sequence ................................................................69
Erase Suspend/Erase Resume Commands ..................................................70
Figure 5. Erase Operation................................................... 71
Password Program Command ........................................................................71
Password Verify Command ..............................................................................71
Password Protection Mode Locking Bit Program Command ..............72
Persistent Sector Protection Mode Locking Bit Program Command 72
SecSi™ Sector Protection Bit Program Command ................................... 72
PPB Lock Bit Set Command ............................................................................72
DPB Write/Erase/Status Command ............................................................. 73
Password Unlock Command .......................................................................... 73
PPB Program Command .................................................................................. 73
All PPB Erase Command ..................................................................................74
PPB Status Command .......................................................................................74
PPB Lock Bit Status Command ......................................................................74
Command Definitions ....................................................................................... 75
Table 18. Command Definitions .......................................... 75
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 78
DQ7: Data# Polling ............................................................................................78
Figure 6. Data# Polling Algorithm........................................ 79
DQ6: Toggle Bit I ...............................................................................................80
Figure 7. Toggle Bit Algorithm............................................. 81
DQ2: Toggle Bit II ...............................................................................................81
S29WS128/064J
General Description . . . . . . . . . . . . . . . . . . . . . . . . 18
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .20
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .22
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .24
Table 1. Device Bus Operations .......................................... 24
VersatileIO™ (V ) Control ............................................................................ 24
IO
Requirements for Asynchronous Read Operation (Non-Burst) ......... 24
Requirements for Synchronous (Burst) Read Operation .......................25
8-, 16-, and 32-Word Linear Burst with Wrap Around ..................... 26
Table 2. Burst Address Groups ............................................ 26
Configuration Register ..................................................................................... 26
Handshaking ......................................................................................................... 26
Simultaneous Read/Write Operations with Zero Latency ....................27
Writing Commands/Command Sequences .................................................27
Accelerated Program Operation ...................................................................27
Autoselect Mode ................................................................................................ 28
Table 3. Autoselect Codes (High Voltage Method) ................. 29
Sector/Sector Block Protection and Unprotection ................................. 29
Table 4. S29WS128/064J_MCP Boot Sector/Sector Block Addresses
for Protection/Unprotection ................................................. 29
Table 5. S29WS064J Boot Sector/Sector Block Addresses for
Protection/Unprotection ..................................................... 31
Sector Protection ...........................................................................................33
Persistent Sector Protection ...........................................................................33
Persistent Protection Bit (PPB) ..................................................................34
Persistent Protection Bit Lock (PPB Lock) .............................................34
Dynamic Protection Bit (DYB) ...................................................................34
Table 6. Sector Protection Schemes ..................................... 35
Persistent Sector Protection Mode Locking Bit ........................................36
Password Protection Mode .............................................................................36
Password and Password Mode Locking Bit ................................................36
64-bit Password ...................................................................................................37
Persistent Protection Bit Lock ........................................................................37
Standby Mode .......................................................................................................37
Automatic Sleep Mode ......................................................................................38
RESET#: Hardware Reset Input .................................................................38
Output Disable Mode ....................................................................................39
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Table 19. DQ6 and DQ2 Indications ..................................... 82
Reading Toggle Bits DQ6/DQ2 ..................................................................... 82
DQ5: Exceeded Timing Limits ........................................................................83
DQ3: Sector Erase Timer .................................................................................83
Table 20. Write Operation Status ......................................... 84
General Description . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 38. Functional Block Diagram .................................. 115
Table 22. Signal Descriptions ............................................ 116
Table 23. Bus Operations—Asynchronous Mode ................... 117
Table 24. Bus Operations—Burst Mode ............................... 118
Functional Description . . . . . . . . . . . . . . . . . . . . . 118
Power-Up Initialization .....................................................................................118
Figure 39. Power-Up Initialization Timing............................ 119
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . 119
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .85
Figure 8. Maximum Negative Overshoot Waveform................. 85
Figure 9. Maximum Positive Overshoot Waveform .................. 85
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 86
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .87
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Figure 10. Test Setup ......................................................... 88
Table 21. Test Specifications ............................................... 88
Asynchronous Mode .........................................................................................119
Figure 40. READ Operation (ADV# LOW) ............................ 119
Figure 41. WRITE Operation (ADV# LOW)........................... 120
Page Mode READ Operation ........................................................................120
Figure 42. Page Mode READ Operation (ADV# LOW) ............ 121
Burst Mode Operation .....................................................................................121
Figure 43. Burst Mode READ (4-word burst)........................ 122
Figure 44. Burst Mode WRITE (4-word burst) ...................... 122
Mixed-Mode Operation ...................................................................................123
WAIT Operation ...............................................................................................123
Figure 45. Wired or WAIT Configuration.............................. 123
LB#/UB# Operation .........................................................................................124
Figure 46. Refresh Collision During READ Operation............. 124
Figure 47. Refresh Collision During WRITE Operation............ 125
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . 125
Standby Mode Operation ................................................................................125
Temperature Compensated Refresh ...........................................................125
Partial Array Refresh ........................................................................................126
Deep Power-Down Operation .....................................................................126
Configuration Registers . . . . . . . . . . . . . . . . . . . . 126
Access Using CRE .............................................................................................126
Figure 48. Configuration Register WRITE, Asynchronous Mode
Followed by READ............................................................ 127
Figure 49. Configuration Register WRITE, Synchronous Mode
Followed by READ0.......................................................... 128
Bus Configuration Register .............................................................................128
Table 25. Bus Configuration Register Definition .................... 129
Table 26. Sequence and Burst Length ................................ 130
Burst Length (BCR[2:0]): Default = Continuous Burst .....................130
Burst Wrap (BCR[3]): Default = No Wrap ..........................................130
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength .............................................................................................................131
Table 27. Output Impedance ............................................. 131
WAIT Configuration (BCR[8]): Default = WAIT Transitions One
Clock Before Data Valid/Invalid .................................................................131
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH ................131
Figure 50. WAIT Configuration (BCR[8] = 0)....................... 131
Figure 51. WAIT Configuration (BCR[8] = 1)....................... 132
Figure 52. WAIT Configuration During Burst Operation ......... 132
Latency Counter (BCR[13:11]): Default = Three-Clock Latency .....132
Table 28. Variable Latency Configuration Codes ................... 132
Figure 53. Latency Counter (Variable Initial Latency, No Refresh
Collision)........................................................................ 133
Operating Mode (BCR[15]): Default = Asynchronous Operation . 133
Refresh Configuration Register .....................................................................133
Table 29. Refresh Configuration Register Mapping ................ 134
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh ....134
Table 30. 128Mb Address Patterns for PAR (RCR[4] = 1) ...... 134
Table 31. 64Mb Address Patterns for PAR (RCR[4] = 1) ........ 135
Table 32. 32Mb Address Patterns for PAR (RCR[4] = 1) ........ 135
Deep Power-Down (RCR[4]): Default = DPD Disabled ..................135
Key to Switching Waveforms . . . . . . . . . . . . . . . 88
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 88
Figure 11. Input Waveforms and Measurement Levels............. 88
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .89
V
Power-up .....................................................................................................89
CC
Figure 12. VCC Power-up Diagram ........................................ 89
CLK Characterization .......................................................................................89
Figure 13. CLK Characterization ........................................... 89
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .90
Synchronous/Burst Read @ V = 1.8 V .....................................................90
IO
Figure 14. CLK Synchronous Burst Mode Read (rising active CLK).
91
Figure 15. CLK Synchronous Burst Mode Read (Falling Active Clock)
91
Figure 16. Synchronous Burst Mode Read.............................. 92
Figure 17. 8-word Linear Burst with Wrap Around................... 92
Figure 18. Linear Burst with RDY Set One Cycle Before Data.... 93
Asynchronous Mode Read @ V = 1.8 V ................................................. 94
IO
Figure 19. Asynchronous Mode Read with Latched Addresses... 95
Figure 20. Asynchronous Mode Read..................................... 95
Figure 21. Reset Timings..................................................... 96
Erase/Program Operations @ V = 1.8 V ..................................................97
IO
Figure 22. Asynchronous Program Operation Timings: AVD#
Latched Addresses ............................................................. 98
Figure 23. Asynchronous Program Operation Timings: WE#
Latched Addresses ............................................................. 99
Figure 24. Synchronous Program Operation Timings: WE# Latched
Addresses ....................................................................... 100
Figure 25. Synchronous Program Operation Timings: CLK Latched
Addresses ....................................................................... 101
Figure 26. Chip/Sector Erase Command Sequence................ 102
Figure 27. Accelerated Unlock Bypass Programming Timing ... 103
Figure 28. Data# Polling Timings (During Embedded Algorithm)...
104
Figure 29. Toggle Bit Timings (During Embedded Algorithm).. 104
Figure 30. Synchronous Data Polling
Timings/Toggle Bit Timings................................................ 105
Figure 31. DQ2 vs. DQ6.................................................... 105
Temporary Sector Unprotect .......................................................................106
Figure 32. Temporary Sector Unprotect Timing Diagram........ 106
Figure 33. Sector/Sector Block Protect and Unprotect Timing
Diagram.......................................................................... 107
Figure 34. Latency with Boundary Crossing.......................... 108
Figure 35. Latency with Boundary Crossing into Program/Erase
Bank .............................................................................. 109
Figure 36. Example of Wait States Insertion ........................ 110
Figure 37. Back-to-Back Read/Write Cycle Timings............... 111
Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation ........................................................................................................135
CellularRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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S71WS256/128/064J_00_A0 November 10, 2004
P r e l i m i n a r y
Table 55. Burst WRITE Timing Parameters .......................... 167
Figure 70. Continuous Burst WRITE Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition................................. 168
Table 56. Burst WRITE Timing Parameters—BCR[8] = 0 ....... 168
Figure 71. Burst WRITE Followed by Burst READ.................. 169
Table 57. WRITE Timing Parameters—Burst WRITE Followed by
Burst READ ..................................................................... 169
Table 58. READ Timing Parameters—Burst WRITE Followed by
Burst READ ..................................................................... 169
Figure 72. Asynchronous WRITE Followed by Burst READ...... 170
Table 59. WRITE Timing Parameters—Asynchronous WRITE
Followed by Burst READ ................................................... 171
Table 60. READ Timing Parameters—Asynchronous WRITE
Followed by Burst READ ................................................... 171
Figure 73. Asynchronous WRITE (ADV# LOW) Followed By Burst
READ............................................................................. 172
Table 61. Asynchronous WRITE Timing
Parameters—ADV# LOW .................................................. 172
Table 62. Burst READ Timing Parameters ............................ 173
Figure 74. Burst READ Followed by Asynchronous WRITE (WE#-
Controlled) ..................................................................... 174
Table 63. Burst READ Timing Parameters ............................ 175
Table 64. Asynchronous WRITE Timing Parameters—WE#
Controlled ....................................................................... 175
Figure 75. Burst READ Followed by Asynchronous WRITE Using
ADV#............................................................................. 176
Table 65. Burst READ Timing Parameters ............................ 177
Table 66. Asynchronous WRITE Timing Parameters
Page Mode Operation (RCR[7]): Default = Disabled .........................135
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 136
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 137
Table 33. Electrical Characteristics and Operating Conditions .137
Table 34. Temperature Compensated Refresh Specifications and
Conditions .......................................................................138
Table 35. Partial Array Refresh Specifications and Conditions .138
Table 36. Deep Power-Down Specifications ..........................138
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 54. AC Input/Output Reference Waveform ................. 139
Figure 55. Output Load Circuit ........................................... 139
Table 37. Output Load Circuit ............................................139
Table 38. Asynchronous READ Cycle Timing Requirements .....140
Table 39. Burst READ Cycle Timing Requirements .................141
Table 40. Asynchronous WRITE Cycle Timing Requirements ...142
Table 41. Burst WRITE Cycle Timing Requirements ...............142
Timing Diagrams ................................................................................................ 143
Figure 56. Initialization Period............................................ 143
Table 42. Initialization Timing Parameters ...........................143
Figure 57. Asynchronous READ .......................................... 144
Table 43. Asynchronous READ Timing Parameters ................144
Figure 58. Asynchronous READ Using ADV# ........................ 146
Table 44. Asynchronous READ Timing
Parameters Using ADV# ....................................................146
Figure 59. Page Mode READ............................................... 148
Table 45. Asynchronous READ Timing Parameters—Page Mode
Operation ........................................................................148
Figure 60. Single-Access Burst READ
Operation—Variable Latency.............................................. 150
Table 46. Burst READ Timing Parameters—Single Access, Variable
Latency ...........................................................................150
Figure 61. Four-word Burst READ
Operation—Variable Latency.............................................. 152
Table 47. Burst READ Timing Parameters—4-word Burst .......153
Figure 62. Four-word Burst READ Operation (with LB#/UB#). 154
Table 48. Burst READ Timing Parameters—4-word Burst with LB#/
UB# ...............................................................................155
Figure 63. READ Burst Suspend ......................................... 156
Table 49. Burst READ Timing Parameters—Burst Suspend .....156
Figure 64. Continuous Burst READ Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition ................................. 157
Table 50. Burst READ Timing Parameters—BCR[8] = 0 ..........157
Figure 65. CE#-Controlled Asynchronous WRITE .................. 158
Table 51. Asynchronous WRITE Timing Parameters—CE#-
Controlled .......................................................................158
Figure 66. LB#/UB#-Controlled Asynchronous WRITE........... 160
Table 52. Asynchronous WRITE Timing Parameters—LB#/UB#-
Controlled .......................................................................160
Figure 67. WE#-Controlled Asynchronous WRITE.................. 162
Table 53. Asynchronous WRITE Timing Parameters—WE#-
Controlled .......................................................................162
Figure 68. Asynchronous WRITE Using ADV#....................... 164
Table 54. Asynchronous WRITE Timing
Using ADV# .................................................................... 177
Figure 76. Asynchronous WRITE Followed by Asynchronous READ—
ADV# LOW..................................................................... 178
Table 67. WRITE Timing Parameters—ADV# LOW ................ 178
Table 68. READ Timing Parameters—ADV# LOW .................. 179
Figure 77. Asynchronous WRITE Followed by
Asynchronous READ......................................................... 180
Table 69. WRITE Timing Parameters—Asynchronous WRITE
Followed by Asynchronous READ ....................................... 180
Table 70. READ Timing Parameters—Asynchronous WRITE
Followed by Asynchronous READ ....................................... 181
How Extended Timings Impact CellularRAM™
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Introduction .........................................................................................................181
Asynchronous WRITE Operation ................................................................182
Figure 78. Extended Timing for tCEM.............................................. 182
Figure 79. Extended Timing for tTM................................................ 182
Table 71. Extended Cycle Impact on READ and WRITE Cycles 182
Extended WRITE Timing— Asynchronous WRITE Operation .....182
Figure 80. Extended WRITE Operation................................ 183
Page Mode READ Operation ........................................................................183
Burst-Mode Operation ....................................................................................183
Summary ...............................................................................................................183
Revision Summary
Parameters Using ADV# ....................................................165
Figure 69. Burst WRITE Operation...................................... 166
November 10, 2004 S71WS256/128/064J_00_A0
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MCP Block Diagram
F-VCC
Flash-only Address
Shared Address
V
V
ID
CC
DQ15 to DQ0
CLK
WP#
A22
16
DQ15 to DQ0
CLK
F-WP#
F-ACC
(Note 4) F1-CE#
OE#
ACC
CE#
OE#
WE#
Flash 1
Flash 2
(Note 3)
WE#
F-RST#
AVD#
RESET#
AVD#
RDY
RDY
(Note 4) F2-CE#
R-VCC
V
SS
A22
V
V
CCQ
CC
WAIT#
(Note 4)
CLK
16
R-CE#1
CE#
WE#
OE#
UB#
LB#
I/O15 to I/O0
pSRAM
R-UB#
R-LB#
V
SSQ
(Note 4)
AVD#
CRE
(Note 1) R-CRE
Notes:
1. R-CRE is only present in CellularRAM-compatible pSRAM.
2. For 1 Flash + pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for
the second Flash.
3. Only needed for S71WS256JC0.
4. CLK and AVD# not applicable for 16Mb pSRAM, as burst features are not yet supported at that RAM density.
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Connection Diagram (CellularRAM Type-based)
84-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
A10
DNU
DNU
B2
B3
B4
B5
B6
B7
B8
B9
AVD#
DNU
CLK
DNU
DNU
DNU
DNU
DNU
Legend
C2
C3
A7
C4
LB#
D4
C5
ACC
D5
C6
WE#
D6
C7
A8
C8
A11
D9
C9
DNU
D10
A15
E9
WP#
D2
D3
D7
1st Flash only
1st RAM only
Do Not Use
A3
A6
UB#
E4
RST#
E5
DNU
E6
A19
E7
A12
E8
E2
A2
E3
A5
A18
F4
RDY
H5
A20
H6
A9
A13
F8
A21
F9
F2
F3
F7
DNU
DNU
A1
A4
A17
G4
A10
G7
A14
G8
A22
G9
G2
G3
VSS
H3
H5
DNU
H5
H6
DNU
H6
A0
DQ1
H4
DQ6
H7
DNU
H8
A16
Flash/RAM Shared
H2
H9
CREs
J9
CE1#f
J2
OE#
J3
DQ9
J4
DQ3
J5
DQ4
J6
DQ13
J7
DQ15
J8
CE1#s
K2
DQ0
K3
DQ10
K4
VCCf
K5
VCCs
K6
DQ12
K7
DQ7
K8
VSS
K9
DNU
DQ8
DQ2
DQ11
DNU
DQ5
DQ14
DNU
L5
L2
L3
L4
L6
L7
L8
L9
DNU
DNU
DNU
VCCf
DNU
DNU
DNU
DNU
M1
M10
DNU
DNU
Notes:
1. In MCPs based on a single S29WSxxxJ (S71WSxxxJ), ball B5 is RFU. In MCPs based on two S29WSxxxJ
(S71WS256J), ball B5 is F2-CE#.
2. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP
Flash-only Addresses
Shared Addresses
A19-A0
S71WS064JA0
S71WS064JB0
S71WS128JA0
S71WS128JB0
S71WS128JC0
S71WS256JC0
A21-A20
A21
A20-A0
A22-A20
A22-A21
A22
A19-A0
A19-A0
A21-A0
A22
A21-A0
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Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultra-
sonic cleaning methods. The package and/or data integrity may be compromised
if the package body is exposed to temperatures above 150°C for prolonged peri-
ods of time.
November 10, 2004 S71WS256/128/064J_00_A0
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Lookahead Connection Diagram
Legend:
A2
A1
A10
A9
DNU
DNU
DNU
DNU
DNU
(Do Not Use)
B1
B9
B2
B10
DNU
DNU
DNU
DNU
Code Flash Only
pSRAM Only
C4
C5
C6
C7
C8
C9
C2
C3
AVD#
VSS
CLK
F2-CE#
F-VCC
F-CLK#
R-OE# F2-OE#
D4
D2
D3
A7
D5
D6
D7
A8
D8
D9
D-DM0/
D1, D#
See Table
See Table WE#
E5 E6
F-RST# R1-CE2
A11
F3-CE#
E2
A3
E3
A6
E4
E7
E8
E9
Flash/xRAM
Shared
D-DM1/
D11, D#
A19
A12
A15
F2
A2
F3
A5
F4
F5
F6
F7
A9
F8
F9
A18 See Table
A20
A13
A21
MirrorBit Data
Only
G6
G8
G9
G2
A1
G4
G7
G3
A4
G5
A17
R2-CE1
A23
A10
A14
A22
xRAM Shared
H2
A0
H3
H4
H5
H6
H7
H8
H9
VSS
DQ1
R2-VCC R2-CE2
DQ6
A24
A16
Flash/Data
Shared
J2
J3
J4
J5
J6
J7
J8
J9
DQ9
DQ3
DQ4
DQ13
DQ15
R-CRE
F1-CE#
OE#
K2
K5
K3
K4
K6
K7
K8
K9
DQ12
VSS
R1-CE1#
DQ0
DQ10
F-VCC
R1-VCC
DQ7
L2
L9
L4
L5
L6
L7
L8
L3
DQ2
DQ11
A25
DQ5
DQ14
F-WP#
R-VCC
DQ8
DNU
M5
M2
M3
M4
M6
M7
M8
M9
A27
A26
VSS
F-VCC
F4-CE# R-VCCQ F-VCCQ
DNU
N1
N2
N10
N9
DNU
DNU
DNU
DNU
P1
P2
P10
P9
DNU
DNU
DNU
DNU
Table
BALL
1.8V
Vcc
3.0V
Vcc
FASL Standard
MCP Packages
D2
NC
F-WP#
ACC
7.0 x 9.0mm
8.0 x 11.6mm
9.0 x 12.0mm
11.0 x 13.0mm
WP#/
ACC
D5
F5
RY/
BY#
F-RDY/
R-WAIT#
Notes:
1. F1 and F2 denote XIP/Code Flash, while F3 and F4 denote Data/Companion Flash.
9
S71WS256/128/064J_00_A0 November 10, 2004
P r e l i m i n a r y
Input/Output Descriptions
A22-A0
DQ15-DQ0
OE#
=
=
=
Address inputs
Data input/output
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
WE#
VSS
NC
=
=
=
=
Write Enable input.
Ground
No Connect; not connected internally
Ready output. Indicates the status of the Burst read
(shared with WAIT# pin of RAM).
RDY
CLK
=
Clock input. In burst mode, after the initial word is
output, subsequent active edges of CLK increment
the internal address counter. Should be at VIL or VIH
while in asynchronous mode
AVD#
=
Address Valid input. Indicates to device that the
valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid
address; for burst mode, causes starting address to
be latched.
High = device ignores address inputs
F-RST#
F-WP#
=
=
Hardware reset input. Low = device resets and
returns to reading array data
Hardware write protect input. At VIL, disables
program and erase functions in the four outermost
sectors. Should be at VIH for all other conditions.
F-ACC
=
Accelerated input. At VHH, accelerates
programming; automatically places device in unlock
bypass mode. At VIL, disables all program and erase
functions. Should be at VIH for all other conditions.
R-CE#1
F1-CE#
=
=
Chip-enable input for pSRAM.
Chip-enable input for Flash 1. Asynchronous relative
to CLK for Burst Mode.
R-CRE
F-VCC
R-VCC
R-UB#
R-LB#
F2-CE#
=
=
=
=
=
=
Control Register Enable (pSRAM).
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM).
Chip-enable input for Flash 2. Asynchronous relative
to CLK for burst mode (needed only for
S71WS256J).
DNU
=
Do not use.
November 10, 2004 S71WS256/128/064J_00_A0
10
P r e l i m i n a r y
Ordering Information
The order number is formed by a valid combinations of the following:
S71WS 256
J
C0 BA
W
A
K
0
PACKING TYPE
0
1
2
3
=
=
=
=
Tray
Tube
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
6
A
=
=
CellularRAM 1, 66MHz
CellularRAM 2, 66MHz
PACKAGE MODIFIER
A
T
2
=
=
=
8 x 11.6 mm, 1.2 mm height, 84 balls, FBGA
8 x 11.6 mm, 1.4 mm height, 84 balls, FBGA
7 x 9 mm, 1.2 mm height, 80 balls, FBGA
TEMPERATURE RANGE
W
I
=
=
Wireless (-25
Industrial (-40
°
C to +85
°
C)
C)
°C to +85
°
PACKAGE TYPE
BA
BF
=
=
Very-thin Fine-pitch BGA Lead (Pb)-free compliant package
Very-thin Fine-pitch BGA Lead (Pb)-free package
pSRAM DENSITY
C0
B0
A0
=
=
=
64 Mb pSRAM
32 Mb pSRAM
16 Mb pSRAM
PROCESS TECHNOLOGY
110 nm, Floating Gate Technology
J
=
FLASH DENSITY
256
128
064
=
=
=
256Mb
128Mb
64Mb
PRODUCT FAMILY
S71WS Multi-chip Product (MCP)
1.8-volt Simultaneous Read/Write, Burst Mode Flash Memory and pRAM
S71WS064JA0 Valid Combinations (WS064J Flash + 16Mb pSRAM)
Base Ordering
Part Number
Temperature
Range
Package Marking
Burst Speed
Material Set
Supplier
S71WS064JA0BAW2A
S71WS064JA0BAI2A
S71WS064JA0BFW2A
S71WS064JA0BFI2A
71WS064JA0BAW2A
71WS064JA0BAI2A
71WS064JA0BFW2A
71WS064JA0BFI2A
-25°C to +85°C
-40°C to +85°C
-25°C to +85°C
-40°C to +85°C
Pb-free compliant
66 MHz
CellularRAM Type 2
Pb-free
Notes:
Valid Combinations
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
11
S71WS256/128/064J_00_A0 November 10, 2004
P r e l i m i n a r y
S71WS064JB0 Valid Combinations (WS064J Flash + 32Mb pSRAM)
Base Ordering
Part Number
Temperature
Range
Package Marking
Burst Speed
Material Set
Supplier
S71WS064JB0BAW2A
S71WS064JB0BAI2A
S71WS064JB0BFW2A
S71WS064JB0BFI2A
71WS064JB0BAW2A
71WS064JB0BAI2A
71WS064JB0BFW2A
71WS064JB0BFI2A
-25°C to +85°C
-40°C to +85°C
-25°C to +85°C
-40°C to +85°C
CellularRAM Type 2
CellularRAM Type 2
CellularRAM Type 2
CellularRAM Type 2
Pb-free compliant
66 MHz
Pb-free
Notes:
Valid Combinations
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
S71WS128JA0 Valid Combinations (WS128J Flash + 16Mb pSRAM)
Base Ordering
Part Number
Temperature
Range
Package Marking
Burst Speed
Material Set
Supplier
S71WS128JA0BAWAA
S71WS128JA0BAIAA
S71WS128JA0BFWAA
S71WS128JA0BFIAA
71WS128JA0BAWAA
71WS128JA0BAIAA
71WS128JA0BFWAA
71WS128JA0BFIAA
-25°C to +85°C
-40°C to +85°C
-25°C to +85°C
-40°C to +85°C
Pb-free compliant
66 MHz
CellularRAM Type 2
Pb-free
Notes:
Valid Combinations
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
S71WS128JB0 Valid Combinations (WS128J Flash + 32Mb pSRAM)
Base Ordering
Part Number
Temperature
Range
Package Marking
Burst Speed
Material Set
Supplier
S71WS128JB0BAWAA
S71WS128JB0BAIAA
S71WS128JB0BFWAA
S71WS128JB0BFIAA
71WS128JB0BAWAA
71WS128JB0BAIAA
71WS128JB0BFWAA
71WS128JB0BFIAA
-25°C to +85°C
-40°C to +85°C
-25°C to +85°C
-40°C to +85°C
CellularRAM Type 2
CellularRAM Type 2
CellularRAM Type 2
CellularRAM Type 2
Pb-free compliant
66 MHz
Pb-free
Notes:
Valid Combinations
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
November 10, 2004 S71WS256/128/064J_00_A0
12
P r e l i m i n a r y
S71WS128JC0 Valid Combinations (WS128J Flash + 64Mb pSRAM)
Base Ordering
Part Number
Temperature
Range
Package Marking
Burst Speed
Material Set
Supplier
S71WS128JC0BAWA6
S71WS128JC0BAWAA
S71WS128JC0BAIA6
S71WS128JC0BAIAA
S71WS128JC0BFWA6
S71WS128JC0BFWAA
S71WS128JC0BFIA6
S71WS128JC0BFIAA
71WS128JC0BAWA6
71WS128JC0BAWAA
71WS128JC0BAIA6
71WS128JC0BAIAA
71WS128JC0BFWA6
71WS128JC0BFWAA
71WS128JC0BFIA6
71WS128JC0BFIAA
CellularRAM Type 1
CellularRAM Type 2
CellularRAM Type 1
CellularRAM Type 2
CellularRAM Type 1
CellularRAM Type 2
CellularRAM Type 1
CellularRAM Type 2
-25°C to +85°C
-40°C to +85°C
-25°C to +85°C
-40°C to +85°C
Pb-free compliant
66 MHz
Pb-free
Notes:
Valid Combinations
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
S71WS256JC0 Valid Combinations (2 x WS128J Flash + 64Mb pSRAM)
Base Ordering
Part Number
Temperature
Range
Package Marking
Burst Speed
Material Set
Supplier
S71WS256JC0BAWT6
S71WS256JC0BAWTA
S71WS256JC0BAIT6
S71WS256JC0BAITA
S71WS256JC0BFWT6
S71WS256JC0BFWTA
S71WS256JC0BFIT6
S71WS256JC0BFITA
71WS256JC0BAWT6
71WS256JC0BAWTA
71WS256JC0BAIT6
71WS256JC0BAITA
71WS256JC0BFWT6
71WS256JC0BFWTA
71WS256JC0BFIT6
71WS256JC0BFITA
CellularRAM Type 1
CellularRAM Type 2
CellularRAM Type 1
CellularRAM Type 2
CellularRAM Type 1
CellularRAM Type 2
CellularRAM Type 1
CellularRAM Type 2
-25°C to +85°C
-40°C to +85°C
-25°C to +85°C
-40°C to +85°C
Pb-free compliant
66 MHz
Pb-free
Notes:
Valid Combinations
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
13
S71WS256/128/064J_00_A0 November 10, 2004
P r e l i m i n a r y
Physical Dimensions
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
C
C
A2
A
0.08
C
A1
SIDE VIEW
6
84X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
TLA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.20
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.81
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
0.97
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
E1
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
Ø b
eE
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SD / SE
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
November 10, 2004 S71WS256/128/064J_00_A0
14
P r e l i m i n a r y
FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
A
D1
D
eD
0.15
(2X)
C
10
9
8
SE
7
7
6
E
B
E1
5
4
3
2
1
eE
J
H
G
F
E
D
C
B
A
M
L K
INDEX MARK
10
PIN A1
CORNER
PIN A1
CORNER
7
SD
0.15
(2X)
C
TOP VIEW
BOTTOM VIEW
0.20
0.08
C
C
A2
A
C
A1
SIDE VIEW
6
84X
b
0.15
M
C
C
A
B
0.08
M
NOTES:
PACKAGE
JEDEC
FTA 084
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
11.60 mm x 8.00 mm
PACKAGE
NOTE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
SYMBOL
MIN
---
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
1.02
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
1.17
BODY THICKNESS
BODY SIZE
D
11.60 BSC.
8.00 BSC.
8.80 BSC.
7.20 BSC.
12
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
BODY SIZE
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
MD
ME
n
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
10
84
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
φb
0.35
0.40
0.45
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
eD
SD / SE
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
B1,B10,C1,C10,D1,D10,E1,E10
F1,F10,G1,G10,H1,H10
DEPOPULATED SOLDER BALLS
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
3388 \ 16-038.21a
15
S71WS256/128/064J_00_A0 November 10, 2004
S29WS128/064J
Flash Family for Multi-Chip Products (MCP)
128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
ADVANCE
INFORMATION
Distinctive Characteristics
— Asynchronous random access times of 45/55 ns (at
30 pF)
Power dissipation (typical values, CL = 30 pF)
— Burst Mode Read: 10 mA @ 80Mhz
— Simultaneous Operation: 25 mA @ 80Mhz
— Program/Erase: 15 mA
Architectural Advantages
Single 1.8 volt read, program and erase (1.65 to
1.95 volt)
Manufactured on 0.11 µm process technology
VersatileIO™ (VIO) Feature
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the VIO pin
— Standby mode: 0.2 µA
Hardware Features
— 1.8V compatible I/O signals (1.65-1.95 V)
Handshaking feature available
— Provides host system with minimum possible latency
by monitoring RDY
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture: WS128J: 16Mb/48Mb/48Mb/
16Mb, WS064J: 8Mb/24Mb/24Mb/8Mb
Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
WP# input
Programable Burst Interface
— Write protect (WP#) function allows protection of
four outermost boot sectors, regardless of sector
protect status
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector
SecSi™ (Secured Silicon) Sector region
— 128 words accessible through a command sequence,
64words for the Factory SecSi™ Sector and 64words
for the Customer SecSi™ Sector.
Sector Architecture
4 Kword x 16 boot sectors, eight at the top of the address
range, and eight at the bottom of the address range
— Sectors can be locked and unlocked in-system at VCC
level
Password Sector Protection
— WS128J: 4 Kword X 16, 32 Kword x 254 sectors
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
Bank A: 4 Kword x 8, 32 Kword x 31 sectors
Bank B: 32 Kword x 96 sectors
Bank C: 32 Kword x 96 sectors
ACC input: Acceleration function reduces
programming time; all sectors locked when ACC =
VIL
Bank D: 4 Kword x 8, 32 Kword x 31 sectors
— WS064J: 4 Kword x 16, 32 Kword x 126 sectors.
Bank A: 4 Kword x 8, 32 Kword x 15 sectors
CMOS compatible inputs, CMOS compatible outputs
Low VCC write inhibit
Bank B: 32 Kword x 48 sectors
Bank C: 32 Kword x 48 sectors
Bank D: 4 Kword x 8, 32 Kword x 15 sectors
Software Features
Cycling Endurance: 100,000 cycles per sector
typical
Data retention: 20-years typical
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC
42.4 standards
— Backwards compatible with AMD Am29BDS,
AMD Am29BDD, AMD Am29BL, andFujitsu MBM29BS
families
Performance Characteristics
Read access times at 80/66 MHz
— Burst access times of 9.1/11.2 ns @ 30 pF at
industrial temperature range
— Synchronous latency of 46/56 ns (at 30 pF)
Data# Polling and toggle bits
— Provides a software method of detecting program
and erase operation completion
Publication Number S29WS128_064J_MCP_00 Revision A Amendment 0 Issue Date May 5, 2004
This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion reserves the right to change or discontinue work on this proposed product without notice.
Erase Suspend/Resume
Unlock Bypass Program command
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
— Reduces overall programming time when issuing
multiple program command sequences
17
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
General Description
The S29WS128/064J_MCP/S29WS064J is a 128/64 Mbit, 1.8 Volt-only, simultaneous
Read/Write, Burst Mode Flash memory device, organized as 8,388,608/4,194,304 words
of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and
erase the memory array. A 12.0-volt VHH on ACC may be used for faster program perfor-
mance if desired. The device can also be programmed in standard EPROM programmers.
At 80 MHz, the device provides a burst access of 9.1 ns at 30 pF with a latency of 46 ns
at 30 pF. At 66 MHz, the device provides a burst access of 11.2 ns at 30 pF with a latency
of 56 ns at 30 pF. The device operates within the industrial temperature range of -40°C to
+85°C and the wireless temperature range of -25°C to +85°C. The device is offered in
Various FBGA packages.
The Simultaneous Read/Write architecture provides simultaneous operation by divid-
ing the memory space into four banks. The device can improve overall system perfor-
mance by allowing a host system to program or erase in one bank, then immediately and
simultaneously read from another bank, with zero latency. This releases the system from
waiting for the completion of program or erase operations.
The device is divided as shown in the following table:
Quantity
Bank
128Mb
64 Mb
8
Size
8
4 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
A
31
96
96
31
8
15
48
48
15
8
B
C
D
The VersatileIO™ (VIO) control allows the host system to set the voltage levels that the
device generates at its data outputs and the voltages tolerated at its data inputs to the
same voltage level that is asserted on the VIO pin.
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Out-
put Enable (OE#) to control asynchronous read and write operations. For burst opera-
tions, the device additionally requires Ready (RDY), and Clock (CLK). This
implementation allows easy interface with minimal glue logic to a wide range of micropro-
cessors/microcontrollers for high performance read operations.
The burst read mode feature gives system designers flexibility in the interface to the de-
vice. The user can preset the burst length and wrap through the same memory space, or
read the flash array in continuous mode.
The clock polarity feature provides system designers a choice of active clock edges, either
rising or falling. The active clock edge initiates burst accesses and determines when data
will be output.
The device is entirely command set compatible with the JEDEC 42.4 single-power-
supply Flash standard. Commands are written to the command register using standard
microprocessor write timing. Register contents serve as inputs to an internal state-ma-
chine that controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out
of the device is similar to reading from other Flash or EPROM devices.
The Erase Suspend/Erase Resume feature enables the user to put erase or program
on hold for any period of time to read data from, or program data to, any sector that is
not selected for erasure. True background erase can thus be achieved. If a read is needed
from the SecSi™ Sector area (One Time Program area) after an erase suspend, then the
user must use the proper command sequence to enter and exit this region. Program sus-
pend is also offered.
The hardware RESET# pin terminates any operation in progress and resets the internal
state machine to reading array data. The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the device, enabling the system microproces-
sor to read boot-up firmware from the Flash memory device.
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
18
The host system can detect whether a program or erase operation is complete by using
the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or
erase cycle has been completed, the device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be erased and reprogrammed
without affecting the data contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically in-
hibits write operations during power transitions. The device also offers two types of data
protection at the sector level. When at VIL, WP# locks the four outermost boot sectors.
The device offers two power-saving features. When addresses have been stable for a
specified amount of time, the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power consumption is greatly reduced in
both modes.
Spansion™ Flash memory products combine years of Flash memory manufacturing expe-
rience to produce the highest levels of quality, reliability and cost effectiveness. The de-
vice electrically erases all bits within a sector simultaneously via Fowler-Nordheim
tunnelling. The data is programmed using hot electron injection.
19
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
Product Selector Guide
S29WS128/064J_MCP/S29WS064J
Synchronous/Burst Asynchronous
Part
Number
2
2
66
80*
66
80*
Speed Option
Speed Option
MHz MHz
MHz MHz
Max Latency, ns (tIACC
Max Burst Access Time, ns (tBACC
Max OE# Access, ns (tOE
)
56
46
Max Access Time, ns (tACC
)
55
55
45
45
V
=
IO
1.65 –
1.95 V
)
11.2
11.2
9.1 Max CE# Access, ns (tCE)
)
9.1 Max OE# Access, ns (tOE
)
11.2
9.1
Block Diagram
VCC
VSS
DQ15–DQ0
VSSIO
VIO
RDY
Buffer
RDY
Erase Voltage
Generator
Input/Output
Buffers
WE#
RESET#
WP#
State
Control
ACC
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
CE#
OE#
Y-Decoder
Y-Gating
VCC
Detector
Timer
Cell Matrix
X-Decoder
Burst
State
Control
Burst
Address
Counter
AVD#
CLK
Amax–A0
Amax: WS064J (A21), WS128J (A22)
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
20
Block Diagram of Simultaneous Operation Circuit
V
CC
V
V
SS
IO
V
SSIO
Bank A Address
DQ15–DQ0
Bank A
Amax–A0
X-Decoder
OE#
Bank B Address
DQ15–DQ0
Bank B
WP#
ACC
X-Decoder
Amax–A0
STATE
CONTROL
&
COMMAND
REGISTER
RESET#
WE#
DQ15–DQ0
Status
CE#
AVD#
RDY
Control
Amax–A0
DQ15–DQ0
X-Decoder
Bank C
DQ15–DQ0
Bank C Address
Amax–A0
Amax–A0
X-Decoder
Bank D
Bank D Address
DQ15–DQ0
Amax: WS064J (A21), WS128J (A22)
21
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
Input/Output Descriptions
Amax-A0
DQ15-DQ0
CE#
=
=
=
Address inputs
Data input/output
Chip Enable input. Asynchronous relative to CLK for
the Burst mode.
OE#
=
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
WE#
VCC
=
=
Write Enable input.
Device Power Supply
(1.65 – 1.95 V).
VIO
=
Input & Output Buffer Power Supply
(1.65 – 1.95 V).
VSS
NC
RDY
=
=
=
Ground
No Connect; not connected internally
Ready output;
In Synchronous Mode, indicates the status of the
Burst read.
Low = data not valid at expected time. High = data
valid.
In Asynchronous Mode, indicates the status of the
internal program and erase function.
Low = program/erase in progress.
High Impedance = program/erase completed.
CLK is not required in asynchronous mode. In burst
mode, after the initial word is output, subsequent
active edges of CLK increment the internal address
counter.
Address Valid input. Indicates to device that the valid
address is present on the address inputs (Amax-A0).
Low = for asynchronous mode, indicates valid
address; for burst mode, causes starting address to
be latched.
CLK
=
=
AVD#
High = device ignores address inputs
Hardware reset input. Low = device resets and
returns to reading array data
Hardware write protect input. At VIL, disables
program and erase functions in the four outermost
sectors. Should be at VIH for all other conditions.
At VHH, accelerates programming; automatically
places device in unlock bypass mode. At VIL, locks all
sectors. Should be at VIH for all other conditions.
RESET#
WP#
=
=
ACC
=
Note:
1. Amax = A22 (WS128J), A21 (WS064J)
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
22
Logic Symbol
max*+1
Amax–A0
16
DQ15–DQ0
CLK
WP#
ACC
CE#
OE#
WE#
RDY
RESET#
AVD#
*Max = 22 for the WS128J and 21 for the WS064J.
23
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus operations, the inputs and con-
trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. Device Bus Operations
CLK
(See
Operation
CE#
OE#
WE#
A22–0
Addr In
Addr In
Addr In
Addr In
HIGH Z
HIGH Z
DQ15–0 RESET# Note) AVD#
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
L
L
L
L
H
H
L
I/O
I/O
H
H
H
H
H
L
X
X
X
L
L
L
H
H
X
X
I/O
Synchronous Write
L
L
I/O
Standby (CE#)
H
X
X
X
HIGH Z
HIGH Z
X
X
X
X
Hardware Reset
Burst Read Operations
Load Starting Burst Address
L
L
X
L
H
H
Addr In
HIGH Z
X
H
H
Advance Burst to next address with
appropriate Data presented on the Data Bus
Burst
Data Out
H
Terminate current Burst read cycle
H
X
X
X
H
H
HIGH Z
HIGH Z
HIGH Z
HIGH Z
H
L
X
X
Terminate current Burst read cycle via RESET#
X
Terminate current Burst read cycle and start
new Burst read cycle
L
X
H
HIGH Z
I/O
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care
Note: Default active edge of CLK is the rising edge.
VersatileIO™ (VIO) Control
The VersatileIO (VIO) control allows the host system to set the voltage levels that
the device generates at its data outputs and the voltages tolerated at its data in-
puts to the same voltage level that is asserted on the VIO pin.
Requirements for Asynchronous Read Operation (Non-Burst)
To read data from the memory array, the system must first assert a valid address
on Amax–A0(A22-A0 for WS128J and A21-A0 for WS064J), while driving AVD#
and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the
address. The data will appear on DQ15–DQ0. Since the memory array is divided
into four banks, each bank remains enabled for read access until the command
register contents are altered.
Address access time (tACC) is equal to the delay from stable addresses to valid
output data. The chip enable access time (tCE) is the delay from the stable ad-
dresses and stable CE# to valid data at the outputs. The output enable access
time (tOE) is the delay from the falling edge of OE# to valid data at the output.
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
24
The internal state machine is set for reading array data in asynchronous mode
upon device power-up, or after a hardware reset. This ensures that no spurious
alteration of the memory content occurs during the power transition.
Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst
operation of a preset length. When the device first powers up, it is enabled for
asynchronous read operation.
Prior to entering burst mode, the system should determine how many wait states
are desired for the initial word (tIACC) of each burst access, what mode of burst
operation is desired, which edge of the clock will be the active clock edge, and
how the RDY signal will transition with valid data. The system would then write
the configuration register command sequence. See “Set Configuration Register
Command Sequence” section on page 61 and “Command Definitions” section on
page 61 for further details.
Once the system has written the “Set Configuration Register” command se-
quence, the device is enabled for synchronous reads only.
The initial word is output tIACC after the active edge of the first CLK cycle. Sub-
sequent words are output tBACC after the active edge of each successive clock
cycle, which automatically increments the internal address counter. Note that the
device has a fixed internal address boundary that occurs every 64 words, starting
at address 00003Fh.
During the time the device is outputting data at this fixed internal address bound-
ary (address 00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency occurs
before data appears for the next address (address 000040h, 000080h, 0000C0h,
etc.).
Additionally, when the device is read from an odd address, 1 wait state is inserted
when the address pointer crosses the first boundary that occurs every 16 words.
For instance, if the device is read from 00001Ah (odd), 1 wait state is inserted
before the data of 000020h is output. This wait states is inserted at only the first
16 words boundary. Then, if the device is read from the odd address within the
last 16 words of 64 word boundary (address 000031h, 000033h,..., 00003Eh), a
three cycle latency occurs before data appears for the next address (address
000040h).
The RDY output indicates this condition to the system by pulsing deactive (low).
See Figure 34, “Latency with Boundary Crossing,” on page 108.
The device will continue to output sequential burst data, wrapping around to ad-
dress 000000h after it reaches the highest addressable memory location, until
the system drives CE# high, RESET# low, or AVD# low in conjunction with a new
address. See Table 1, “Device Bus Operations,” on page 24.
If the host system crosses the bank boundary while reading in burst mode, and
the device is not programming or erasing, a two-cycle latency will occur as de-
scribed above in the subsequent bank. If the host system crosses the bank
boundary while the device is programming or erasing, the device will provide read
status information. The clock will be ignored. After the host has completed status
reads, or the device has completed the program or erase operation, the host can
restart a burst operation using a new address and AVD# pulse.
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three burst read modes are of the linear wrap around design, in
which a fixed number of words are read from consecutive addresses. In each of
these modes, the burst addresses read are determined by the group within which
25
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
the starting address falls. The groups are sized according to the number of words
read in a single burst sequence for a given mode (see Table 2.)
Table 2. Burst Address Groups
Mode
8-word
16-word
32-word
Group Size
8 words
Group Address Ranges
0-7h, 8-Fh, 10-17h,...
16 words
32 words
0-Fh, 10-1Fh, 20-2Fh,...
00-1Fh, 20-3Fh, 40-5Fh,...
As an example: if the starting address in the 8-word mode is 39h, the address
range to be read would be 38-3Fh, and the burst sequence would be 39-3A-3B-
3C-3D-3E-3F-38h-etc. The burst sequence begins with the starting address writ-
ten to the device, but wraps back to the first address in the selected group. In a
similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst
sequence on the starting address written to the device, and then wrap back to
the first address in the selected address group. Note that in these three burst
read modes the address pointer does not cross the boundary that occurs
every 128 or 64 words; thus, no wait states are inserted (except during
the initial access).
The RDY pin indicates when data is valid on the bus.
Configuration Register
The device uses a configuration register to set the various burst parameters:
number of wait states, burst read mode, active clock edge, RDY configuration,
and synchronous mode active.
Handshaking
The device is equipped with a handshaking feature that allows the host system
to simply monitor the RDY signal from the device to determine when the initial
word of burst data is ready to be read. The host system should use the program-
mable wait state configuration to set the number of wait states for optimal burst
mode operation. The initial word of burst data is indicated by the active edge of
RDY after OE# goes low.
For optimal burst mode performance, the host system must set the appropriate
number of wait states in the flash device depending on clock frequency. See “Set
Configuration Register Command Sequence” section on page 61 for more
information.
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
26
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while program-
ming or erasing in another bank of memory. An erase operation may also be
suspended to read from or program to another location within the same bank (ex-
cept the sector being erased). Figure 37, “Back-to-Back Read/Write Cycle
Timings,” on page 111 shows how read and write cycles may be initiated for si-
multaneous operation with zero latency. Refer to the DC Characteristics table for
read-while-program and read-while-erase current specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asynchronous or synchronous
write operation. While the device is configured in Asynchronous read mode, it is
able to perform Asynchronous write operations only. CLK is ignored in the Asyn-
chronous programming mode. When in the Synchronous read mode
configuration, the device is able to perform both Asynchronous and Synchronous
write operations. CLK and WE# address latch is supported in the Synchronous
programming mode. During a synchronous write operation, to write a command
or command sequence (which includes programming data to the device and eras-
ing sectors of memory), the system must drive AVD# and CE# to VIL, and OE#
to VIH when providing an address to the device, and drive WE# and CE# to VIL,
and OE# to VIH. when writing commands or data. During an asynchronous write
operation, the system must drive CE# and WE# to VIL and OE# to VIH when pro-
viding an address, command, and data. Addresses are latched on the last falling
edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#.
The asynchronous and synchronous programing operation is independent of the
Set Device Read Mode bit in the Configuration Register (see Table 17, “Configu-
ration Register,” on page 65).
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 12, “WS128J Sector Address Table,” on page 47 and Table 13, “WS064J
Sector Address Table,” on page 55 indicate the address space that each sector oc-
cupies. The device address space is divided into four banks. A “bank address” is
the address bits required to uniquely select a bank. Similarly, a “sector address”
is the address bits required to uniquely select a sector.
ICC2 in the “DC Characteristics” section on page 87 represents the active current
specification for the write mode. The AC Characteristics section contains timing
specification tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. ACC
is primarily intended to allow faster manufacturing throughput at the factory.
If the system asserts VHH on this input, the device automatically enters the afore-
mentioned Unlock Bypass mode and uses the higher voltage on the input to
reduce the time required for program operations. The system would use a two-
cycle program command sequence as required by the Unlock Bypass mode. Re-
moving VHH from the ACC input returns the device to normal operation. Note that
sectors must be unlocked prior to raising ACC to VHH. Note that the ACC pin must
not be at VHH for operations other than accelerated programming, or device dam-
age may result. In addition, the ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions.
27
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sec-
tor protection verification, through identifier codes output from the internal
register (which is separate from the memory array) on DQ15–DQ0. This mode is
primarily intended for programming equipment to automatically match a device
to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID on ad-
dress pin A9. Address pins must be as shown in Table 3, “Autoselect Codes (High
Voltage Method),” on page 29. In addition, when verifying sector protection, the
sector address must appear on the appropriate highest order address bits (see
Table 4, “S29WS128/064J_MCP Boot Sector/Sector Block Addresses for Protec-
tion/Unprotection,” on page 29 and Table 5, “S29WS064J Boot Sector/Sector
Block Addresses for Protection/Unprotection,” on page 31). Table 3 shows the
remaining address bits that are don’t care. When all necessary bits have been
set as required, the programming equipment may then read the corresponding
identifier code on DQ15–DQ0. However, the autoselect codes can also be ac-
cessed in-system through the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A9
pin. The command sequence is illustrated in Table 18, “Command Definitions,”
on page 75. Note that if a Bank Address (BA) on address bits A22, A21, and A20
for the WS128J (A21:A19 for the WS064J) is asserted during the third write
cycle of the autoselect command, the host system can read autoselect data that
bank and then immediately read array data from the other bank, without exiting
the autoselect mode.
To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in Table 18, “Command
Definitions,” on page 75. This method does not require VID. Autoselect mode
may only be entered and used when in the asynchronous read mode. Refer to
the “Autoselect Command Sequence” section on page 65 for more information.
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
28
Table 3. Autoselect Codes (High Voltage Method)
Ama
x
to
A11
to
A5
to
WE
#
DQ15
to DQ0
Description
CE# OE#
RESET# A12 A10 A9 A8 A7 A6 A4 A3 A2 A1 A0
Manufacturer ID
FASL
:
VID
VID
VID
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
L
L
L
L
L
L
L
L
L
H
L
0001h
227Eh
Read Cycle 1
Read Cycle 2
2218h (WS128J)
221Eh (WS064J)
H
H
H
2200h (WS128J)
2201h (WS064J)
Read Cycle 3
H
L
H
L
H
H
H
L
Sector Protection
Verification
0001h (protected),
0000h (unprotected)
SA
DQ15 - DQ8 = 0
DQ7 - Factory Lock Bit
1 = Locked, 0 = Not Locked
DQ6 -Customer Lock Bit
1 = Locked, 0 = Not Locked
DQ5 = Handshake Bit
1 = Reserved, 0 = Standard
Handshake
VID
Indicator Bits
L
L
L
L
H
H
H
H
X
X
X
X
X
X
X
L
X
L
L
L
L
L
H
H
H
L
DQ4 & DQ3 - Boot Code
DQ2 - DQ0 = 001
Hardware Sector
Group Protection
0001h (protected),
0000h (unprotected)
VID
SA
X
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.
Notes:
1. The autoselect codes may also be accessed in-system via command sequences.
2. PPB Protection Status is shown on the data bus
Sector/Sector Block Protection and Unprotection
The hardware sector protection feature disables both programming and erase op-
erations in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected sectors. Sector protection/
unprotection can be implemented via two methods.
(Note: For the following discussion, the term “sector” applies to both sectors and
sector blocks. A sector block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table 4, “S29WS128/064J_MCP
Boot Sector/Sector Block Addresses for Protection/Unprotection,” on page 29 and
Table 5, “S29WS064J Boot Sector/Sector Block Addresses for Protection/Unpro-
tection,” on page 31).)
Table 4. S29WS128/064J_MCP Boot Sector/Sector Block Addresses for Protection/Unprotection
Sector/
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A22–A12
Sector Block Size
00000000000
00000000001
00000000010
00000000011
00000000100
00000000101
00000000110
00000000111
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
29
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
Sector/
Sector
A22–A12
Sector Block Size
SA8
00000001XXX,
00000010XXX,
00000011XXX,
000001XXXXX
000010XXXXX
000011XXXXX
000100XXXXX
000101XXXXX
000110XXXXX
000111XXXXX
001000XXXXX
001001XXXXX
001010XXXXX
001011XXXXX
001100XXXXX
001101XXXXX
001110XXXXX
001111XXXXX
010000XXXXX
010001XXXXX
010010XXXXX
010011XXXXX
010100XXXXX
010101XXXXX
010110XXXXX
010111XXXXX
011000XXXXX
011001XXXXX
011010XXXXX
011011XXXXX
011100XXXXX
011101XXXXX
011110XXXXX
011111XXXXX
100000XXXXX
100001XXXXX
100010XXXXX
100011XXXXX
100100XXXXX
100101XXXXX
100110XXXXX
100111XXXXX
101000XXXXX
101001XXXXX
101010XXXXX
101011XXXXX
101100XXXXX
101101XXXXX
32 Kwords
SA9
32 Kwords
SA10
32 Kwords
SA11–SA14
SA15–SA18
SA19–SA22
SA23-SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51–SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
SA119–SA122
SA123–SA126
SA127–SA130
SA131-SA134
SA135-SA138
SA139-SA142
SA143-SA146
SA147-SA150
SA151–SA154
SA155–SA158
SA159–SA162
SA163–SA166
SA167–SA170
SA171–SA174
SA175–SA178
SA179–SA182
SA183–SA186
SA187–SA190
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
30
Sector/
Sector
SA191–SA194
SA195–SA198
SA199–SA202
SA203–SA206
SA207–SA210
SA211–SA214
SA215–SA218
SA219–SA222
SA223–SA226
SA227–SA230
SA231–SA234
SA235–SA238
SA239–SA242
SA243–SA246
SA247–SA250
SA251–SA254
SA255–SA258
SA259
A22–A12
Sector Block Size
101110XXXXX
101111XXXXX
110000XXXXX
110001XXXXX
110010XXXXX
110011XXXXX
110100XXXXX
110101XXXXX
110110XXXXX
110111XXXXX
111000XXXXX
111001XXXXX
111010XXXXX
111011XXXXX
111100XXXXX
111101XXXXX
111110XXXXX
11111100XXX
11111101XXX
11111110XXX
11111111000
11111111001
11111111010
11111111011
11111111100
11111111101
11111111110
11111111111
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
32 Kwords
SA260
32 Kwords
SA261
32 Kwords
SA262
4 Kwords
SA263
4 Kwords
SA264
4 Kwords
SA265
4 Kwords
SA266
4 Kwords
SA267
4 Kwords
SA268
4 Kwords
SA269
4 Kwords
Table 5. S29WS064J Boot Sector/Sector Block Addresses for Protection/Unprotection
Sector/
Sector
SA0
A21–A12
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001XXX
0000010XXX
0000011XXX
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
Sector Block Size
4 Kwords
SA1
4 Kwords
SA2
4 Kwords
SA3
4 Kwords
SA4
4 Kwords
SA5
4 Kwords
SA6
4 Kwords
SA7
4 Kwords
SA8
32 Kwords
SA9
32 Kwords
SA10
32 Kwords
SA11–SA14
SA15–SA18
SA19–SA22
SA23-SA26
SA27-SA30
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
31
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
Sector/
Sector
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51–SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
SA119–SA122
SA123–SA126
SA127–SA130
SA131
A21–A12
Sector Block Size
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
1111100XXX
1111101XXX
1111110XXX
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
128 (4x32) Kwords
32 Kwords
SA132
32 Kwords
SA133
32 Kwords
SA134
4 Kwords
SA135
4 Kwords
SA136
4 Kwords
SA137
4 Kwords
SA138
4 Kwords
SA139
4 Kwords
SA140
4 Kwords
SA141
4 Kwords
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
32
Sector Protection
The device features several levels of sector protection, which can disable both the
program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled pro-
tection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before
changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in the outer-
most sectors.
All parts default to operate in the Persistent Sector Protection mode. The cus-
tomer must then choose if the Persistent or Password Protection method is most
desirable. There are two one-time programmable non-volatile bits that define
which sector protection method will be used. If the customer decides to continue
using the Persistent Sector Protection method, they must set the Persistent
Sector Protection Mode Locking Bit. This will permanently set the part to op-
erate only using Persistent Sector Protection. If the customer decides to use the
password method, they must set the Password Mode Locking Bit. This will
permanently set the part to operate only using password sector protection.
It is important to remember that setting either the Persistent Sector Protec-
tion Mode Locking Bit or the Password Mode Locking Bit permanently
selects the protection mode. It is not possible to switch between the two meth-
ods once a locking bit has been set. It is important that one mode is
explicitly selected when the device is first programmed, rather than re-
lying on the default mode alone. This is so that it is not possible for a system
program or virus to later set the Password Mode Locking Bit, which would cause
an unexpected shift from the default Persistent Sector Protection Mode into the
Password Protection Mode.
The WP# Hardware Protection feature is always available, independent of the
software managed protection method chosen.
The device is shipped with all sectors unprotected. Optional Spansion™ pro-
gramming services enable programming and protecting sectors at the factory
prior to shipping the device. Contact your local sales office for Details.
It is possible to determine whether a sector is protected or unprotected. See
“Autoselect Command Sequence” section on page 65 for details.
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protec-
tion method while at the same time enhancing flexibility by providing three
different sector protection states:
Persistently Locked—A sector is protected and cannot be changed.
Dynamically Locked—The sector is protected and can be changed by a sim-
ple command
Unlocked—The sector is unprotected and can be changed by a simple com-
mand
In order to achieve these states, three types of “bits” are going to be used:
33
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum of four
sectors (“S29WS128/064J_MCP Boot Sector/Sector Block Addresses for Protec-
tion/Unprotection” section on page 29, “S29WS064J Boot Sector/Sector Block
Addresses for Protection/Unprotection” section on page 31). All 4 Kbyte boot-
block sectors have individual sector Persistent Protection Bits (PPBs) for greater
flexibility. Each PPB is individually modifiable through the PPB Program
Command.
Note: If a PPB requires erasure, all of the sector PPBs must first be prepro-
grammed prior to PPB erasing. All PPBs erase in parallel, unlike programming
where individual PPBs are programmable. It is the responsibility of the user to
perform the preprogramming operation. Otherwise, an already erased sector
PPBs has the potential of being over-erased. There is no hardware mechanism to
prevent sector PPBs over-erasure.
Persistent Protection Bit Lock (PPB Lock)
A global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared
(“0”), the PPBs are changeable. There is only one PPB Lock bit per device. The
PPB Lock is cleared after power-up or hardware reset. There is no command se-
quence to unlock the PPB Lock.
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware
reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through
the DPB Write Command.
When the parts are first shipped, the PPBs are cleared (“0”). The DPBs and PPB
Lock are defaulted to power up in the cleared state – meaning the PPBs are
changeable.
When the device is first powered on, the DYBs power up in the cleared state
(sectors not protected). The Protection State for each sector is determined by
the logical OR of the PPB and the DPB related to that sector. For the sectors that
have the PPBs cleared, the DPBs control whether or not the sector is protected
or unprotected. By issuing the DPB Write command sequences, the DPBs will be
set or cleared, thus placing each sector in the protected or unprotected state.
These are the so-called Dynamic Locked or Unlocked states. They are called
dynamic states because it is very easy to switch back and forth between the
protected and unprotected conditions. This allows software to easily protect sec-
tors against inadvertent changes yet does not prevent the easy removal of
protection when changes are needed. The DPBs maybe set or cleared as often
as needed.
The PPBs allow for a more static, and difficult to change, level of protection. The
PPBs retain their state across power cycles because they are Non-Volatile. Indi-
vidual PPBs are set with a command but must all be cleared as a group through
a complex sequence of program and erasing commands. The PPBs are also lim-
ited to 100 erase cycles.
The PBB Lock bit adds an additional level of protection. Once all PPBs are pro-
grammed to the desired settings, the PPB Lock may be set to “1”. Setting the
PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In
effect, the PPB Lock Bit locks the PPBs into their current state. The only way to
clear the PPB Lock is to go through a power cycle. System boot code can deter-
mine if any changes to the PPB are needed e.g. to allow new system code to be
downloaded. If no changes are needed then the boot code can set the PPB Lock
to disable any further changes to the PPBs during system operation.
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
34
The WP# write protect pin adds a final level of hardware protection to the four
outermost 4 Kbytes sectors (SA0 - SA3 for a bottom boot, WS128J: SA266 -
SA269, WS064J: SA138 - SA141, or SA0 - SA3 & WS128J: SA266 - SA269,
WS064J: SA138 - SA141 for a dual boot). When this pin is low it is not possible
to change the contents of these four sectors. These sectors generally hold sys-
tem boot code. So, the WP# pin can prevent any changes to the boot code that
could override the choices made while setting up sector protection during sys-
tem initialization.
It is possible to have sectors that have been persistently locked, and sectors
that are left in the dynamic state. The sectors in the dynamic state are all un-
protected. If there is a need to protect some of them, a simple DPB Write
command sequence is all that is necessary. The DPB write command for the dy-
namic sectors switch the DPBs to signify protected and unprotected,
respectively. If there is a need to change the status of the persistently locked
sectors, a few more steps are required. First, the PPB Lock bit must be disabled
by either putting the device through a power-cycle, or hardware reset. The PPBs
can then be changed to reflect the desired settings. Setting the PPB lock bit once
again will lock the PPBs, and the device operates normally again.
Note: to achieve the best protection, it’s recommended to execute the PPB lock
bit set command early in the boot code, and protect the boot code by holding
WP# = VIL.
Table 6. Sector Protection Schemes
DPB
PPB
PPB Lock
Sector State
0
1
0
1
0
0
1
1
0
0
0
0
Unprotected—PPB and DPB are changeable
Protected—PPB and DPB are changeable
Protected—PPB and DPB are changeable
Protected—PPB and DPB are changeable
Unprotected—PPB not changeable, DPB is
changeable
0
1
0
1
0
0
1
1
1
1
1
1
Protected—PPB not changeable, DPB is
changeable
Protected—PPB not changeable, DPB is
changeable
Protected—PPB not changeable, DPB is
changeable
Table 6 contains all possible combinations of the DPB, PPB, and PPB lock relating
to the status of the sector.
In summary, if the PPB is set, and the PPB lock is set, the sector is protected and
the protection can not be removed until the next power cycle clears the PPB
lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The
DPB then controls whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores
the command and returns to read mode. A program command to a protected
sector enables status polling for approximately 1 µs before the device returns to
read mode without having modified the contents of the protected sector. An
erase command to a protected sector enables status polling for approximately
35
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
50 µs after which the device returns to read mode without having erased the
protected sector.
The programming of the DPB, PPB, and PPB lock for a given sector can be veri-
fied by writing a DPB/PPB/PPB lock verify command to the device.
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking
bit exists to guarantee that the device remain in software sector protection.
Once set, the Persistent Sector Protection locking bit prevents programming of
the password protection mode locking bit. This guarantees that a hacker could
not place the device in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of se-
curity than the Persistent Sector Protection Mode. There are two main
differences between the Persistent Sector Protection and the Password Sector
Protection Mode:
When the device is first powered on, or comes out of a reset cycle, the PPB
Lock bit is set to the locked state, rather than cleared to the unlocked state.
The only means to clear the PPB Lock bit is by writing a unique 64-bit Pass-
word to the device.
The Password Sector Protection method is otherwise identical to the Persistent
Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
The password is stored in a the SecSi™ (Secured Silicon) region of the flash
memory. Once the Password Mode Locking Bit is set, the password is perma-
nently set with no means to read, program, or erase it. The password is used to
clear the PPB Lock bit. The Password Unlock command must be written to the
flash, along with a password. The flash device internally compares the given
password with the pre-programmed password. If they match, the PPB Lock bit is
cleared, and the PPBs can be altered. If they do not match, the flash device does
nothing. There is a built-in 2 µs delay for each “password check.” This delay is
intended to thwart any efforts to run a program that tries all possible combina-
tions in order to crack the password.
Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first
program the password. FASL recommends that the password be somehow corre-
lated to the unique Electronic Serial Number (ESN) of the particular flash device.
Each ESN is different for every flash device; therefore each password should be
different for every flash device. While programming in the password region, the
customer may perform Password Verify operations.
Once the desired password is programmed in, the customer must then set the
Password Mode Locking Bit. This operation achieves two objectives:
1. It permanently sets the device to operate using the Password Protection
Mode. It is not possible to reverse this function.
2. It also disables all further commands to the password region. All program,
and read operations are ignored.
Both of these objectives are important, and if not carefully considered, may lead
to unrecoverable errors. The user must be sure that the Password Protection
method is desired when setting the Password Mode Locking Bit. More impor-
tantly, the user must be sure that the password is correct when the Password
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
36
Mode Locking Bit is set. Due to the fact that read operations are disabled, there
is no means to verify what the password is afterwards. If the password is lost
after setting the Password Mode Locking Bit, there will be no way to clear the
PPB Lock bit.
The Password Mode Locking Bit, once set, prevents reading the 64-bit password
on the DQ bus and further password programming. The Password Mode Locking
Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persis-
tent Sector Protection Locking Bit is disabled from programming, guaranteeing
that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible
through the use of the Password Program and Verify commands (see “Password
Program Command” section on page 71 and “Password Verify Command” sec-
tion on page 71). The password function works in conjunction with the Password
Mode Locking Bit, which when set, prevents the Password Verify command from
reading the contents of the password on the pins of the device.
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of
the Password Mode Locking Bit after power-up reset. If the Password Mode Lock
Bit is also set, after a hardware reset (RESET# asserted) or a power-up reset
the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to
issue the Password Unlock command. Successful execution of the Password Un-
lock command clears the PPB Lock Bit, allowing for sector PPBs modifications.
Asserting RESET#, taking the device through a power-on reset, or issuing the
PPB Lock Bit Set command sets the PPB Lock Bit to a “1”.
If the Password Mode Locking Bit is not set, including Persistent Protection
Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB
Lock Bit is setable by issuing the PPB Lock Bit Set command. Once set the only
means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset.
The Password Unlock command is ignored in Persistent Protection Mode.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming
equipment. The procedure requires high voltage (VID) to be placed on the RE-
SET# pin. Refer to Figure 2, “In-System Sector Protection/Sector Unprotection
Algorithms,” on page 40 for details on this procedure. Note that for sector unpro-
tect, all unprotected sectors must be first protected prior to the first sector write
cycle. Once the Password Mode Locking bit or Persistent Protection Locking bit are
set, the high voltage sector protect/unprotect capability is disabled.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# inputs are
both held at VCC ± 0.2 V. The device requires standard access time (tCE) for read
access, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
37
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
ICC3 in the “DC Characteristics” section on page 87 represents the standby cur-
rent specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. While in
asynchronous mode, the device automatically enables this mode when addresses
remain stable for tACC + 60 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is
latched and always available to the system. Based on the implementation by
design, the Auto Power Down feature is disabled in synchronous mode
and enabled in asynchronous mode. As a result, in synchronous mode,
the device can be in Auto Power Down Mode only by deselecting the CE#.
Note that a new burst operation is required to provide new data.
ICC6 in the “DC Characteristics” section on page 87 represents the automatic
sleep mode current specification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of resetting the device to reading
array data. When RESET# is driven low for at least a period of tRP, the device im-
mediately terminates any operation in progress, tristates all outputs, resets the
configuration register, and ignores all read/write commands for the duration of
the RESET# pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS ± 0.2 V, the standby current will be greater.
RESET# may be tied to the system reset circuitry. A system reset would thus also
reset the Flash memory, enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase operation, the device requires
a time of tREADY (during Embedded Algorithms) before the device is ready to read
data again. If RESET# is asserted when a program or erase operation is not ex-
ecuting, the reset operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after RESET# returns to
VIH.
Refer to the “AC Characteristics” section on page 96 for RESET# parameters and
to Figure 21, “Reset Timings,” on page 96 for the timing diagram.
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
38
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The outputs are
placed in the high impedance state.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If WP# = VIL, outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Figure 1. Temporary Sector Unprotect Operation
39
S29WS128/064J
S29WS128_064J_MCP_00_A0 May 5, 2004
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 µs
Wait 1 µs
unprotect address
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A7:A0 =
Verify Sector
Protect: Write 40h
to sector address
with A7:A0 =
01000010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 1.5 ms
00000010
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Protection/Sector Unprotection Algorithms
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
40
SecSi™ (Secured Silicon) Sector Flash Memory Region
The SecSi™ (Secured Silicon) Sector feature provides a Flash memory region
that enables permanent part identification through an Electronic Serial Number
(ESN). The SecSi™ Sector is 128 words in length and located at addresses
000000h-000007h. The Factory Indicator Bit (DQ7) is used to indicate whether
or not the Factory SecSi™ Sector is locked when shipped from the factory. The
Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer
SecSi™ Sector is locked when shipped from the factory. These bits are perma-
nently set at the factory and cannot be changed, in order to prevent cloning of a
factory locked part. This ensures the security of the ESN and customer code
once the product is shipped to the field.
FASL™ offers the device with a 64 word Factory SecSi™ Sector that is locked
when the part is shipped and a 64 words Customer SecSi™ Sector that is either
locked or is lockable. The Factory SecSi™ Sector is always protected when
shipped from the factory, and has the Factory Indicator Bit (DQ7) permanently
set to a “1”. The Customer SecSi™ Sector is shipped unprotected with the Cus-
tomer Indicator Bit (DQ6) set to “0”, allowing customers to utilize that sector in
any manner they choose. Once the Customer SecSi™ Sector area is protected,
the Customer Indicator Bit will be permanently set to “1.”
The system accesses the SecSi™ Sector through a command sequence (see
“Enter SecSi™ Sector/Exit SecSi™ Sector Command Sequence”). After the sys-
tem has written the Enter SecSi™ Sector command sequence, it may read the
SecSi™ Sector by using the addresses normally occupied by the memory array.
This mode of operation continues until the system issues the Exit SecSi™ Sector
command sequence, or until power is removed from the device. While SecSi™
Sector access is enabled, Memory Array read access, program operations, and
erase operations to all sectors other than SA0 are also available. On power-up,
or following a hardware reset, the device reverts to sending commands to the
normal address space.
Factory Locked: Factor SecSi™ Sector Programmed and Protected At the
Factory
In a factory sector locked device, the Factory SecSi™ Sector is protected when
the device is shipped from the factory whether or not the area was programmed
at the factory. The Factory SecSi™ Sector cannot be modified in any way. Op-
tional Spansion™ programming service can preprogram a random ESN, a
customer-defined code, or any combination of the two. The Factory SecSi™ Sec-
tor is located at addresses 000000h–00003Fh.
The device is available preprogrammed with one of the following:
A random, secure ESN only within the Factor SecSi™ Sector
Customer code within the Customer SecSi™ Sector through the Spansion
programming service
Both a random, secure ESN and customer code through the Spansion pro-
gramming service.
Table 7. SecSi™ Sector Addresses
Sector
Customer
Factory
Sector Size
64 words
Address Range
000040h-00007Fh
000000h-00003Fh
64 words
Customers may opt to have their code programmed by FASL through the Span-
sion programming service. FASL programs the customer’s code, with or without
the random ESN. The devices are then shipped from FASL’s factory with the Fac-
41
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S29WS128_064J_MCP_00_A0 May 5, 2004
tory SecSi™ Sector and Customer SecSi™ Sector permanently locked. Contact
the local sales office for details on using Spansion programming services.
Customer SecSi™ Sector
The customer lockable area is shipped unprotected, which allows the customer
to program and optionally lock the area as appropriate for the application. secu-
rity feature is not required, the Customer SecSi™ Sector can be treated as an
additional Flash memory space. The Customer SecSi™ Sector can be read any
number of times, but can be programmed and locked only once. Note that the
accelerated programming (ACC) and unlock bypass functions are not available
when programming the Customer SecSi™ Sector, but reading in Banks A, B, and
C is available. The Customer SecSi™ Sector is located at addresses 000040h–
00007Fh.
The Customer SecSi™ Sector area can be protected using one of the following
procedures:
Write the three-cycle Enter SecSi™ Sector Region command sequence, and
then follow the in-system sector protect algorithm as shown in Figure 2, “In-
System Sector Protection/Sector Unprotection Algorithms,” on page 40 ex-
cept that RESET# may be at either VIH or VID. This allows in-system protec-
tion of the Customer SecSi™ Sector Region without raising any device pin to
a high voltage. Note that this method is only applicable to the SecSi™ Sector.
Write the SecSi™ Sector Protection Bit Lock command sequence.
Once the Customer SecSi™ Sector is locked and verified, the system must write
the Exit SecSi™ Sector Region command sequence to return to reading and
writing the remainder of the array.
The Customer SecSi™ Sector lock must be used with caution since, once locked,
there is no procedure available for unlocking the Customer SecSi™ Sector area
and none of the bits in the Customer SecSi™ Sector memory space can be mod-
ified in any way.
SecSi™ Sector Protection Bit
The Customer SecSi™ Sector Protection Bit prevents programming of the Cus-
tomer SecSi™ Sector memory area. Once set, the Customer SecSi™ Sector
memory area contents are non-modifiable.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table 18, “Command
Definitions,” on page 75 for command definitions).
The device offers two types of data protection at the sector level:
The PPB and DPB associated command sequences disables or re-enables both
program and erase operations in any sector or sector group.
When WP# is at VIL, the four outermost sectors are locked.
When ACC is at VIL, all sectors are locked.
The following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or from system noise.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the four
outermost sectors. This function is provided by the WP# pin and overrides the
previously discussed Sector Protection/Unprotection method.
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
42
If the system asserts VIL on the WP# pin, the device disables program and erase
functions in the four “outermost” 4 Kword boot sectors. The four outermost 4
Kword boot sectors are the four sectors containing the lowest addresses (SA0 -
SA3), or the four sectors containing the highest addresses (WS128J: SA266 -
SA269, WS064J: SA138 - SA141) or both the lower four (SA0 - SA3) and upper
four sectors (WS128J: SA266 - SA269, WS064J: SA138 - SA141) in a dual-boot-
configured device.
If the system asserts VIH on the WP# pin, the device reverts to whether the
upper and/or lower four sectors were last set to be protected or unprotected.
That is, sector protection or unprotection for these sectors depends on whether
they were last protected or unprotected using the method described in “PPB Pro-
gram Command” section on page 73.
Note that the WP# pin must not be left floating or unconnected; inconsistent be-
havior of the device may result.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This pro-
tects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until VCC is greater than VLKO. The sys-
tem must provide the proper signals to the control inputs to prevent unintentional
writes when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does
not accept commands on the rising edge of WE#. The internal state machine is
automatically reset to the read mode on power-up.
43
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Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h any time the device is ready to read array data.
The system can read CFI information at the addresses given in Tables 8-11. To
terminate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 8-11. The system must write the reset
command to return the device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication
100, available via the FASL site at the following URL:
http://www.amd.com/us-en/FlashMemory/TechnicalResources/
0,,37_1693_1780_1834^1955,00.html. Alternatively, contact an FASL represen-
tative for copies of these documents.
Table 8. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
Primary OEM Command Set
13h
14h
0002h
0000h
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
May 5, 2004 S29WS128_064J_MCP_00_A0
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44
Table 9. System Interface String
Addresses
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
0017h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0019h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0003h
0000h
0009h
0000h
0004h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 10. Device Geometry Definition
Addresses
Data
Description
0018h (WS128J)
0017h (WS064J)
27h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FDh (WS128J)
007Dh (WS064J)
31h
Erase Block Region 2 Information
32h
33h
34h
0000h
0000h
0001h
35h
36h
37h
38h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
Erase Block Region 4 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
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Table 11. Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
000Ch
Silicon Technology (Bits 5-2) 0011 = 0.13 µm
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
0002h
0001h
0001h
0007h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
07 = Advanced Sector Protection
00E7h (WS128J)
0077h (WS064J)
Simultaneous Operation
Number of Sectors in all banks except boot block
4Ah
Burst Mode Type
00 = Not Supported, 01 = Supported
4Bh
4Ch
0001h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
4Fh
00B5h
00C5h
0001h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
01h = Dual Boot Device, 02h = Bottom Boot Device, 03h = Top Boot Device
50h
57h
0000h
0004h
Program Suspend. 00h = not supported
Bank Organization: X = Number of banks
0027h (WS128J)
0017h (WS064J)
58h
59h
5Ah
5Bh
Bank A Region Information. X = Number of sectors in bank
Bank B Region Information. X = Number of sectors in bank
Bank C Region Information. X = Number of sectors in bank
Bank D Region Information. X = Number of sectors in bank
0060h (WS128J)
0030h (WS064J)
0060h (WS128J)
0030h (WS064J)
0027h (WS128J)
0017h (WS064J)
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
46
Table 12. WS128J Sector Address Table
Bank
Sector
SA0
Sector Size
4 Kwords
(x16) Address Range
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
SA1
4 Kwords
SA2
4 Kwords
SA3
4 Kwords
SA4
4 Kwords
SA5
4 Kwords
SA6
4 Kwords
SA7
4 Kwords
SA8
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank D
47
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Table 12. WS128J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Bank C
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
48
Table 12. WS128J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
200000h-207FFFh
208000h-20FFFFh
210000h-217FFFh
218000h-21FFFFh
220000h-227FFFh
228000h-22FFFFh
230000h-237FFFh
238000h-23FFFFh
240000h-247FFFh
248000h-24FFFFh
250000h-257FFFh
258000h-25FFFFh
260000h-267FFFh
268000h-26FFFFh
270000h-277FFFh
278000h-27FFFFh
280000h-287FFFh
288000h-28FFFFh
290000h-297FFFh
298000h-29FFFFh
2A0000h-2A7FFFh
2A8000h-2AFFFFh
2B0000h-2B7FFFh
2B8000h-2BFFFFh
2C0000h-2C7FFFh
2C8000h-2CFFFFh
2D0000h-2D7FFFh
2D8000h-2DFFFFh
2E0000h-2E7FFFh
2E8000h-2EFFFFh
2F0000h-2F7FFFh
2F8000h-2FFFFFh
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
Bank C
49
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Table 12. WS128J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
300000h-307FFFh
308000h-30FFFFh
310000h-317FFFh
318000h-31FFFFh
320000h-327FFFh
328000h-32FFFFh
330000h-337FFFh
338000h-33FFFFh
340000h-347FFFh
348000h-34FFFFh
350000h-357FFFh
358000h-35FFFFh
360000h-367FFFh
368000h-36FFFFh
370000h-377FFFh
378000h-37FFFFh
380000h-387FFFh
388000h-38FFFFh
390000h-397FFFh
398000h-39FFFFh
3A0000h-3A7FFFh
3A8000h-3AFFFFh
3B0000h-3B7FFFh
3B8000h-3BFFFFh
3C0000h-3C7FFFh
3C8000h-3CFFFFh
3D0000h-3D7FFFh
3D8000h-3DFFFFh
3E0000h-3E7FFFh
3E8000h-3EFFFFh
3F0000h-3F7FFFh
3F8000h-3FFFFFh
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
Bank C
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
50
Table 12. WS128J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
400000h-407FFFh
408000h-40FFFFh
410000h-417FFFh
418000h-41FFFFh
420000h-427FFFh
428000h-42FFFFh
430000h-437FFFh
438000h-43FFFFh
440000h-447FFFh
448000h-44FFFFh
450000h-457FFFh
458000h-45FFFFh
460000h-467FFFh
468000h-46FFFFh
470000h-477FFFh
478000h-47FFFFh
480000h-487FFFh
488000h-48FFFFh
490000h-497FFFh
498000h-49FFFFh
4A0000h-4A7FFFh
4A8000h-4AFFFFh
4B0000h-4B7FFFh
4B8000h-4BFFFFh
4C0000h-4C7FFFh
4C8000h-4CFFFFh
4D0000h-4D7FFFh
4D8000h-4DFFFFh
4E0000h-4E7FFFh
4E8000h-4EFFFFh
4F0000h-4F7FFFh
4F8000h-4FFFFFh
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
SA160
SA161
SA162
SA163
SA164
SA165
SA166
Bank B
51
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Table 12. WS128J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
500000h-507FFFh
508000h-50FFFFh
510000h-517FFFh
518000h-51FFFFh
520000h-527FFFh
528000h-52FFFFh
530000h-537FFFh
538000h-53FFFFh
540000h-547FFFh
548000h-54FFFFh
550000h-557FFFh
558000h-55FFFFh
560000h-567FFFh
568000h-56FFFFh
570000h-577FFFh
578000h-57FFFFh
580000h-587FFFh
588000h-58FFFFh
590000h-597FFFh
598000h-59FFFFh
5A0000h-5A7FFFh
5A8000h-5AFFFFh
5B0000h-5B7FFFh
5B8000h-5BFFFFh
5C0000h-5C7FFFh
5C8000h-5CFFFFh
5D0000h-5D7FFFh
5D8000h-5DFFFFh
5E0000h-5E7FFFh
5E8000h-5EFFFFh
5F0000h-5F7FFFh
5F8000h-5FFFFFh
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA174
SA175
SA176
SA177
SA178
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
SA192
SA193
SA194
SA195
SA196
SA197
SA198
Bank B
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
52
Table 12. WS128J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
600000h-607FFFh
608000h-60FFFFh
610000h-617FFFh
618000h-61FFFFh
620000h-627FFFh
628000h-62FFFFh
630000h-637FFFh
638000h-63FFFFh
640000h-647FFFh
648000h-64FFFFh
650000h-657FFFh
658000h-65FFFFh
660000h-667FFFh
668000h-66FFFFh
670000h-677FFFh
678000h-67FFFFh
680000h-687FFFh
688000h-68FFFFh
690000h-697FFFh
698000h-69FFFFh
6A0000h-6A7FFFh
6A8000h-6AFFFFh
6B0000h-6B7FFFh
6B8000h-6BFFFFh
6C0000h-6C7FFFh
6C8000h-6CFFFFh
6D0000h-6D7FFFh
6D8000h-6DFFFFh
6E0000h-6E7FFFh
6E8000h-6EFFFFh
6F0000h-6F7FFFh
6F8000h-6FFFFFh
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
SA224
SA225
SA226
SA227
SA228
SA229
SA230
Bank B
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Table 12. WS128J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
(x16) Address Range
700000h-707FFFh
708000h-70FFFFh
710000h-717FFFh
718000h-71FFFFh
720000h-727FFFh
728000h-72FFFFh
730000h-737FFFh
738000h-73FFFFh
740000h-747FFFh
748000h-74FFFFh
750000h-757FFFh
758000h-75FFFFh
760000h-767FFFh
768000h-76FFFFh
770000h-777FFFh
778000h-77FFFFh
780000h-787FFFh
788000h-78FFFFh
790000h-797FFFh
798000h-79FFFFh
7A0000h-7A7FFFh
7A8000h-7AFFFFh
7B0000h-7B7FFFh
7B8000h-7BFFFFh
7C0000h-7C7FFFh
7C8000h-7CFFFFh
7D0000h-7D7FFFh
7D8000h-7DFFFFh
7E0000h-7E7FFFh
7E8000h-7EFFFFh
7F0000h-7F7FFFh
7F8000h-7F8FFFh
7F9000h-7F9FFFh
7FA000h-7FAFFFh
7FB000h-7FBFFFh
7FC000h-7FCFFFh
7FD000h-7FDFFFh
7FE000h-7FEFFFh
7FF000h-7FFFFFh
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
SA256
SA257
SA258
SA259
SA260
SA261
SA262
SA263
SA264
SA265
SA266
SA267
SA268
SA269
Bank A
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
May 5, 2004 S29WS128_064J_MCP_00_A0
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54
Table 13. WS064J Sector Address Table
Bank
Sector
SA0
Sector Size
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
Bank D
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Table 13. WS064J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
Bank C
May 5, 2004 S29WS128_064J_MCP_00_A0
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56
Table 13. WS064J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Bank C
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Table 13. WS064J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
200000h-207FFFh
208000h-20FFFFh
210000h-217FFFh
218000h-21FFFFh
220000h-227FFFh
228000h-22FFFFh
230000h-237FFFh
238000h-23FFFFh
240000h-247FFFh
248000h-24FFFFh
250000h-257FFFh
258000h-25FFFFh
260000h-267FFFh
268000h-26FFFFh
270000h-277FFFh
278000h-27FFFFh
280000h-287FFFh
288000h-28FFFFh
290000h-297FFFh
298000h-29FFFFh
2A0000h-2A7FFFh
2A8000h-2AFFFFh
2B0000h-2B7FFFh
2B8000h-2BFFFFh
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
Bank B
May 5, 2004 S29WS128_064J_MCP_00_A0
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58
Table 13. WS064J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
(x16) Address Range
2C0000h-2C7FFFh
2C8000h-2CFFFFh
2D0000h-2D7FFFh
2D8000h-2DFFFFh
2E0000h-2E7FFFh
2E8000h-2EFFFFh
2F0000h-2F7FFFh
2F8000h-2FFFFFh
300000h-307FFFh
308000h-30FFFFh
310000h-317FFFh
318000h-31FFFFh
320000h-327FFFh
328000h-32FFFFh
330000h-337FFFh
338000h-33FFFFh
340000h-347FFFh
348000h-34FFFFh
350000h-357FFFh
358000h-35FFFFh
360000h-367FFFh
368000h-36FFFFh
370000h-377FFFh
378000h-37FFFFh
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
Bank B
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Table 13. WS064J Sector Address Table (Continued)
Bank
Sector
Sector Size
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
4 Kwords
(x16) Address Range
380000h-387FFFh
388000h-38FFFFh
390000h-397FFFh
398000h-39FFFFh
3A0000h-3A7FFFh
3A8000h-3AFFFFh
3B0000h-3B7FFFh
3B8000h-3BFFFFh
3C0000h-3C7FFFh
3C8000h-3CFFFFh
3D0000h-3D7FFFh
3D8000h-3DFFFFh
3E0000h-3E7FFFh
3E8000h-3EFFFFh
3F0000h-3F7FFFh
3F8000h-3F8FFFh
3F9000h-3F9FFFh
3FA000h-3FAFFFh
3FB000h-3FBFFFh
3FC000h-3FCFFFh
3FD000h-3FDFFFh
3FE000h-3FEFFFh
3FF000h-3FFFFFh
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
Bank A
May 5, 2004 S29WS128_064J_MCP_00_A0
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60
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 18, “Command Definitions,” on page 75
defines the valid register command sequences. Writing incorrect address and
data values or writing them in the improper sequence may place the device in an
unknown state. The system must write the reset command to return the device
to reading array data. Refer to the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data in asynchronous mode. Each bank is
ready to read array data after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. After completing a pro-
gramming operation in the Erase Suspend mode, the system may once again
read array data from any non-erase-suspended sector within the same bank. See
the “Erase Suspend/Erase Resume Commands” section on page 70 for more
information.
The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the “Reset Command” section
on page 65 for more information.
See also “Requirements for Asynchronous Read Operation (Non-Burst)” section
on page 24 and “Requirements for Synchronous (Burst) Read Operation” section
on page 25 for more information. The Asynchronous Read and Synchronous/
Burst Read tables provide the read parameters, and Figure 14, “CLK Synchronous
Burst Mode Read (rising active CLK),” on page 91, Figure 16, “Synchronous Burst
Mode Read,” on page 92, and Figure 19, “Asynchronous Mode Read with Latched
Addresses,” on page 95 show the timings.
Set Configuration Register Command Sequence
The device uses a configuration register to set the various burst parameters:
number of wait states, burst read mode, active clock edge, RDY configuration,
and synchronous mode active. The configuration register must be set before the
device will enter burst mode.
The configuration register is loaded with a three-cycle command sequence. The
first two cycles are standard unlock sequences. On the third cycle, the data
should be C0h, address bits A11–A0 should be 555h, and address bits A19–A12
set the code to be latched. The device will power up or after a hardware reset
with the default setting, which is in asynchronous mode. The register must be set
before the device can enter synchronous mode. The configuration register can
not be changed during device operations (program, erase, or sector lock).
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Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(D15 = 0)
Asynchronous Mode
(D15 = 1)
Synchronous Read
Mode Only
Figure 3. Synchronous/Asynchronous State Diagram
Read Mode Setting
On power-up or hardware reset, the device is set to be in asynchronous read
mode. This setting allows the system to enable or disable burst mode during sys-
tem operations. Address A19 determines this setting: “1’ for asynchronous mode,
“0” for synchronous mode.
Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock
cycles that must elapse after AVD# is driven active before data will be available.
This value is determined by the input frequency of the device. Address bits A14–
A12 determine the setting (see Table 14, “Programmable Wait State Settings,” on
page 63).
The wait state command sequence instructs the device to set a particular number
of clock cycles for the initial access in burst mode. The number of wait states that
should be programmed into the device is directly related to the clock frequency.
May 5, 2004 S29WS128_064J_MCP_00_A0
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62
Table 14. Programmable Wait State Settings
A14
0
A13
0
A12
0
Total Initial Access Cycles
2
0
0
1
3
0
1
0
4
5
0
1
1
1
0
0
6
1
0
1
7 (default)
Reserved
Reserved
1
1
0
1
1
1
Notes:
1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2.
It is recommended that the wait state command sequence be written, even if the
default wait state value is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default setting.
Standard wait-state Handshaking Option
The host system must set the appropriate number of wait states in the flash de-
vice depending upon the clock frequency. The host system should set address bits
A14–A12 to 010 for a clock frequency of 66/80 MHz.
Table 15 describes the typical number of clock cycles (wait states) for various
conditions.
Table 15. Wait States for Standard wait-state Handshaking
Typical No. of Clock Cycles after AVD# Low
Burst Mode
8-Word or 16-Word or Continuous
32-Word
Conditions
VIO = 1.8 V
VIO = 1.8 V
66/80 MHz
4
5
* In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
The host system must set the appropriate number of wait states in the flash de-
vice depending upon the clock frequency. The autoselect function allows the host
system to determine whether the flash device is enabled for handshaking. See
the “Autoselect Command Sequence” section on page 65 for more information.
Read Mode Configuration
The device supports four different read modes: continuous mode, and 8, 16, and
32 word linear wrap around modes. A continuous sequence begins at the starting
address and advances the address pointer until the burst operation is complete.
If the highest address in the device is reached during the continuous burst read
mode, the address pointer wraps around to the lowest address.
For example, an eight-word linear read with wrap around begins on the starting
address written to the device and then advances to the next 8 word boundary.
The address pointer then returns to the 1st word after the previous eight word
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boundary, wrapping through the starting location. The sixteen- and thirty-two lin-
ear wrap around modes operate in a fashion similar to the eight-word mode.
Table 16 shows the address bits and settings for the four read modes.
Table 16. Read Mode Settings
Address Bits
Burst Modes
A16
0
A15
0
Continuous
8-word linear wrap around
16-word linear wrap around
32-word linear wrap around
0
1
1
0
1
1
Note: Upon power-up or hardware reset the default setting is continuous.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising edge of the clock after the
initial synchronous access time. Subsequent outputs will also be on the following
rising edges, barring any delays. The device can be set so that the falling clock
edge is active for all synchronous accesses. Address bit A17 determines this set-
ting; “1” for rising active, “0” for falling active.
RDY Configuration
By default, the device is set so that the RDY pin will output VOH whenever there
is valid data on the outputs. The device can be set so that RDY goes active one
data cycle before active data. Address bit A18 determines this setting; “1” for
RDY active with data, “0” for RDY active one clock cycle before valid data. In
asynchronous mode, RDY is an open-drain output.
Configuration Register
Table 17 shows the address bits that determine the configuration register settings
for various device functions.
May 5, 2004 S29WS128_064J_MCP_00_A0
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64
Table 17. Configuration Register
Settings (Binary)
Address Bit
Function
Set Device
Read Mode
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (default)
A19
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
A18
RDY
0 = Burst starts and data is output on the falling edge of CLK
1 = Burst starts and data is output on the rising edge of CLK (default)
A17
A16
Clock
Synchronous Mode
00 = Continuous (default)
Read Mode
01 = 8-word linear with wrap around
10 = 16-word linear with wrap around
11 = 32-word linear with wrap around
A15
A14
A13
000 = Data is valid on the 2nd active CLK edge after AVD# transition to VIH
001 = Data is valid on the 3rd active CLK edge after AVD# transition to VIH
010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH
011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH
100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH
101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default)
Programmable
Wait State
A12
110 = Reserved
111 = Reserved
Note: Device will be in the default state upon power-up or hardware reset.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins (prior to the third cycle). This re-
sets the bank to which the system was writing to the read mode. If the program
command sequence is written to a bank that is in the Erase Suspend mode, writ-
ing the reset command returns that bank to the erase-suspend-read mode. Once
programming begins, however, the device ignores reset commands until the op-
eration is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If a bank entered the autoselect mode while
in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command
returns the banks to the read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and device codes, and determine whether or not a sector is protected.
Table 18, “Command Definitions,” on page 75 shows the address and data re-
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quirements. The autoselect command sequence may be written to an address
within a bank that is either in the read or erase-suspend-read mode. The autose-
lect command may not be written while the device is actively programming or
erasing in the other bank.
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the bank address and the au-
toselect command. The bank then enters the autoselect mode. No subsequent
data will be made available if the autoselect data is read in synchronous mode.
The system may read at any address within the same bank any number of times
without initiating another autoselect command sequence. Read commands to
other banks will return data from the array. The following table describes the ad-
dress requirements for the various autoselect functions, and the resulting data.
BA represents the bank address, and SA represents the sector address. The de-
vice ID is read in three cycles.
Description
Manufacturer ID
Device ID, Word 1
Address
(BA) + 00h
(BA) + 01h
Read Data
0001h
227Eh
2218h (WS128J)
221Eh (WS064J)
Device ID, Word 2
Device ID, Word 3
(BA) + 0Eh
2200h (WS128J)
2201h (WS064J)
(BA) + 0Fh
(SA) + 02h
Sector Protection
Verification
0001 (locked),
0000 (unlocked)
DQ15 - DQ8 = 0
DQ7 - Factory Lock Bit
1 = Locked, 0 = Not Locked
DQ6 -Customer Lock Bit
1 = Locked, 0 = Not Locked
DQ5 - Handshake Bit
1 = Reserved,
Indicator Bits
(BA) + 03h
0 = Standard Handshake
DQ4 & DQ3 - Boot Code
00 = Dual Boot Sector,
01 = Top Boot Sector,
10 = Bottom Boot Sector
DQ2 - DQ0 = 001
The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the bank was previously in Erase Suspend).
Enter SecSi™ Sector/Exit SecSi™ Sector Command Sequence
The SecSi™ Sector region provides a secured data area containing a random,
eight word electronic serial number (ESN). The system can access the SecSi™
Sector region by issuing the three-cycle Enter SecSi™ Sector command se-
quence. The device continues to access the SecSi™ Sector region until the
system issues the four-cycle Exit SecSi™ Sector command sequence. The Exit
SecSi™ Sector command sequence returns the device to normal operation. The
SecSi™ Sector is not accessible when the device is executing an Embedded Pro-
gram or embedded Erase algorithm. Table 18, “Command Definitions,” on
May 5, 2004 S29WS128_064J_MCP_00_A0
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page 75 shows the address and data requirements for both command
sequences.
The following commands are not allowed when the SecSi™ is accessible.
— CFI
— Unlock Bypass Entry
— Unlock Bypass Program
— Unlock Bypass Reset
— Erase Suspend/Resume
— Chip Erase
Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up com-
mand. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further con-
trols or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table 18, “Command Defini-
tions,” on page 75 shows the address and data requirements for the program
command sequence.
When the Embedded Program algorithm is complete, that bank then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the
“Write Operation Status” section on page 78 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program op-
eration. The program command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit can-
not be programmed from “0” back to a “1.” Attempting to do so may cause that
bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the oper-
ation was successful. However, a succeeding read will show that the data is still
“0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to primarily program to a array
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program com-
mand sequence is all that is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence, resulting in faster total program-
ming time. The host system may also initiate the chip erase and sector erase
sequences in the unlock bypass mode. The erase command sequences are four
cycles in length instead of six cycles. Table 18, “Command Definitions,” on
page 75 shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock
Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The first cycle must contain the
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bank address and the data 90h. The second cycle need only contain the data 00h.
The array then returns to the read mode.
The device offers accelerated program operations through the ACC input. When
the system asserts VHH on this input, the device automatically enters the Unlock
Bypass mode. The system may then write the two-cycle Unlock Bypass program
command sequence. The device uses the higher voltage on the ACC input to ac-
celerate the operation.
Figure 4, “Program Operation,” on page 68 illustrates the algorithm for the pro-
gram operation. Refer to the Erase/Program Operations table in the AC
Characteristics section for parameters, and Figure 22, “Asynchronous Program
Operation Timings: AVD# Latched Addresses,” on page 98 and Figure 24, “Syn-
chronous Program Operation Timings: WE# Latched Addresses,” on page 100 for
timing diagrams.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 18 for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table 18, “Command Definitions,” on page 75
shows the address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
May 5, 2004 S29WS128_064J_MCP_00_A0
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68
of the erase operation by using DQ7 or DQ6/DQ2. Refer to the “Write Operation
Status” section on page 78 for information on these status bits.
Any commands written during the chip erase operation are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be reinitiated once that bank
has returned to reading array data, to ensure data integrity.
The host system may also initiate the chip erase command sequence while the
device is in the unlock bypass mode. The command sequence is two cycles in
length instead of six cycles. See Table 18, “Command Definitions,” on page 75 for
details on the unlock bypass command sequences.
Figure 5, “Erase Operation,” on page 71 illustrates the algorithm for the erase op-
eration. Refer to the Erase/Program Operations table in the AC Characteristics
section for parameters and timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 18, “Command Defi-
nitions,” on page 75 shows the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of no less than
50 µs occurs. During the time-out period, additional sector addresses and sector
erase commands may be written. Loading the sector erase buffer may be done
in any sequence, and the number of sectors may be from one sector to all sectors.
The time between these additional cycles must be less than 50 µs, otherwise era-
sure may begin. Any sector erase address and command following the exceeded
time-out may or may not be accepted. It is recommended that processor inter-
rupts be disabled during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase command is written. Any
command other than Sector Erase or Erase Suspend during the time-out period
resets that bank to the read mode. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See “DQ3: Sector Erase Timer” section on page 83.) The time-out begins from
the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase operation by reading
DQ7 or DQ6/DQ2 in the erasing bank. Refer to the “Write Operation Status” sec-
tion on page 78 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
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The host system may also initiate the sector erase command sequence while the
device is in the unlock bypass mode. The command sequence is four cycles cycles
in length instead of six cycles.
Figure 5, “Erase Operation,” on page 71 illustrates the algorithm for the erase op-
eration. Refer to the Erase/Program Operations table in the Figure , “AC
Characteristics,” on page 97 for parameters and timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. The bank address is required when writing this command. This com-
mand is valid only during the sector erase operation, including the minimum 50
µs time-out period during the sector erase command sequence. The Erase Sus-
pend command is ignored if written during the chip erase operation or Embedded
Program algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a maximum of 35 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written during the sector erase time-
out, the device immediately terminates the time-out period and suspends the
erase operation.
After the erase operation has been suspended, the bank enters the erase-sus-
pend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces sta-
tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer
to the Figure , “Write Operation Status,” on page 78 for information on these sta-
tus bits.
After an erase-suspended program operation is complete, the bank returns to the
erase-suspend-read mode. The system can determine the status of the program
operation using the DQ7 or DQ6 status bits, just as in the standard program op-
eration. Refer to the “Write Operation Status” section on page 78 for more
information.
In the erase-suspend-read mode, the system can also issue the autoselect com-
mand sequence. Refer to the “Autoselect Mode” section on page 28 and
“Autoselect Command Sequence” section on page 65 for details.
May 5, 2004 S29WS128_064J_MCP_00_A0
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To resume the sector erase operation, the system must write the Erase Resume
command. The bank address of the erase-suspended bank is required when writ-
ing this command. Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has resumed erasing.
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 18 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timer.
Figure 5. Erase Operation
Password Program Command
The Password Program Command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64-bits
long. 4 Password Program commands are required to program the password.
The user must enter the unlock cycle, password program command (38h) and
the program address/data for each portion of the password when programming.
There are no provisions for entering the 2-cycle unlock cycle, the password pro-
gram command, and all the password data. There is no special addressing order
required for programming the password. Also, when the password is undergoing
programming, Simultaneous Operation is disabled. Read operations to any
memory location will return the programming status except DQ7. Once pro-
gramming is complete, the user must issue a SecSi™ Exit command to return
the device to normal operation. Once the Password is written and verified, the
Password Mode Locking Bit must be set in order to prevent verification. The
Password Program Command is only capable of programming “0”s. Program-
ming a “1” after a cell is programmed as a “0” results in a time-out by the
Embedded Program Algorithm™ with the cell remaining as a “0”. The password
is all F’s when shipped from the factory. All 64-bit password combinations are
valid as a password.
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is
verifiable only when the Password Mode Locking Bit is not programmed. If the
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Password Mode Locking Bit is programmed and the user attempts to verify the
Password, the device will always drive all F’s onto the DQ data bus.
Also, the device will not operate in Simultaneous Operation when the Password
Verify command is executed. Only the password is returned regardless of the
bank address. The lower two address bits (A1–A0) are valid during the Password
Verify. Writing the SecSi™ Exit command returns the device back to normal
operation.
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the
Password Protection Mode Locking Bit, which prevents further verifies or up-
dates to the password. Once programmed, the Password Protection Mode
Locking Bit cannot be erased and the Persistent Protection Mode Locking Bit pro-
gram circuitry is disabled, thereby forcing the device to remain in the Password
Protection Mode. After issuing “PL/68h” at the fourth bus cycle, the device re-
quires a time out period of approximately 150 µs for programming the Password
Protection Mode Locking Bit. Then by writing “PL/48h” at the fifth bus cycle, the
device outputs verify data at DQ0. If DQ0 = 1, then the Password Protection
Mode Locking Bit is programmed. If not, the system must repeat this program
sequence from the fourth cycle of “PL/68h”. Exiting the Password Protection
Mode Locking Bit Program command is accomplished by writing the SecSi Sector
command.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs
the Persistent Sector Protection Mode Locking Bit, which prevents the Password
Mode Locking Bit from ever being programmed. By disabling the program cir-
cuitry of the Password Mode Locking Bit, the device is forced to remain in the
Persistent Sector Protection mode of operation, once this bit is set. After issuing
“SMPL/68h” at the fourth bus cycle, the device requires a time out period of ap-
proximately 150 µs for programming the Persistent Protect ion Mode Locking Bit.
Then by writing “SMPL/48h” at the fifth bus cycle, the device outputs verify data
at DQ0. If DQ0 = 1, then the Persistent Protection Mode Locking Bit is pro-
grammed. If not, the system must repeat this program sequence from the
fourth cycle of “PL/68h”. Exiting the Persistent Protection Mode Locking Bit Pro-
gram command is accomplished by writing the SecSi Sector Exit command.
SecSi™ Sector Protection Bit Program Command
To protect the SecSi Sector, write the SecSi Sector Protect command sequence
while in the SecSi Sector mode. After issuing “OPBP/48h” at the fourth bus cycle,
the device requires a time out period of approximately 150 µs to protect the SecSi
Sector. Then, by writing “OPBP/48” at the fifth bus cycle, the device outputs verify
data at DQ0. If DQ0 = 1, then the SecSi Sector is protected. If not, then the sys-
tem must repeat this program sequence from the fourth cycle of “OPBP/48h”.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared ei-
ther at reset or if the Password Unlock command was successfully executed.
There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot
be cleared unless the device is taken through a power-on clear or the Password
Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are
latched into the DPBs. If the Password Mode Locking Bit is set, the PPB Lock Bit
status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock
May 5, 2004 S29WS128_064J_MCP_00_A0
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72
Bit Set command is accomplished by writing the SecSi™ Exit command, only
while in the Persistent Sector Protection Mode.
DPB Write/Erase/Status Command
The DPB Write command is used to set or clear a DPB for a given sector. The
high order address bits (Amax–A11) are issued at the same time as the code
01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data
write cycle. The DPBs are modifiable at any time, regardless of the state of the
PPB or PPB Lock Bit. If the PPB is set, the sector is protected regardless of the
value of the DPB. If the PPB is cleared, setting the DPB to a 1 protects the sector
from programs or erases. Since this is a volatile bit, removing power or resetting
the device will clear the DPBs. The programming of the DPB for a given sector
can be verified by writing a DPB Status command to the device. Exiting the DPB
Write/Erase command is accomplished by writing the Read/Reset command. Ex-
iting the DPB Status command is accomplished by writing the SecSi™ Sector
Exit command
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the
PPBs can be unlocked for modification, thereby allowing the PPBs to become ac-
cessible for modification. The exact password must be entered in order for the
unlocking function to occur. This command cannot be issued any faster than 2 µs
at a time to prevent a hacker from running through the all 64-bit combinations
in an attempt to correctly match a password. If the command is issued before
the 2 µs execution window for each portion of the unlock, the command will be
ignored.
The Password Unlock function is accomplished by writing Password Unlock com-
mand and data to the device to perform the clearing of the PPB Lock Bit. The
password is 64 bits long, so the user must write the Password Unlock command
4 times. A1 and A0 are used for matching. Writing the Password Unlock com-
mand is not address order specific. The lower address A1–A0= 00, the next
Password Unlock command is to A1–A0= 01, then to A1–A0= 10, and finally to
A1–A0= 11.
Once the Password Unlock command is entered for all four words, the RDY pin
goes LOW indicating that the device is busy. Also, reading the Bank D results in
the DQ6 pin toggling, indicating that the Password Unlock function is in
progress. Reading the other bank returns actual array data. Approximately 1µs
is required for each portion of the unlock. Once the first portion of the password
unlock completes (RDY is not driven and DQ6 does not toggle when read), the
Password Unlock command is issued again, only this time with the next part of
the password. Four Password Unlock commands are required to successfully
clear the PPB Lock Bit. As with the first Password Unlock command, the RDY sig-
nal goes LOW and reading the device results in the DQ6 pin toggling on
successive read operations until complete. It is the responsibility of the micro-
processor to keep track of the number of Password Unlock commands, the order,
and when to read the PPB Lock bit to confirm successful password unlock. In
order to re lock the device into the Password Mode, the PPB Lock Bit Set com-
mand can be re-issued.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is
individually programmed (but is bulk erased with the other PPBs). The specific
sector address (Amax–A12) are written at the same time as the program com-
mand 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set
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for the sector, the PPB Program command will not execute and the command will
time-out without programming the PPB.
After programming a PPB, two additional cycles are needed to determine whether
the PPB has been programmed with margin. After 4th cycle, the device requires
approximately 150 µs time out period for programming the PPB. And then after
5th cycle, the device outputs verify data at DQ0.
The PPB Program command does not follow the Embedded Program algorithm.
Writing the SecSi™ Sector Exit command returns the device back to normal
operation.
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means
for individually erasing a specific PPB. Unlike the PPB program, no specific sector
address is required. However, when the PPB erase command is written (60h)
and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the
ALL PPB Erase command will not execute and the command will time-out with-
out erasing the PPBs.
After erasing the PPBs, two additional cycles are needed to determine whether
the PPB has been erased with margin. After 4th cycle, the device requires ap-
proximately 1.5 ms time out period for erasing the PPB. And then after 5th
cycle, the device outputs verify data at DQ0.
It is the responsibility of the user to preprogram all PPBs prior to issuing the All
PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure
may occur making it difficult to program the PPB at a later time. Also note that
the total number of PPB program/erase cycles is limited to 100 cycles. Cycling
the PPBs beyond 100 cycles is not guaranteed. Writing the SecSi™ Sector Exit
command returns the device back to normal operation.
PPB Status Command
The programming of the PPB for a given sector can be verified by writing a PPB
status verify command to the device.
PPB Lock Bit Status Command
The programming of the PPB Lock Bit for a given sector can be verified by writ-
ing a PPB Lock Bit status verify command to the device.
May 5, 2004 S29WS128_064J_MCP_00_A0
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Command Definitions
Table 18. Command Definitions
Bus Cycles (Notes 1–6)
Third Fourth Fifth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command Sequence
(Note 1)
First
Second
Sixth
Seventh
Asynchronous Read (Note 7)
Reset (Note 8)
1
1
RA
RD
F0
XXX
(BA)
555
(BA)
X00
Manufacturer ID
4
6
4
4
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
90
90
90
90
0001
227E
(BA)
555
(BA)
X01
(BA)X (Note (BA) (Not
Device ID (Note 10)
0E
10)
X0F e 10)
(SA)
555
(SA) 0000/
X02
Sector Lock Verify
(Note 11)
0001
(BA)
555
(BA)
X03
(Note
12)
Indicator Bits
Program
4
6
6
1
1
555
555
555
BA
AA
AA
AA
B0
30
2AA
2AA
2AA
55
55
55
555
555
555
A0
80
80
PA
Data
AA
Chip Erase
555
555
2AA
2AA
55
55
555
SA
10
30
Sector Erase
AA
Erase Suspend (Note 15)
Erase Resume (Note 16)
BA
(CR)
555
Set Configuration Register (Note 17)
3
555
AA
2AA
55
C0
20
CFI Query (Note 18)
1
55
98
Unlock Bypass Entry
3
555
AA
2AA
PA
55
PD
555
Unlock Bypass
Program (Notes 13,
14)
2
XX
A0
Unlock Bypass
Unlock
Sector Erase (Notes
2
2
2
XX
XX
XX
80
80
90
SA
30
Bypass
13, 14)
Mode
Unlock Bypass Erase
(Notes 13, 14)
XXX 10
XXX 00
Unlock Bypass Reset
(Notes 13, 14)
Sector Protection Command Definitions
SecSi™ Sector Entry
3
4
555
555
AA
AA
2AA
2AA
55
55
555
555
88
90
SecSi™ Sector Exit
SecSi™
XX
00
68
Sector
SecSi™ Protection
Bit Program (Notes
19, 20, 22)
RD
(0)
6
555
AA
2AA
55
555
60
OW
OW
48
OW
XX0
XX1
XX2
XX3
XX0
XX1
XX2
XX3
PD0
PD1
PD2
PD3
PD0
PD1
PD2
PD3
Password Program
(Notes 19, 24)
4
555
AA
2AA
55
555
38
Password
Protection
Password Verify
4
7
555
555
AA
AA
2AA
2AA
55
55
555
555
C8
28
Password Unlock
(Note 24)
XX0
PD0 XX1 PD1 XX2 PD2 XX3 PD3
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Bus Cycles (Notes 1–6)
Third Fourth Fifth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command Sequence
(Note 1)
First
Second
Sixth
Seventh
(SA)
+ WP
RD
(0)
PPB Program (Notes
(SA)
6
6
555
555
AA
AA
2AA
2AA
55
55
555
555
60
60
68
60
48
40
XX
XX
19, 20, 22)
+ WP
RD
(0)
PPB
All PPB Erase (Notes
Commands 19, 20, 23, 25)
(SA)
WP
WP
(SA)
555
(SA)
X02
RD
(0)
PPB Status (Note 26)
4
3
4
555
555
555
AA
AA
AA
2AA
2AA
2AA
55
55
55
90
78
58
PPB Lock Bit Set
555
PPB Lock
Bit
(BA)
555
RD
(1)
PPB Lock Bit Status
(Note 20)
BA
DPB Write
DPB Erase
4
4
555
555
AA
AA
2AA
2AA
55
55
555
555
48
48
SA
SA
X1
X0
DPB
(BA)
555
RD
(0)
DPB Status
4
6
555
555
AA
AA
2AA
2AA
55
55
58
60
SA
PL
Password Protection Mode
Locking Bit Program (Notes 19,
20, 22)
RD
(0)
555
555
68
68
PL
SL
48
48
PL
SL
Persistent Protection Mode
Locking Bit Program (Notes 19,
20, 22)
RD
(0)
6
555
AA
2AA
55
60
SL
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of
CLK which ever comes first.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector.
BA = Address of the bank (WS128J: A22, A21, A20, WS064J: A21, A20, A19) that is being switched to autoselect mode, is in
bypass mode, or is being erased.
SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked.
CR = Configuration Register address bits A19–A12.
OW = Address (A7–A0) is (00011010).
PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.
PWD = Password Data.
PL = Address (A7-A0) is (00001010)
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0.
RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0.
SL = Address (A7-A0) is (00010010)
WD= Write Data. See “Configuration Register” definition for specific write data
WP = Address (A7-A0) is (00000010)
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands,
fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1).
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PD3-PD0.
5. Unless otherwise noted, address bits Amax–A12 are don’t cares.
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
76
6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown
state. The system must write the reset command to return the device to reading array data.
7. No unlock or command cycles required when bank is reading array data.
8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or
performing sector lock/unlock.
9. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the
Autoselect Command Sequence section for more information.
10. (BA)X0Fh = 2200h (WS128J), (BA)X0Eh = 2218h (WS128J), (BA)X0Fh = 221Eh (WS064J), (BA)X0Eh = 2201h (WS064J)
11. The data is 0000h for an unlocked sector and 0001h for a locked sector
12. DQ15 - DQ8 = 0, DQ7 - Factory Lock Bit (1 = Locked, 0 = Not Locked), DQ6 -Customer Lock Bit (1 = Locked, 0 = Not
Locked), DQ5 = Handshake Bit (1 = Reserved, 0 = Standard Handshake)8, DQ4 & DQ3 - Boot Code (00= Dual Boot Sector,
01= Top Boot Sector, 10= Bottom Boot Sector, 11=No Boot Sector), DQ2 - DQ0 = 001
13. The Unlock Bypass command sequence is required prior to this command sequence.
14. The Unlock Bypass Reset command is required to return to reading array data.
15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase operation, and requires the bank address.
16. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.
17. See “Set Configuration Register Command Sequence” for details.
18. Command is valid when device is ready to read array data or when device is in autoselect mode.
19. The Reset command returns the device to reading the array.
20. Regardless of CLK and AVD# interaction or Control Register bit 15 setting, command mode verifies are always asynchronous
read operations.
21. ACC must be at VHH during the entire operation of this command
22. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been
fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again.
23. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If
DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again.
24. The entire four bus-cycle sequence must be entered for each portion of the password.
25. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs.
26. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set.
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Write Operation Status
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 20, “Write Operation Status,”
on page 84 and the following subsections describe the function of these bits. DQ7
and DQ6 each offers a method for determining whether a program or erase op-
eration is complete or in progress.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether a bank is in
Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse
in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then that bank returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide
an address within any of the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
bank returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
may change asynchronously with DQ6–DQ0 while Output Enable (OE#) is as-
serted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device has completed the program
or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may
be still invalid. Valid data on DQ7-D00 will appear on successive read cycles.
Table 20, “Write Operation Status,” on page 84 shows the outputs for Data# Poll-
ing on DQ7. Figure 6, “Data# Polling Algorithm,” on page 79 shows the Data#
Polling
algorithm.
Figure 28,
“Data#
Polling
Timings
(During Embedded Algorithm),” on page 104 in the AC Characteristics section
shows the Data# Polling timing diagram.
May 5, 2004 S29WS128_064J_MCP_00_A0
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78
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within
the sector being erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
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RDY: Ready
The RDY is a dedicated output that, when the device is configured in the Synchro-
nous mode, indicates (when at logic low) the system should wait 1 clock cycle
before expecting the next word of data. The RDY pin is only controlled by CE#.
Using the RDY Configuration Command Sequence, RDY can be set so that a logic
low indicates the system should wait 2 clock cycles before expecting valid data.
The following conditions cause the RDY output to be low: during the initial access
(in burst mode), and after the boundary that occurs every 64 words beginning
with the 64th address, 3Fh.
When the device is configured in Asynchronous Mode, the RDY is an open-drain
output pin which indicates whether an Embedded Algorithm is in progress or
completed. The RDY status is valid after the rising edge of the final WE# pulse in
the command sequence.
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is in high im-
pedance (Ready), the device is in the read mode, the standby mode, or in the
erase-suspend-read mode. Table 20, “Write Operation Status,” on page 84 shows
the outputs for RDY.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address in the same bank, and is valid
after the rising edge of the final WE# pulse in the command sequence (prior to
the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. When the operation is complete, DQ6
stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 ms after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
See the following for additional information: Figure 7, “Toggle Bit Algorithm,” on
page 81, “DQ6: Toggle Bit I” on page 80, Figure 29, “Toggle Bit Timings
(During Embedded Algorithm),” on page 104 (toggle bit timing diagram), and
Table 19, “DQ6 and DQ2 Indications,” on page 82.
Toggle Bit I on DQ6 requires either OE# or CE# to be deasserteed and reasserted
to show the change in state.
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80
START
Read Byte
(DQ0-DQ7)
Address = VA
Read Byte
(DQ0-DQ7)
Address = VA
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
No
DQ6 = Toggle?
Yes
FAIL
PASS
Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to
“1.” See the subsections on DQ6 and DQ2 for more information.
Figure 7. Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. But DQ2 cannot distinguish whether the sector is ac-
tively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits are required for sector and
81
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S29WS128_064J_MCP_00_A0 May 5, 2004
mode information. Refer to Table 19, “DQ6 and DQ2 Indications,” on page 82 to
compare outputs for DQ2 and DQ6.
See the following for additional information: Figure 7, “Toggle Bit Algorithm,” on
page 81, “DQ6: Toggle Bit I” on page 80, Figure 29, “Toggle Bit Timings
(During Embedded Algorithm),” on page 104, and Table 19, “DQ6 and DQ2 Indi-
cations,” on page 82.
Table 19. DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
programming,
at any address,
toggles,
does not toggle.
at an address within a sector
selected for erasure,
toggles,
toggles,
also toggles.
does not toggle.
toggles.
actively erasing,
erase suspended,
at an address within sectors not
selected for erasure,
at an address within a sector
selected for erasure,
does not toggle,
returns array data,
toggles,
at an address within sectors not
returns array data. The system can read
from any sector not selected for erasure.
selected for erasure,
programming in
erase suspend
at any address,
is not applicable.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7, “Toggle Bit Algorithm,” on page 81 for the following discussion.
Whenever the system initially begins reading toggle bit status, it must read DQ7–
DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typi-
cally, the system would note and store the value of the toggle bit after the first
read. After the second read, the system would compare the new value of the tog-
gle bit with the first. If the toggle bit is not toggling, the device has completed
the program or erase operation. The system can read array data on DQ7–DQ0 on
the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (Figure 7, “Toggle
Bit Algorithm,” on page 81).
May 5, 2004 S29WS128_064J_MCP_00_A0
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82
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified inter-
nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a
location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the operation,
and when the timing limit has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return
to the read mode (or to the erase-suspend-read mode if a bank was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be as-
sumed to be less than 50 µs, the system need not monitor DQ3. See also “Sector
Erase Command Sequence” on page 69.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device will accept addi-
tional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each sub-
sequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 20 shows the status of DQ3 relative to the other status bits.
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Table 20. Write Operation Status
DQ7
DQ5
DQ2
RDY
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
(Note 5)
Embedded Program Algorithm
No toggle
(Note 6)
DQ7#
0
Toggle
Toggle
0
0
0
0
Standard
Mode
Embedded Erase Algorithm
Erase
Toggle
Toggle
No toggle
(Note 6)
High
Impedance
1
0
N/A
Suspended Sector
Erase-Suspend-
Read (Note 4)
Erase
Suspend
Mode
Non-Erase
Suspended Sector
High
Impedance
Data
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
DQ7#
Toggle
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
4. The system may read either asynchronously or synchronously (burst) while in erase suspend.
5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress.
This is available in the Asynchronous mode only.
6. When the device is set to Asynchronous mode, these status flags should be read by CE# toggle.
May 5, 2004 S29WS128_064J_MCP_00_A0
S29WS128/064J
84
Absolute Maximum Ratings
Storage Temperature, Plastic Packages ................................. –65°C to +150°C
Ambient Temperature with Power Applied.............................. –65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except as noted below (Note 1) ................ –0.5 V to VIO + 0.5 V
VCC (Note 1)................................................................. –0.5 V to +2.5 V
VIO ............................................................................. –0.5 V to +2.5 V
A9, RESET#, ACC (Note 1) ............................................. –0.5 V to +12.5 V
Output Short Circuit Current (Note 3) ................................... 100 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –
2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage
transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 9.
2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater
than one second.
3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions
for extended periods may affect device reliability.
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 8. Maximum Negative Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
1.0 V
20 ns
20 ns
Figure 9. Maximum Positive Overshoot Waveform
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Operating Ranges
Commercial (C) Devices
Ambient Temperature (TA)0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA)................................................... –40°C to +85°C
Supply Voltages
VCC Supply Voltages........................................................... +1.65 V to +1.95 V
VIO Supply Voltages: .......................................................... +1.65 V to +1.95 V
VCC >= VIO - 100mV
Operating ranges define those limits between which the functionality of the device is guaranteed.
May 5, 2004 S29WS128_064J_MCP_00_A0
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86
DC Characteristics
CMOS Compatible
Parameter
Description
Test Conditions Notes: 1 & 2
VIN = VSS to VCC, VCC = VCCmax
VOUT = VSS to VCC, VCC = VCCmax
Min
Typ
Max
±1
±1
30
Unit
µA
ILI
Input Load Current
ILO
Output Leakage Current
µA
CE# = VIL, OE# = VIH
,
66 MHz
80 MHz
66 MHz
80 MHz
66 MHz
80 MHz
15
18
15
18
15
18
mA
mA
mA
mA
mA
mA
WE# = VIH, burst length =
8
36
CE# = VIL, OE# = VIH
,
30
WE# = VIH, burst length =
16
36
ICCB
VCC Active burst Read Current
CE# = VIL, OE# = VIH
,
30
WE# = VIH, burst length =
Continuous
36
CE# = VIL, OE# = VIH, WE# = VIH
burst length = 8
,
50
200
µA
IIO1
VIO Non-active Output
OE# = VIH
0.2
20
12
3.5
15
0.2
0.2
22
25
0.2
7
10
30
µA
mA
mA
mA
mA
µA
10 MHz
5 MHz
1 MHz
VCC Active Asynchronous Read Current
(Note 3)
CE# = VIL, OE# = VIH
WE# = VIH
,
ICC1
16
5
ICC2
ICC3
ICC4
VCC Active Write Current (Note 4)
VCC Standby Current (Note 5)
VCC Reset Current
CE# = VIL, OE# = VIH, ACC = VIH
CE# = RESET# = VCC ± 0.2 V
RESET# = VIL, CLK = VIL
40
50
50
µA
66 MHz
54
mA
mA
µA
VCC Active Current
(Read While Write)
ICC5
ICC6
IACC
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
80 MHz
60
VCC Sleep Current
50
VACC
VCC
15
mA
mA
V
Accelerated Program Current
(Note 6)
CE# = VIL, OE# = VIH,
VACC = 12.0 ± 0.5 V
5
10
VIL
VIH
VOL
VOH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VIO = 1.8 V
VIO = 1.8 V
–0.5
0.4
VIO + 0.4
0.1
VIO – 0.4
IOL = 100 µA, VCC = VCC min = VIO
IOH = –100 µA, VCC = VCC min = VIO
V
V
VIO – 0.1
11.5
Voltage for Autoselect and Temporary
Sector Unprotect
VID
VCC = 1.8 V
12.5
V
VHH
Voltage for Accelerated Program
Low VCC Lock-out Voltage
11.5
1.0
12.5
1.4
V
V
VLKO
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. VCC= VIO
3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH
.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Device enters automatic sleep mode when addresses are stable for tACC + 60 ns. Typical sleep mode current is equal
to ICC3
6. Total current during accelerated programming is the sum of VACC and VCC currents.
.
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Test Conditions
Device
Under
Test
C
L
Figure 10. Test Setup
Table 21. Test Specifications
Test Condition
All Speed Options
Unit
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
2.5 - 3
0.0–VIO
VIO/2
ns
V
Input Pulse Levels
Input timing measurement reference levels
Output timing measurement reference levels
V
VIO/2
V
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
Switching Waveforms
VIO
All Inputs and Outputs
VIO/2
VIO/2
Input
Measurement Level
Output
0.0 V
Figure 11. Input Waveforms and Measurement Levels
May 5, 2004 S29WS128_064J_MCP_00_A0
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88
AC Characteristics
VCC Power-up
Parameter
tVCS
Description
VCC Setup Time
VIO Setup Time
Test Setup
Min
Speed
50
Unit
µs
tVIOS
Min
50
µs
tRSTH
Notes:
RESET# Low Hold Time
Min
50
µs
1. VCC >= VIO - 100mV and VCC ramp rate is > 1V / 100µs
2. VCC ramp rate <1V / 100µs, a Hardware Reset will be required.
tVCS
VCC
tVIOS
VIO
RESET#
Figure 12.
V
Power-up Diagram
CC
CLK Characterization
Parameter
Description
66 MHz
66
80 MHz
80
Unit
fCLK
tCLK
tCKH
tCKL
tCR
CLK Frequency
Max
Min
MHz
ns
CLK Period
15
12.5
CLK High Time
CLK Low Time
CLK Rise Time
CLK Fall Time
Min
7.0
3
5
ns
ns
Max
2.5
tCF
t
CLK
t
t
CL
CH
CLK
t
t
CF
CR
Figure 13. CLK Characterization
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AC Characteristics
Synchronous/Burst Read @ VIO = 1.8 V
Parameter
JEDEC Standard Description
66 MHz 80 MHz Unit
Latency (Standard wait-state Handshake mode) for 8-Word
and 16-Word Burst
tIACC
Max
Max
56
46
ns
ns
Latency (Standard wait-state Handshake mode) for 32-
Word and Continuous Burst
tIACC
71
58.5
9.1
tBACC
tACS
tACH
tBDH
tCR
Burst Access Time Valid Clock to Output Delay
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Output Enable to Output Valid
Chip Enable to High Z
Max
Min
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Min
Min
Max
Max
Max
Min
11.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
5.5
2
11.2
11.2
9.1
9.1
tOE
tCEZ
tOEZ
tCES
tRDYS
tRACC
tAAS
tAAH
tCAS
tAVC
tAVD
tACC
tCKA
tCKZ
tOES
8
8
4
4
Output Enable to High Z
CE# Setup Time to CLK
RDY Setup Time to CLK
Ready Access Time from CLK
Address Setup Time to AVD# (Note 1)
Address Hold Time to AVD# (Note 1)
CE# Setup Time to AVD#
AVD# Low to CLK
11.2
9.1
4
5.5
0
4
AVD# Pulse
10
Access Time
55
45
CLK to access resume
11.2
9.1
CLK to High Z
8
4
Output Enable Setup Time
Note:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
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AC CHaracteristics
tCEZ
tCES
7 cycles for initial access shown.
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
tBDH
Addresses
Data
Aa
tBACC
tACH
Hi-Z
tIACC
tACC
Da
Da + 1
Da + n
tOEZ
OE#
RDY
tCR
tRACC
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed
from two cycles to seven cycles.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 14. CLK Synchronous Burst Mode Read (rising active CLK)
tCEZ
4 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
CLK
tAVC
AVD#
tAVD
tACS
tBDH
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da + 1
Da + n
tACC
tOEZ
OE#
RDY
tRACC
tOE
tCR
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from
two cycles to seven cycles. Clock is set for active falling edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 15. CLK Synchronous Burst Mode Read (Falling Active Clock)
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AC Characteristics
tCEZ
7 cycles for initial access shown.
tCAS
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tAAS
Addresses
Data
Aa
tBACC
tAAH
Hi-Z
tIACC
Da
Da + 1
Da + n
tACC
tBDH
tOEZ
OE#
RDY
tRACC
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed
from two cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 16. Synchronous Burst Mode Read
7 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
AC
Addresses
Data
tBACC
tACH
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
RDY
tCR
tRACC
tOE
tRACC
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed
from two cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode with wrap around.
4. D0-D7 in data waveform indicates the order the data within a given 8-word address range, from lowest to highest.
Starting address in figure is the 4th address in range (AC)
Figure 17. 8-word Linear Burst with Wrap Around
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92
AC Characteristics
tCEZ
6 wait cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
CLK
tAVC
AVD#
tAVD
tACS
Aa
Addresses
Data
tBACC
tACH
Hi-Z
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tOEZ
tRACC
OE#
RDY
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with A18=0; device will output RDY one cycle
before valid data.
Figure 18. Linear Burst with RDY Set One Cycle Before Data
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AC Characteristics
Asynchronous Mode Read @ VIO = 1.8 V
Parameter
66
80
JEDEC Standard Description
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCE
tACC
Access Time from CE# Low
Max
Max
Min
Min
Min
Max
Min
Min
Max
Min
55
55
45
45
Asynchronous Access Time (Note 1)
AVD# Low Time
tAVDP
tAAVDS
tAAVDH
tOE
10
4
Address Setup Time to Rising Edge of AVD
Address Hold Time from Rising Edge of AVD
Output Enable to Output Valid
5.5
11.2
9.1
Read
0
8
8
0
tOEH
Output Enable Hold Time
Toggle and Data# Polling
tOEZ
tCAS
Output Enable to High Z (Note 2)
CE# Setup Time to AVD#
Notes:
1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#.
2. Not 100% tested.
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AC Characteristics
CE#
tOE
OE#
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
tAAVDH
tCAS
tAVDP
tAAVDS
Note: RA = Read Address, RD = Read Data.
Figure 19. Asynchronous Mode Read with Latched Addresses
CE#
OE#
tOE
tOEH
WE#
Data
tCE
tOEZ
Valid RD
tACC
RA
Addresses
AVD#
Note: RA = Read Address, RD = Read Data.
Figure 20. Asynchronous Mode Read
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AC Characteristics
Hardware Reset (RESET#)
Parameter
All Speed
Options
JEDEC
Std
Description
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
Max
35
µs
RESET# Pin Low (NOT During Embedded Algorithms)
to Read Mode (See Note)
tReady
500
ns
tRP
tRH
RESET# Pulse Width
Min
Min
Min
500
200
20
ns
ns
µs
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
tRPD
Note: Not 100% tested.
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
CE#, OE#
RESET#
tReady
tRP
Figure 21. Reset Timings
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AC Characteristics
Erase/Program Operations @ VIO = 1.8 V
Parameter
JEDEC Standard Description
66 MHz 80 MHz Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
Min
45
4
ns
Synchronous
Asynchronous
Synchronous
Asynchronous
Address Setup Time (Notes
2, 3)
tAVWL
tAS
ns
0
5.5
15
10
20
0
Address Hold Time (Notes
2, 3)
tWLAX
tAH
Min
ns
tAVDP
tDS
AVD# Low Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
tDVWH
tWHDX
tGHWL
tDH
tGHWL
tCAS
tCH
Read Recovery Time Before Write
CE# Setup Time to AVD#
CE# Hold Time
0
0
0
tWHEH
tWLWH
tWHWL
tWP
Write Pulse Width
20
20
0
tWPH
tSR/W
Write Pulse Width High
Latency Between Read and Write Operations
tWHWH1
tWHWH1
tWHWH1 Programming Operation (Note 4)
<7
<4
<0.2
<104
500
1
tWHWH1 Accelerated Programming Operation (Note 4)
Sector Erase Operation (Notes 4, 5)
tWHWH2
tWHWH2
Typ
sec
Chip Erase Operation (Notes 4, 5)
tVID
tVIDS
tVCS
VACC Rise and Fall Time
Min
Min
Min
Min
Min
Min
Min
Min
ns
µs
µs
ns
ns
ns
ns
ns
VACC Setup Time (During Accelerated Programming)
VCC Setup Time
50
0
tELWL
tCS
CE# Setup Time to WE#
AVD# Setup Time to WE#
AVD# Hold Time to WE#
AVD# Hold Time to CLK
tAVSW
tAVHW
tAVHC
tCSW
4
4
4
Clock Setup Time to WE#
5
Notes:
1. Not 100% tested.
2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both
Asynchronous and Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#.
In synchronous program operation timing, addresses are latched on the first of either the rising edge of AVD# or the
active edge of CLK.
4. See the “Erase and Programming Performance” section for more information.
5. Does not include the preprogramming time.
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AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
PA
VA
VA
Addresses
Data
555h
In
Complete
A0h
PD
tDS
tDH
Progress
CE#
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A22–A12 are don’t care during command sequence unlock cycles.
4. CLK can be either VIL or VIH
.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Reg-
ister.
Figure 22. Asynchronous Program Operation Timings: AVD# Latched Addresses
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AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data
CLK
tACS
tCSW
AVD#
tAVDP
Addresses
555h
PA
VA
VA
In
Data
tCAS
Complete
A0h
PD
tDS
tDH
Progress
tAVSW
CE#
tCH
OE#
tAH
tWP
WE#
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A22–A12 are don’t care during command sequence unlock cycles.
4. CLK can be either VIL or VIH
.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Reg-
ister.
Figure 23. Asynchronous Program Operation Timings: WE# Latched Addresses
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AC Characteristics
Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
tACS
tCSW
AVD#
tAVDP
Addresses
555h
PA
VA
VA
In
Data
tCAS
Complete
A0h
PD
tDS
tDH
Progress
tAVSW
CE#
tCH
OE#
tAH
tWP
WE#
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A22–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.
The Configuration Register must be set to the Synchronous Read Mode.
Figure 24. Synchronous Program Operation Timings: WE# Latched Addresses
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AC Characteristics
Program Command Sequence (last two cycles)
tAVCH
Read Status Data
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
Addresses
555h
PA
VA
VA
In
Data
Complete
A0h
PD
tDS
tDH
Progress
tCAS
CE#
tCH
OE#
WE#
tCSW
tWP
tWHWH1
tWPH
tWC
tVCS
VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A22–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.
The Configuration Register must be set to the Synchronous Read Mode.
Figure 25. Synchronous Program Operation Timings: CLK Latched Addresses
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AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
SA
555h for
chip erase
VA
VA
Addresses
Data
2AAh
10h for
chip erase
In
Complete
55h
30h
Progress
tDS
tDH
CE#
tCH
OE#
WE#
tWP
tWHWH2
tCS
tWPH
tWC
tVCS
VCC
Figure 26. Chip/Sector Erase Command Sequence
Notes:
1. SA is the sector address for Sector Erase.
2. Address bits A22–A12 are don’t cares during unlock cycles in the command sequence.
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AC Characteristics
CE#
AVD#
WE#
Addresses
Data
PA
Don't Care
A0h
Don't Care
PD
Don't Care
OE#
tVIDS
1 µs
V
V
ID
ACC
tVID
or V
IL
IH
Note: Use setup and hold times from conventional program operation.
Figure 27. Accelerated Unlock Bypass Programming Timing
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AC Characteristics
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
tOEH
WE#
tACC
VA
Addresses
VA
Status Data
Status Data
Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, and Data# Polling will output true data.
3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 28. Data# Polling Timings (During Embedded Algorithm)
AVD#
tCEZ
tCE
CE#
tOEZ
tCH
tOE
OE#
WE#
tOEH
tACC
Addresses
Data
VA
VA
Status Data
Status Data
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, the toggle bits will stop toggling.
3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.
Figure 29. Toggle Bit Timings (During Embedded Algorithm)
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AC Characteristics
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tIACC
tIACC
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is
active one clock cycle before data.
Figure 30. Synchronous Data Polling Timings/Toggle Bit Timings
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Suspend
Program
Complete
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 31. DQ2 vs. DQ6
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AC Characteristics
Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
tVHH
Description
All Speed Options
Unit
ns
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
Min
500
250
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
Min
Min
4
4
µs
µs
RESET# Hold Time from RDY High for
Temporary Sector Unprotect
tRRB
Note: Not 100% tested.
VID
VID
RESET#
VIL or VIH
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
RDY
tRRB
tRSP
Figure 32. Temporary Sector Unprotect Timing Diagram
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AC Characteristics
V
ID
V
IH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
40h
Data
60h
60h
Sector Protect: 150 µs
Sector Unprotect: 1.5 ms
1 µs
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 33. Sector/Sector Block Protect and Unprotect Timing Diagram
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AC Characteristics
Address boundary occurs every 64 words, beginning at address
00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.
C60
C61
3D
C62
3E
C63
3F
C63
3F
C63
3F
C64
40
C65
41
C66
42
C67
43
CLK
3C
Address (hex)
(stays high)
AVD#
RDY
RDY
tRACC
tRACC
(Note 1)
(Note 2)
latency
tRACC
tRACC
latency
Data
D60
D61
D62
D63
D64
D65
D66
D67
Notes:
1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not
crossing a bank in the process of performing an erase or program.
4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle
latency at the boundary crossing.
Figure 34. Latency with Boundary Crossing
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AC Characteristics
Address boundary occurs every 64 words, beginning at address
00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.
C60
C61
3D
C62
3E
C63
3F
C63
3F
C63
3F
C64
40
CLK
3C
Address (hex)
(stays high)
AVD#
RDY
RDY
tRACC
tRACC
(Note 1)
(Note 2)
latency
tRACC
tRACC
latency
Data
Invalid
D60
D61
D62
D63
Read Status
OE#,
CE#
(stays low)
Notes:
1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device
crossing a bank in the process of performing an erase or program.
Figure 35. Latency with Boundary Crossing into Program/Erase Bank
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AC Characteristics
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
OE#
total number of clock cycles
following addresses being latched
1
2
0
3
1
4
5
6
4
7
5
CLK
2
3
number of clock cycles
programmed
Wait State Decoding Addresses:
A14, A13, A12 = “111” ⇒ Reserved
A14, A13, A12 = “110” ⇒ Reserved
A14, A13, A12 = “101” ⇒ 5 programmed, 7 total
A14, A13, A12 = “100” ⇒ 4 programmed, 6 total
A14, A13, A12 = “011” ⇒ 3 programmed, 5 total
A14, A13, A12 = “010” ⇒ 2 programmed, 4 total
A14, A13, A12 = “001” ⇒ 1 programmed, 3 total
A14, A13, A12 = “000” ⇒ 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.
Figure 36. Example of Wait States Insertion
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AC Characteristics
Last Cycle in
Program or
Sector Erase
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
Command Sequence
tWC
tRC
tRC
tWC
CE#
OE#
tOE
tOEH
tGHWL
WE#
Data
tWPH
tOEZ
tWP
tDS
tACC
tOEH
tDH
PD/30h
RD
RD
AAh
tSR/W
RA
Addresses
AVD#
PA/SA
tAS
RA
555h
tAH
Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking the
status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information.
Figure 37. Back-to-Back Read/Write Cycle Timings
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Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
32 Kword
4 Kword
128J
<0.4
<2
<2
Sector Erase Time
s
<0.2
Excludes 00h programming
prior to erasure (Note 4)
<103
Chip Erase Time
s
064J
<53
Excludes system level
overhead (Note 5)
Word Programming Time
<6
<100
<67
µs
µs
Accelerated Word Programming Time
<4
128J
<50.4
<25.2
<33
Chip Programming Time
(Note 3)
Excludes system level
overhead (Note 5)
s
s
064J
128J
Accelerated Chip
Programming Time
064J
<17
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 100,000 cycles. Additionally,
programming typicals assumes a checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.65 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 18, “Command Definitions,” on page 75 for further information on command definitions.
6. The device has a minimum cycling endurance of 100,000 cycles per sector.
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P r e l i m i n a r y
CellularRAM
128/64/32 Megabit
Burst CellularRAM
Features
Single device supports asynchronous, page, and burst operations
VCC Voltages
— 1.70V–1.95V VCC
Random Access Time: 70ns
Burst Mode Write Access
— Continuous burst
Burst Mode Read Access
— 4, 8, or 16 words, or continuous burst
Page Mode Read Access
— Sixteen-word page size
— Interpage read access: 70ns
— Intrapage read access: 20ns
Low Power Consumption
— Asynchronous READ < 25mA
— Intrapage READ < 15mA
— Initial access, burst READ < 35mA
— Continuous burst READ < 11mA
— Standby: 180µA
— Deep power-down < 10µA
Low-Power Features
— Temperature Compensated Refresh (TCR) On-chip sensor control
— Partial Array Refresh (PAR)
— Deep Power-Down (DPD) Mode
General Description
CellularRAM™ products are high-speed, CMOS dynamic random access memories
developed for low-power, portable applications. These devices include an industry
standard burst mode Flash interface that dramatically increases read/write band-
width compared with other low-power SRAM or Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a
transparent self-refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on de-
vice read/write performance.
Two user-accessible control registers define device operation. The bus configura-
tion register (BCR) defines how the CellularRAM device interacts with the system
memory bus and is nearly identical to its counterpart on burst mode Flash de-
vices. The refresh configuration register (RCR) is used to control how refresh is
performed on the DRAM array. These registers are automatically loaded with de-
fault settings during power-up and can be updated anytime during normal
operation.
Special attention has been focused on standby current consumption during self
refresh. CellularRAM products include three mechanisms to minimize standby
current. Partial array refresh (PAR) enables the system to limit refresh to only
that part of the DRAM array that contains essential data. Temperature compen-
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sated refresh (TCR) adjusts the refresh rate to match the device temperature—
the refresh rate decreases at lower temperatures to minimize current consump-
tion during standby. Deep power-down (DPD) enables the system to halt the
refresh operation altogether when no vital information is stored in the device. The
system-configurable refresh mechanisms are accessed through the RCR.
128M: A[22:0]
64M: A[21:0]
32M: A[20:0]
Address Decode
Logic
Input/
Output
MUX
and
Buffers
DQ[7:0]
DRAM
MEMORY
ARRAY
DQ[15:8]
Refresh Configuration
Register (RCR)
Bus Configuration
Register (BCR)
CE#
WE#
OE#
CLK
Control
Logic
ADV#
CRE
WAIT
LB#
UB#
Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing di-
agrams for detailed information.
Figure 38. Functional Block Diagram
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Table 22. Signal Descriptions
SYMBOL
TYPE
DESCRIPTION
128M: A[22:0]
64M: A[21:0]
32M: A[20:0]
Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are
internally latched during READ and WRITE cycles. The address lines are also used to define
the value to be loaded into the BCR or the RCR.
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous
operations. When configured for synchronous operation, the address is latched on the first
rising CLK edge when ADV# is active. CLK is static (HIGH or LOW) during asynchronous
access READ and WRITE operations and during PAGE READ ACCESS operations.
CLK
Input
Input
Address Valid: Indicates that a valid address is present on the address inputs. Addresses
can be latched on the rising edge of ADV# during asynchronous READ and WRITE
operations. ADV# can be held LOW during asynchronous READ and WRITE operations.
ADV#
CRE
CE#
Input
Input
Configuration Register Enable: When CRE is HIGH, WRITE operations load the RCR or BCR.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and
goes into standby or deep power-down mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output
buffers are disabled.
OE#
WE#
Input
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a
WRITE to either a configuration register or to the memory array.
LB#
UB#
Input
Input
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Input/
Output
DQ[15:0]
Data Inputs/Outputs.
Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is
gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE
operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to
mask the delay associated with opening a new internal page. WAIT is asserted and should
be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is
HIGH.
WAIT
VCC
Output
Supply
Supply
Supply
Supply
Device Power Supply: (1.7V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.7V–1.95V) Power supply for input/output buffers.
VSS must be connected to ground.
VCC
VSS
VSS
Q
Q
VSSQ must be connected to ground.
Note: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode.
WAIT will be asserted but should be ignored during asynchronous and page mode operations.
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Table 23. Bus Operations—Asynchronous Mode
CLK
(Note 1) ADV#
LB#/
UB#
WAIT
(Note 2)
DQ[15:0]
(Note 3)
MODE
Read
POWER
Active
Active
Standby
Idle
CE#
L
OE#
L
WE#
CRE
NOTES
4
X
X
X
X
L
L
H
L
L
L
L
L
L
L
Low-Z
Low-Z
High-Z
Low-Z
Data-Out
Data-In
High-Z
X
Write
L
X
4
Standby
No Operation
X
X
H
X
X
X
X
X
5, 6
4, 6
L
X
Configuration
Register
Active
X
X
L
L
H
X
L
H
X
X
X
Low-Z
High-Z
High-Z
High-Z
Deep
Power-down
DPD
X
H
X
7
Notes:
1. CLK may be HIGH or LOW, but must be static during synchronous read, synchronous write, burst suspend, and DPD
modes; and to achieve standby power during standby and active modes.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0]
are affected. When only UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any
external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
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Table 24. Bus Operations—Burst Mode
CLK
(Note 1) ADV#
LB#/
UB#
WAIT
(Note 2)
DQ[15:0]
(Note 3)
MODE
POWER
Active
Active
Standby
Idle
CE#
L
OE#
L
WE#
CRE
NOTES
4
Async Read
Async Write
Standby
X
X
X
X
L
L
H
L
L
L
L
L
L
L
Low-Z
Low-Z
High-Z
Low-Z
Data-Out
Data-In
High-Z
X
L
X
4
X
X
H
X
X
X
X
X
5, 6
4, 6
No Operation
L
X
Initial Burst Read
Initial Burst Write
Active
Active
L
L
L
L
X
H
H
L
L
L
L
Low-Z
Low-Z
Data-Out
Data-In
4, 8
4, 8
X
Data-In or
Data-Out
Burst Continue
Burst Suspend
Active
Active
Active
H
X
L
L
L
L
X
H
H
X
X
L
L
L
X
X
X
Low-Z
Low-Z
Low-Z
4, 8
4, 8
8
X
X
High-Z
High-Z
Configuration
Register
H
Deep
Power-Down
DPD
X
H
X
X
X
X
High-Z
High-Z
7
Notes:
1. CLK may be HIGH or LOW, but must be static during asynchronous read, synchronous write, burst suspend, and
DPD modes; and to achieve standby power during standby and active modes.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0]
are affected. When only UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any
external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
Functional Description
The CellularRAM bus interface supports both asynchronous and burst mode
transfers. Page mode accesses are also included as a bandwidth-enhancing ex-
tension to the asynchronous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the
power-up initialization process. Initialization will configure the BCR and the RCR
with their default settings (see Table 25 and Table 29). VCC and VCCQ must be
applied simultaneously. When they reach a stable level at or above 1.7V, the de-
vice will require 150µs to complete its self-initialization process. During the
initialization period, CE# should remain HIGH. When initialization is complete, the
device is ready for normal operation.
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>
PU
V
= 1.7 V
t
150 µs
CC
Device ready for
normal operation
V
CC
Device Initialization
V
Q
CC
Figure 39. Power-Up Initialization Timing
Bus Operating Modes
CellularRAM products incorporate a burst mode interface found on Flash products
targeting low-power, wireless applications. This bus interface supports asynchro-
nous, page mode, and burst mode read and write transfers. The specific interface
supported is defined by the value loaded into the BCR. Page mode is controlled
by the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode
uses the industry standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#).
READ operations (Figure 40) are initiated by bringing CE#, OE#, and LB#/UB#
LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the
specified access time has elapsed. WRITE operations (Figure 41) occur when
CE#, WE#, and LB#/ UB# are driven LOW. During asynchronous WRITE opera-
tions, the OE# level is a “Don't Care,” and WE# will override OE#. The data to be
written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs
first). Asynchronous operations (page mode disabled) can either use the ADV
input to latch the address, or ADV can be driven LOW during the entire READ/
WRITE operation.
During asynchronous operation, the CLK input must be held static (HIGH or LOW,
no transitions). WAIT will be driven while the device is enabled and its state
should be ignored.
CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
t
RC
= READ Cycle Time
Don't Care
Note: ADV must remain LOW for page mode operation.
Figure 40. READ Operation (ADV# LOW)
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CE#
OE#
WE#
ADDRESS
Address Valid
Data Valid
DATA
LB#/UB#
t
= WRITE Cycle Time
WC
Don't Care
Figure 41. WRITE Operation (ADV# LOW)
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous
READ operation. In page mode-capable products, an initial asynchronous read
access is performed, then adjacent addresses can be read quickly by simply
changing the low-order address. Addresses A[3:0] are used to determine the
members of the 16-address CellularRAM page. Addresses A[4] and higher must
remain fixed during the entire page mode access. Figure 42 shows the timing for
a page mode access. Page mode takes advantage of the fact that adjacent ad-
dresses can be read in a shorter period of time than random addresses. WRITE
operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be held LOW.
CE# must be driven HIGH upon completion of a page mode access. WAIT will be
driven while the device is enabled and its state should be ignored. Page mode is
enabled by setting RCR[7] to HIGH. WRITE operations do not include comparable
page mode functionality. ADV must be driven LOW during all page mode read
accesses.
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CE#
OE#
WE#
ADDRESS
ADD[0]
ADD[1] ADD[2] ADD[3]
t
AA
t
t
t
APA
APA
APA
D[0]
D[1]
D[2]
D[3]
DATA
LB#/UB#
Don't Care
Figure 42. Page Mode READ Operation (ADV# LOW)
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE opera-
tions. Burst operations consist of a multi-clock sequence that must be performed
in an ordered fashion. After CE# goes LOW, the address to access is latched on
the rising edge of the next clock that ADV# is LOW. During this first clock rising
edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH,
Figure 43) or WRITE (WE# = LOW, Figure 44).
The size of a burst can be specified in the BCR either as a fixed length or contin-
uous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous
bursts have the ability to start at a specified address and burst through the entire
memory.
The latency count stored in the BCR defines the number of clock cycles that
elapse before the initial data value is transferred between the processor and Cel-
lularRAM device.
The WAIT output asserts as soon as a burst is initiated, and de-asserts to indicate
when data is to be transferred into (or out of) the memory. WAIT will again be
asserted if the burst crosses a row boundary. Once the CellularRAM device has
restored the previous row's data and accessed the next row, WAIT will be deas-
serted and the burst can continue (see Figure 64).
To access other devices on the same bus without the timing penalty of the initial
latency for a new burst, burst mode can be suspended. Bursts are suspended by
stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the
data bus while the burst is suspended, OE# should be taken HIGH to disable the
CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT out-
put will continue to be active, and as a result no other devices should directly
share the WAIT connection to the controller. To continue the burst sequence, OE#
is taken LOW, then CLK is restarted after valid data is available on the bus.
See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on
the maximum CE# LOW time during burst operations. If a burst suspension will
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cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and
the burst restarted with a new CE# LOW/ADV# LOW cycle.
CLK
Address
Valid
A[22:0]
ADV#
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2]
D[3]
Legend:
READ Burst Identified
(WE# = HIGH)
Don't care
Undefined
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted
during delay.
Figure 43. Burst Mode READ (4-word burst)
CLK
Address
Valid
A[22:0]
ADV#
Latency Code 2 (3 clocks), variable
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2]
D[3]
Legend:
Don't care
WRITE Burst Identified
(WE# = LOW)
Note: Non-default BCR settings: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted
during delay.
Figure 44. Burst Mode WRITE (4-word burst)
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Mixed-Mode Operation
The device can support a combination of synchronous READ and asynchronous
WRITE operations when the BCR is configured for synchronous operation. The
asynchronous WRITE operation requires that the clock (CLK) remain static (HIGH
or LOW) during the entire sequence. The ADV# signal can be used to latch the
target address, or it can remain LOW during the entire WRITE operation. CE# can
remain LOW when transitioning between mixed-mode operations with fixed la-
tency enabled. Note that the tCKA period is the same as a READ or WRITE cycle.
This time is required to ensure adequate refresh. Mixed-mode operation facili-
tates a seamless interface to legacy burst mode Flash memory controllers. See
Figure 72 for the “Asynchronous WRITE Followed by Burst READ” timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, sys-
tem-level WAIT signal (see Figure 45 below). The shared WAIT signal is used by
the processor to coordinate transactions with multiple memories on the synchro-
nous bus.
External
Pull-Up/
Pull-Down
Resistor
CellularRAM
WAIT
READY
WAIT
WAIT
Other
Other
Device
Device
Processor
Figure 45. Wired or WAIT Configuration
Once a READ or WRITE operation has been initiated, WAIT goes active to indicate
that the CellularRAM device requires additional time before data can be trans-
ferred. For READ operations, WAIT will remain active until valid data is output
from the device. For WRITE operations, WAIT will indicate to the memory control-
ler when data will be accepted into the CellularRAM device. When WAIT
transitions to an inactive state, the data burst will progress on successive clock
edges.
CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT config-
uration BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data
corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after
WAIT de-asserts, and for row boundary crossings, start one cycle after the WAIT
signal asserts.)
When using variable initial access latency (BCR[14] = 0), the WAIT output per-
forms an arbitration role for READ or WRITE operations launched while an on-chip
refresh is in progress. If a collision occurs, the WAIT pin is asserted for additional
clock cycles until the refresh has completed (see Figure 46 and Figure 47). When
the refresh operation has completed, the READ or WRITE operation will continue
normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses the
boundary between 128-word rows. The WAIT assertion allows time for the new
row to be accessed, and permits any pending refresh operations to be performed.
WAIT will be asserted but should be ignored during asynchronous READ and
WRITE, and page READ operations.
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LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data transfers. During
READ operations, the enabled byte(s) are driven onto the DQs. The DQs associ-
ated with a disabled byte are put into a High-Z state during a READ operation.
During WRITE operations, any disabled bytes will not be transferred to the RAM
array and the internal value will remain unchanged. During an asynchronous
WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#,
LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device
will disable the data bus from receiving or transmitting data. Although the device
will seem to be deselected, it remains in an active mode as long as CE# remains
LOW.
V
V
IH
IL
CLK
A[22:0]
ADV#
V
V
IH
IL
Address
Valid
V
V
IH
IL
V
V
IH
IL
CE#
OE#
V
V
IH
IL
V
V
IH
IL
WE#
V
V
IH
IL
LB#/UB#
High-Z
V
V
OH
OL
WAIT
V
V
OH
OL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 46. Refresh Collision During READ Operation
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V
V
IH
IL
CLK
A[22:0]
ADV#
V
V
IH
IL
Address
Valid
V
V
IH
IL
V
V
IH
IL
CE#
OE#
V
V
IH
IL
V
V
IH
IL
WE#
V
V
IH
IL
LB#/UB#
High-Z
V
V
OH
OL
WAIT
V
V
OH
OL
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
Additional WAIT states inserted to allow refresh completion.
Legend:
Don't care
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 47. Refresh Collision During WRITE Operation
Low-Power Operation
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary
to perform the DRAM refresh operation. Standby operation occurs when CE# is
HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE
operation, or when the address and control inputs remain static for an extended
period of time. This mode will continue until a change occurs to the address or
control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate de-
pending on the device operating temperature. DRAM technology requires
increasingly frequent refresh operation to maintain data integrity as tempera-
tures increase. More frequent refresh is required due to increased leakage of the
DRAM capacitive storage elements as temperatures rise. A decreased refresh rate
at lower temperatures will facilitate a savings in standby current.
TCR allows for adequate refresh at four different temperature thresholds (+15°C,
+45°C, +70°C, and +85°C). The setting selected must be for a temperature
higher than the case temperature of the CellularRAM device. For example, if the
case temperature is 50°C, the system can minimize self refresh current con-
sumption by selecting the +7°0C setting. The +15°C and +45°C settings would
result in inadequate refreshing and cause data corruption.
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Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total
memory array. This feature enables the device to reduce standby current by re-
freshing only that part of the memory array required by the host system. The
refresh options are full array, one-half array, one-quarter array, three-quarter ar-
ray, or none of the array. The mapping of these partitions can start at either the
beginning or the end of the address map (see Table 30). READ and WRITE oper-
ations to address ranges receiving refresh will not be affected. Data stored in
addresses not receiving refresh will become corrupted. When re-enabling addi-
tional portions of the array, the new portions are available immediately upon
writing to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode
is used if the system does not require the storage provided by the CellularRAM
device. Any stored data will become corrupted when DPD is enabled. When re-
fresh activity has been re-enabled by rewriting the RCR, the CellularRAM device
will require 150µs to perform an initialization procedure before normal operations
can resume. During this 150µs period, the current consumption will be higher
than the specified standby levels, but considerably lower than the active current
specification.
DPD cannot be enabled or disabled by writing to the RCR using the software ac-
cess sequence; the RCR should be accessed using CRE instead.
Configuration Registers
Two user-accessible configuration registers define the device operation. The bus
configuration register (BCR) defines how the CellularRAM interacts with the sys-
tem memory bus and is nearly identical to its counterpart on burst mode Flash
devices. The refresh configuration register (RCR) is used to control how refresh
is performed on the DRAM array. These registers are automatically loaded with
default settings during power-up, and can be updated any time the devices are
operating in a standby state.
Access Using CRE
The configuration registers can be written to using either a synchronous or an
asynchronous operation when the configuration register enable (CRE) input is
HIGH (see Figure 48 and Figure 49). When CRE is LOW, a READ or WRITE oper-
ation will access the memory array. The register values are written via address
pins A[21:0]. In an asynchronous WRITE, the values are latched into the config-
uration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first;
LB# and UB# are “Don’t Care.” The BCR is accessed when A[19] is HIGH; the
RCR is accessed when A[19] is LOW. For reads, address inputs other than A[19]
are “Don’t Care,” and register bits 15:0 are output on DQ[15:0].
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A[22:0]
(except A19)
ADDRESS
ADDRESS
OPCODE
t
t
AVH
AVS
Select Control Register
A19
(Note)
CRE
t
AVS
t
AVH
t
VPH
ADV#
t
VP
t
CBPH
Initiate Control Register Access
CE#
OE#
t
CW
t
WP
Write Address
Bus Value to
Control Register
WE#
LB#/UB#
DQ[15:0]
DATA VALID
Legend:
Don't care
Note: A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
Figure 48. Configuration Register WRITE, Asynchronous Mode Followed by READ
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CLK
Latch Control Register Value
OPCODE
A[22:0]
(except A19)
ADDRESS
ADDRESS
t
HD
Latch Control Register Address
t
SP
SP
A19
(Note 2)
t
CRE
t
t
HD
t
SP
ADV#
HD
t
CBPH
(Note 3)
t
CSP
CE#
OE#
t
SP
WE#
t
HD
LB#/UB#
t
CEW
WAIT
High-Z
High-Z
DATA
VALID
DQ[15:0]
Legend:
Don't care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused
by refresh collisions require a corresponding number of additional CE# LOW cycles.
Figure 49. Configuration Register WRITE, Synchronous Mode Followed by READ0
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory
bus. Page mode operation is enabled by a bit contained in the RCR. Table 25
below describes the control bits in the BCR. At power up, the BCR is set to 9D4Fh.
October 4, 2004 cellRAM_00_A0
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The BCR is accessed using CRE and A[19] HIGH.
Table 25. Bus Configuration Register Definition
A[22:20]
A19
A[18:16]
A15
A14
A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2 A1 A0
22–20
19
18–16
15
14
13 12
11
10
9
8
7
6
5
4
3
2
1
0
Burst
Wrap
Impedance (BW)
(Note)
Burst
Length
(BL)
WAIT
Register
Select
Operating
Mode
Initial
Latency
Latency
Counter
WAIT
Polarity
Output
Reserved
Reserved
Reserved Configuration Reserved Reserved
(WC)
(Note)
All must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Setting is ignored
Output Impedance
BCR[5] BCR[4]
0
0
1
1
0
1
0
1
Full Drive (default)
1/2 Drive
1/4 Drive
Reserved
BCR[13] BCR[12] BCR[11]
Latency Counter
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Code 0–Reserved
Code 1–Reserved
Code 2
BCR[3]
Burst Wrap (Note)
0
1
Burst wraps within the burst length
Burst no wrap (default)
Code 3 (Default)
Code 4
Code 5
Code 6
Code 7–Reserved
BCR[8]
WAIT Configuration
Asserted during delay
0
1
Asserted one data cycle before delay (default)
BCR[10] WAIT Polarity
0
1
Active LOW
Active HIGH (default)
BCR[15]
Operating Mode
Burst Length (Note)
BCR[2] BCR[1] BCR[0]
0
1
Synchronous burst access mode
Asynchronous access mode (default)
0
0
0
1
0
1
0
1
1
4 words
1
8 words
1
16 words
Register Select
BCR[19]
1
Continuous burst (default)
0
1
Select RCR
Select BCR
Others
Reserved
Note: Burst wrap and length apply to READ operations only.
129
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Table 26. Sequence and Burst Length
4-WORD
BURST
ADDRESS LENGTH
STARTING
8-WORD BURST
LENGTH
CONTINUOUS
BURST
BURST WRAP
16-WORD BURST LENGTH
BCR[3] WRAP (DECIMAL) LINEAR
LINEAR
LINEAR
LINEAR
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11-…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13-…
…
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
…
2
3
4
5
0
Yes
6
7
…
14
15
0
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
5-6-7-8-9-10-11-12-13-…-15-16-17-18-19-20
6-7-8-9-10-11-12-13-14-…-16-17-18-19-20-21
7-8-9-10-11-12-13-14-…-17-18-19-20-21-22
…
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21…
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12…
7-8-9-10-11-12-13…
…
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
1
2
2-3-4-5-6-7-8-9
3
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
4
5
1
No
6
7
…
14
15
14-15-16-17-18-19-…-23-24-25-26-27-28-29
5-16-17-18-19-20-…-24-25-26-27-28-29-30
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
Burst Length (BCR[2:0]): Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ
operations. The device supports a burst length of 4, 8, or 16 words. The device
can also be set in continuous burst mode where data is accessed sequentially
without regard to address boundaries. Enabling burst no-wrap with BCR[3] = 1
overrides the burst-length setting.
Burst Wrap (BCR[3]): Default = No Wrap
The burst-wrap option determines if a 4-, 8-, or 16-word READ burst wraps within
the burst length or steps through sequential addresses. If the wrap option is not
enabled, the device accesses data from sequential addresses without regard to
burst boundaries. When continuous burst operation is selected, the internal ad-
dress wraps to 000000h if the burst goes past the last address. Enabling burst
nowrap (BCR[3] = 1) overrides the burst-length setting.
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Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength
The output driver strength can be altered to full, one-half, or one-quarter
strength to adjust for different data bus loading scenarios. The reduced-strength
options are intended for stacked chip (Flash + CellularRAM) environments when
there is a dedicated memory bus. The reduced-drive-strength option minimizes
the noise generated on the data bus during READ operations. Normal output drive
strength should be selected when using a discrete CellularRAM device in a more
heavily loaded data bus environment. Outputs are configured at full drive
strength during testing.
Table 27. Output Impedance
BCR[5]
BCR[4]
DRIVE STRENGTH
0
0
1
1
0
1
0
1
Full
1/2
1/4
Reserved
WAIT Configuration (BCR[8]): Default = WAIT Transitions One
Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between
the asserted and the de-asserted state with respect to valid data presented on
the data bus. The memory controller will use the WAIT signal to coordinate data
transfer during synchronous READ and WRITE operations. When BCR[8] = 0,
data will be valid or invalid on the clock edge immediately after WAIT transitions
to the de-asserted or asserted state, respectively (Figure 50 and Figure 52).
When A8 = 1, the WAIT signal transitions one clock period prior to the data bus
going valid or invalid (Figure 51).
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH
or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-
down resistor to maintain the de-asserted state.
CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data[1]
Data immediately valid (or invalid)
Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 52.
Figure 50. WAIT Configuration (BCR[8] = 0)
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CLK
WAIT
High-Z
DQ[15:0]
Data[0]
Data valid (or invalid) after one clock delay
Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 52.
Figure 51. WAIT Configuration (BCR[8] = 1)
CLK
BCR[8]
= 0
WAIT
DATA VALID IN CURRENT CYCLE
BCR[8]
= 1
WAIT
DATA VALID IN NEXT CYCLE
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
D[4]
Legend:
Don't care
Note: Non-default BCR setting: WAIT active LOW.
Figure 52. WAIT Configuration During Burst Operation
Latency Counter (BCR[13:11]): Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the begin-
ning of a READ or WRITE operation and the first data value transferred. Latency
codes from two (three clocks) to six (seven clocks) are allowed (see Table 28 and
Figure 53 below).
Table 28. Variable Latency Configuration Codes
LATENCY (Note)
REFRESH
MAX INPUT CLK FREQUENCY (MHz)
LATENCY
BCR[13:11]
010
CONFIGURATION CODE
NORMAL
COLLISION
70ns/80 MHz
85ns/66 MHz
2 (3 clocks)
3 (4 clocks)—default
4 (5 clocks)
2
3
4
4
6
8
75 (13.0ns)
44 (22.7ns)
011
80 (12.5ns)
66 (15.2ns)
100
Note: Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is trans-
ferred on the next clock cycle.
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V
IH
CLK
V
IL
V
IH
A[21:0]
Valid Address
V
IL
V
IH
ADV#
A/DQ[15:0]
A/DQ[15:0]
A/DQ[15:0]
V
IL
Code 2
Code 3
Code 4
V
V
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
(Default)
V
V
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
V
OH
Valid
Output
Valid
Output
Valid
Output
V
OL
Legend:
Don't care
Undefined
Figure 53. Latency Counter (Variable Initial Latency, No Refresh Collision)
Operating Mode (BCR[15]): Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default
asynchronous mode of operation.
Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device per-
forms its transparent self refresh. Altering the refresh parameters can
dramatically reduce current consumption during standby mode. Page mode con-
trol is also embedded into the RCR. Table 29 below describes the control bits used
in the RCR. At power-up, the RCR is set to 0070h. The RCR is accessed using CRE
and A[19] LOW.
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Table 29. Refresh Configuration Register Mapping
A[22:20]
A19
A[18:8]
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
22–20
Reserved
19
18–8
Reserved
7
6
5
4
3
2
1
0
Read Configuration
Register
Register
Select
Page
TCR
DPD
Reserved
PAR
Must be set to "0"
All must be set to "0"
All must be set to "0"
RCR[19] Register Select
RCR[2] RCR[1] RCR[0] Refresh Coverage
0
1
Select RCR
Select BCR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
RCR[7]
Page Mode Enable/Disable
Page Mode Disabled (default)
Page Mode Enable
0
1
Top 1/2 array
Top 1/4 array
Maximum Case Temp
RCR[6]
RCR[5]
Top 3/4 array
1
1
0
1
0
+85ºC (default)
+70ºC
0
0
1
RCR[4]
Deep Power-Down
DPD Enable
+45ºC
0
1
+15ºC
DPD Disable (default)
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part
of the memory array required by the host system. The refresh options are full ar-
ray, one-half array, one-quarter array, three-quarters array, or none of the array.
The mapping of these partitions can start at either the beginning or the end of
the address map (see Table 30 through Table 32).
Table 30. 128Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
Full die
ADDRESS SPACE
000000h–7FFFFFh
000000h–3FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
0
SIZE
DENSITY
128Mb
64Mb
32Mb
16Mb
0Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
4 Meg x 16
2 Meg x 16
1 Meg x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
One-half of die
One-quarter of die
One-eighth of die
400000h–7FFFFFh
600000h–7FFFFFh
700000h–7FFFFFh
64Mb
32Mb
16Mb
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Table 31. 64Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
Full die
ADDRESS SPACE
000000h–3FFFFFh
000000h–2FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
0
SIZE
DENSITY
64Mb
48Mb
32Mb
16Mb
0Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4 Meg x 16
3 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
3 Meg x 16
2 Meg x 16
1 Meg x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
One-half of die
One-quarter of die
One-eighth of die
100000h–3FFFFFh
200000h–3FFFFFh
300000h–3FFFFFh
48Mb
32Mb
16Mb
Table 32. 32Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
Full die
ADDRESS SPACE
000000h–1FFFFFh
000000h–17FFFFh
000000h–0FFFFFh
000000h–07FFFFh
0
SIZE
DENSITY
32Mb
24Mb
16Mb
8Mb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 Meg x 16
1.5 Meg x 16
1 Meg x 16
512K x 16
0 Meg x 16
1.5 Meg x 16
1 Meg x 16
512K x 16
One-half of die
One-quarter of die
One-eighth of die
None of die
0Mb
One-half of die
One-quarter of die
One-eighth of die
080000h–1FFFFFh
100000h–1FFFFFh
180000h–1FFFFFh
24Mb
16Mb
8Mb
Deep Power-Down (RCR[4]): Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This
mode is used if the system does not require the storage provided by the Cellular-
RAM device. Any stored data will become corrupted when DPD is enabled. When
refresh activity has been re-enabled, the CellularRAM device will require 150µs
to perform an initialization procedure before normal operations can resume.
Deep power-down is enabled when RCR[4] = 0, and remains enabled until
RCR[4] is set to “1.”
Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation
The TCR bits allow for adequate refresh at four different temperature thresholds
(+15ºC, +45ºC, +70ºC, and +85ºC). The setting selected must be for a temper-
ature higher than the case temperature of the CellurlarRAM device. If the case
temperature is +50ºC, the system can minimize self refresh current consumption
by selecting the +70ºC setting. The +15ºC and +45ºC settings would result in
inadequate refreshing and cause data corruption.
Page Mode Operation (RCR[7]): Default = Disabled
The page mode operation bit determines whether page mode is enabled for asyn-
chronous READ operations. In the power-up default state, page mode is disabled.
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Absolute Maximum Ratings
Voltage to Any Ball Except VCC, VCC
Q
Relative to VSS . . . . . -0.50V to (4.0V or VCCQ + 0.3V, whichever is less)
Voltage on VCC Supply Relative to VSS . . . . . . . . . . . . . . . . -0.2V to +2.45V
Voltage on VCCQ Supply Relative to VSS . . . . . . . . . . . . . . . . -0.2V to +2.45V
Storage Temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . -55ºC to +150ºC
Operating Temperature (case)
Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25ºC to +85ºC
*Stresses greater than those listed may cause permanent damage to the device. This
is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
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DC Characteristics
Table 33. Electrical Characteristics and Operating Conditions
Description
Conditions
Symbol
Min
1.70
Max
1.95
Units
V
Notes
Supply Voltage
VCC
W: 1.8V
J: 1.5V
1.70
1.95
V
I/O Supply Voltage
VCCQ
1.35
1.65
V
Input High Voltage
Input Low Voltage
VIH
VIL
VCCQ - 0.4
-0.20
VCCQ + 0.2
0.4
V
2
3
4
4
V
Output High Voltage
Output Low Voltage
Input Leakage Current
IOH = -0.2mA
IOL = +0.2mA
VOH
VOL
ILI
0.80 VCC
Q
V
0.20 VCC
Q
V
VIN = 0 to VCC
Q
1
µA
OE# = VIH or
Chip Disabled
Output Leakage Current
ILO
1
µA
Operating Current
-70
-85
25
20
Asynchronous Random READ
Asynchronous Page READ
Initial Access, Burst READ
Continuous Burst READ
VIN = VCCQ or 0V
Chip Enabled,
IOUT = 0
ICC
1
mA
5
5
-70
-85
15
12
80 MHz
66 MHz
80 MHz
66 MHz
-70
35
VIN = VCCQ or 0V
Chip Enabled,
IOUT = 0
30
ICC1
mA
18
15
25
VIN = VCCQ or 0V
Chip Enabled
WRITE Operating Current
ICC2
mA
µA
-85
20
128 M
64 M
180
120
110
VIN = VCCQ or 0V
Standby Current
ISB
6
CE# = VCC
Q
32 M
Notes:
1. Wireless Temperature (-25ºC < TC < +85ºC); Industrial Temperature (-40ºC < TC < +85ºC).
2. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.
3. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions.
4. BCR[5:4] = 00b.
5. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the
current required to drive output capacitance expected in the actual system.
6. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C. To achieve low standby current,
all inputs must be driven to either VCCQ or VSS
.
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Table 34. Temperature Compensated Refresh Specifications and Conditions
Standard
Power
Te m p e rat ure (No Desig.)
Max Case
Description
Conditions
Symbol
Density
Units
+85
+70
+45
+15
+85
+70
+45
+15
°
°
°
°
°
°
°
°
C
C
C
C
C
C
C
C
120
105
85
64 Mb
70
Temperature Compensated
Refresh Standby Current
VIN = VCCQ or 0V,
ITCR
µA
CE# = VCC
Q
110
95
32 Mb
80
70
Note: IPAR (MAX) values measured with TCR set to 85°C.
Table 35. Partial Array Refresh Specifications and Conditions
Standard
Power
Array
Description
Conditions
Symbol
Density
Partition
Full
1/2
1/4
1/8
0
(No Desig.)
Units
120
115
110
105
70
64 Mb
Full
1/2
1/4
1/8
0
110
105
100
95
Partially Array Refresh Standby
Current
VIN = VCCQ or 0V,
IPAR
µA
CE# = VCC
Q
32 Mb
70
Full
0
180
50
128 Mb
Note:IPAR (MAX) values measured with TCR set to 85°C.
Table 36. Deep Power-Down Specifications
Description
Conditions
Symbol
Typ
Units
µA
Deep Power-down
VIN = VCCQ or 0V; +25°C; VCC = 1.8V
IZZ
10
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AC Characteristics
V
CC
Q
V
Q
/2
V
Q/2
CC
(Note 2)
CC
Input
(Note 1)
Output
Test Points
(Note 3)
V
SS
Notes:
1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns.
2. Input timing begins at VCCQ/2.
3. Output timing ends at VCCQ/2.
Figure 54. AC Input/Output Reference Waveform
V
Q
CC
R1
Test Point
DUT
30pF
R2
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
Figure 55. Output Load Circuit
Table 37. Output Load Circuit
V
Q
R1/R2
2.7K
CC
1.8V
Ω
139
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
Table 38. Asynchronous READ Cycle Timing Requirements
85ns/66 MHz
70ns/80 MHz
Units
Notes
Parameter
Address Access Time
Symbol
tAA
Min
Max
85
Min
Max
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADV# Access Time
tAADV
tAPA
tAVH
tAVS
tBA
85
70
Page Access Time
25
20
Address Hold from ADV# HIGH
Address Setup to ADV# HIGH
LB#/UB# Access Time
5
5
10
10
85
8
70
8
LB#/UB# Disable to DQ High-Z Output
LB#/UB# Enable to Low-Z Output
CE# HIGH between Subsequent Mixed-Mode Operations
Maximum CE# Pulse Width
CE# LOW to WAIT Valid
tBHZ
tBLZ
tCBPH
tCEM
tCEW
tCO
4
3
10
5
10
5
4
4
2
1
10
10
5
7.5
85
1
10
10
5
7.5
70
Chip Select Access Time
CE# LOW to ADV# HIGH
tCVS
tHZ
Chip Disable to DQ and WAIT High-Z Output
Chip Enable to Low-Z Output
Output Enable to Valid Output
Output Hold from Address Change
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Page Cycle Time
8
20
8
8
20
8
4
3
tLZ
tOE
tOH
tOHZ
tOLZ
tPC
4
3
5
5
25
85
10
10
20
70
10
10
READ Cycle Time
tRC
ADV# Pulse Width LOW
tVP
ADV# Pulse Width HIGH
tVPH
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. See “How Extended Timings Impact CellularRAM™ Operation” below.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 55. The Low-Z timings measure a
4. 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL
.
5. Low-Z to High-Z timings are tested with the circuit shown in Figure 55. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
October 4, 2004 cellRAM_00_A0
CellularRAM
140
P r e l i m i n a r y
Table 39. Burst READ Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Parameter
Burst to READ Access Time (Variable Latency)
CLK to Output Delay
Symbol
tABA
tACLK
tAVS
tBOE
tCBPH
tCEW
tCLK
tCSP
tHD
Min
Max
35
9
Min
Max
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
11
Address Setup to ADV# HIGH
Burst OE# LOW to Output Delay
CE# HIGH between Subsequent Mixed-Mode Operations
CE# LOW to WAIT Valid
10
10
20
20
5
1
5
1
7.5
7.5
CLK Period
12.5
4
15
5
CE# Setup Time to Active CLK Edge
Hold Time from Active CLK Edge
Chip Disable to DQ and WAIT High-Z Output
CLK Rise or Fall Time
2
2
tHZ
8
1.6
9
8
1.6
11
8
2
tKHKL
tKHTL
tKHZ
tKLZ
tKOH
tKP
CLK to WAIT Valid
CLK to DQ High-Z Output
3
2
2
3
8
3
2
2
3
CLK to Low-Z Output
5
5
Output HOLD from CLK
CLK HIGH or LOW Time
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Setup Time to Active CLK Edge
tOHZ
tOLZ
tSP
8
8
2
3
5
3
5
3
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 55. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 55. The Low-Z timings measure a 100mV
transition away from the High-Z (VCCQ/2) level toward either VOH or VOL
.
141
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
Table 40. Asynchronous WRITE Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
Notes
Address and ADV# LOW Setup Time
Address Hold from ADV# Going HIGH
Address Setup to ADV# Going HIGH
Address Valid to End of Write
LB#/UB# Select to End of Write
Maximum CE# Pulse Width
CE# LOW to WAIT Valid
tAVH
tAVS
tAW
5
5
ns
10
70
70
10
85
85
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBW
tCEM
tCEW
tCKA
tCVS
tCW
tDH
4
4
1
1
7.5
1
7.5
Async Address-to-Burst Transition Time
CE# Low to ADV# HIGH
70
10
70
0
85
10
85
0
Chip Enable to End of Write
Data Hold from Write Time
Data WRITE Setup Time
tDW
tHZ
23
23
1
Chip Disable to WAIT High-Z Output
Chip Enable to Low-Z Output
End WRITE to Low-Z Output
ADV# Pulse Width
8
8
tLZ
10
5
10
5
3
3
tOW
tVP
tVPH
tVS
10
10
70
70
10
10
85
85
ADV# Pulse Width HIGH
ADV# Setup to End of WRITE
WRITE Cycle Time
tWC
tWHZ
tWP
WRITE to DQ High-Z Output
WRITE Pulse Width
8
8
2
1
46
10
0
55
10
0
WRITE Pulse Width HIGH
tWPH
tWR
WRITE Recovery Time
Notes:
1. See “How Extended Timings Impact CellularRAM™ Operation” below.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 55. The High-Z timings measure a 100mV
transition from either VOH or VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 55. The Low-Z timings measure a 100mV
transition away from the High-Z (VCCQ/2) level toward either VOH or VOL
.
Table 41. Burst WRITE Cycle Timing Requirements
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
tCBPH
tCEW
Min
5
Max
Min
5
Max
Units
ns
Notes
CE# HIGH between Subsequent Mixed-Mode Operations
CE# LOW to WAIT Valid
1
7.5
1
7.5
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
142
P r e l i m i n a r y
Table 41. Burst WRITE Cycle Timing Requirements (Continued)
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
tCLK
tCSP
tHD
Min
12.5
4
Max
Min
15
5
Max
Units
ns
Notes
Clock Period
CE# Setup to CLK Active Edge
Hold Time from Active CLK Edge
Chip Disable to WAIT High-Z Output
CLK Rise or Fall Time
ns
2
2
ns
tHZ
8
1.6
9
8
ns
tKHKL
tKHTL
tKP
1.6
11
ns
Clock to WAIT Valid
ns
CLK HIGH or LOW Time
Setup Time to Activate CLK Edge
3
3
3
3
ns
tSP
ns
Timing Diagrams
V
CC
(MIN)
V
, V Q = 1.7V
CC CC
t
PU
Device ready for
normal operation
Figure 56. Initialization Period
Table 42. Initialization Timing Parameters
70ns/80 MHz
85ns/66 MHz
Parameter
Symbol
Min
Max
Min
Max
Units
Notes
Initialization Period (required before normal operations)
tPU
150
150
µs
143
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
RC
V
V
IH
IL
VALID ADDRESS
A[22:0]
t
AA
V
V
IH
IL
ADV#
CE#
t
t
CBPH
HZ
V
V
IH
IL
t
CO
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
BLZ
t
LZ
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
t
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 57. Asynchronous READ
Table 43. Asynchronous READ Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
70
8
Min
Max
85
85
8
Units
ns
tBA
ns
tBHZ
tBLZ
ns
10
5
10
5
ns
tCBPH
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
144
P r e l i m i n a r y
Table 43. Asynchronous READ Timing Parameters (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tCEW
tCO
Min
Max
7.5
70
8
Min
Max
Units
ns
1
1
7.5
ns
tHZ
8
ns
tLZ
10
10
ns
tOE
20
8
20
8
ns
tOHZ
tOLZ
tRC
ns
5
5
ns
70
85
ns
145
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AA
t
t
AVH
AVS
t
VPH
V
V
IH
IL
ADV#
t
AADV
t
VP
t
t
CVS
t
CBPH
HZ
V
V
IH
IL
CE#
t
CO
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
BLZ
t
LZ
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
t
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 58. Asynchronous READ Using ADV#
Table 44. Asynchronous READ Timing Parameters Using ADV#
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
Min
Max
85
Units
ns
tAADV
70
85
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
146
P r e l i m i n a r y
Table 44. Asynchronous READ Timing Parameters Using ADV# (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tCVS
tAVH
tAVS
tBA
Min
10
5
Max
Min
10
5
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
70
8
85
8
tBHZ
tBLZ
tCBPH
tCEW
tCO
10
5
10
5
1
7.5
70
1
7.5
85
tCVS
tHZ
10
10
10
10
8
8
tLZ
tOE
20
8
20
8
tOHZ
tOLZ
tVP
5
5
10
10
10
10
tVPH
147
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
RC
V
V
IH
IL
A[22:0]
A[3:0]
VALID ADDRESS
V
V
IH
IL
VALID
VALID
VALID
ADDRESS
VALID ADDRESS
ADDRESS
ADDRESS
t
t
PC
AA
V
V
IH
IL
ADV#
t
t
CEM
CBPH
t
t
t
CBPH
CO
HZ
V
V
IH
IL
CE#
t
t
BHZ
BA
V
V
IH
IL
LB#/UB#
t
t
OHZ
OE
V
V
V
V
IH
IL
IH
IL
OE#
WE#
t
OLZ
t
t
APA
BLZ
t
t
OH
LZ
V
V
OH
OL
High-Z
t
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
t
HZ
CEW
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Undefined
Figure 59. Page Mode READ
Table 45. Asynchronous READ Timing Parameters—Page Mode Operation
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
20
70
8
Min
Max
85
25
85
8
Units
ns
tAPA
tBA
ns
ns
tBHZ
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
148
P r e l i m i n a r y
Table 45. Asynchronous READ Timing Parameters—Page Mode Operation (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tBLZ
tCBPH
tCEM
tCEW
tCO
Min
10
5
Max
Min
10
5
Max
Units
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
7.5
70
8
4
7.5
85
8
1
1
tHZ
tLZ
10
5
10
5
tOE
20
8
20
8
tOH
tOHZ
tOLZ
tPC
5
5
20
70
25
85
tRC
149
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
t
KP
t
KP
CLK
V
V
IH
IL
CLK
t
KHKL
t
t
SP
HD
V
V
IH
IL
A[22:0]
ADV#
VALID ADDRESS
t
t
SP
HD
V
V
IH
IL
t
HD
t
t
HZ
t
ABA
CSP
V
V
IH
IL
CE#
OE#
t
t
OHZ
BOE
V
V
IH
IL
t
OLZ
t
t
SP
SP
HD
V
V
IH
IL
WE#
t
t
HD
V
V
IH
IL
LB#/UB#
t
CEW
t
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
t
KOH
ACLK
V
V
OH
OL
High-Z
DQ[15:0]
VALID OUTPUT
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 60. Single-Access Burst READ Operation—Variable Latency
Table 46. Burst READ Timing Parameters—Single Access, Variable Latency
70ns/80 MHz
85ns/66 MHz
Symbol
tABA
Min
Max
35
9
Min
Max
55
Units
ns
tACLK
11
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
150
P r e l i m i n a r y
Table 46. Burst READ Timing Parameters—Single Access, Variable Latency (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tBOE
tCEW
tCLK
tCSP
tHD
Min
Max
20
Min
Max
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
12.5
4
7.5
1
15
5
7.5
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
tOLZ
tSP
8
8
5
3
5
3
151
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
CLK
t
t
t
KP
KHKL
KP
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
CE#
t
t
SP
HD
V
V
IH
IL
t
t
t
t
HD
CSP
ABA
CBPH
V
V
IH
IL
t
HZ
t
t
OHZ
BOE
V
V
IH
IL
OE#
t
OLZ
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
KOH
t
ACLK
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 61. Four-word Burst READ Operation—Variable Latency
October 4, 2004 cellRAM_00_A0
CellularRAM
152
P r e l i m i n a r y
Table 47. Burst READ Timing Parameters—4-word Burst
70ns/80 MHz
85ns/66 MHz
Symbol
tABA
tACLK
tBOE
tCBPH
tCEW
tCLK
tCSP
tHD
Min
Max
35
9
Min
Max
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
tOLZ
tSP
8
8
5
3
5
3
153
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
CE#
t
t
SP
HD
V
V
IH
IL
t
t
t
HD
CSP
CBPH
V
V
IH
IL
t
HZ
t
t
OHZ
BOE
V
V
IH
IL
OE#
t
OLZ
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
KHTL
V
V
OH
OL
High-Z
High-Z
WAIT
t
KOH
t
ACLK
t
t
t
KHTL
KHTL
KHTL
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
High-Z
Legend:
READ Burst Identified
(WE# = HIGH)
Don't Care
Undefined
Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Figure 62. Four-word Burst READ Operation (with LB#/UB#)
October 4, 2004 cellRAM_00_A0
CellularRAM
154
P r e l i m i n a r y
Table 48. Burst READ Timing Parameters—4-word Burst with LB#/UB#
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
tCSP
tHD
Min
Max
9
Min
Max
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
2
2
tHZ
8
9
8
5
8
11
8
tKHTL
tKHZ
tKLZ
3
2
2
3
2
2
5
tKOH
tOHZ
tOLZ
tSP
8
8
5
3
5
3
155
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
HD
SP
V
V
IH
IL
ADV#
t
CBPH
t
t
t
CSP
HZ
V
V
IH
IL
CE#
OE#
t
OHZ
OHZ
(Note 2)
V
V
IH
IL
t
t
t
SP
HD
HD
V
V
IH
IL
WE#
t
SP
V
V
IH
IL
LB#/UB#
t
t
CEW
BOE
t
OLZ
High-Z
V
V
High-Z
IH
IL
WAIT
t
KOH
t
BOE
t
ACLK
t
OLZ
V
V
OH
OL
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data.
Figure 63. READ Burst Suspend
Table 49. Burst READ Timing Parameters—Burst Suspend
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCLK
Min
Max
9
Min
Max
11
Units
ns
20
20
ns
5
12.5
4
5
15
5
ns
ns
tCSP
ns
tHD
2
2
ns
tHZ
8
8
8
8
ns
tKOH
tOHZ
tOLZ
2
5
2
5
ns
ns
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
156
P r e l i m i n a r y
Table 49. Burst READ Timing Parameters—Burst Suspend (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
Max
Units
tSP
3
3
ns
V
CLK
V
IH
IL
t
CLK
V
IH
IL
A[22:0]
V
V
V
IH
IL
ADV#
V
V
IH
IL
LB#/UB#
V
V
IH
IL
CE#
OE#
WE#
V
V
IH
IL
V
V
IH
IL
t
t
KHTL
KHTL
V
V
OH
OL
(Note 2)
WAIT
t
t
KOH
ACLK
V
V
OH
OL
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ[15:0]
Legend:
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 64. Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition
Table 50. Burst READ Timing Parameters—BCR[8] = 0
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tCLK
Min
12.5
2
Max
Min
15
2
Max
Units
ns
9
11
ns
tKHTL
tKOH
9
11
ns
ns
157
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
AA
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
t
AS
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
WHZ
LZ
V
V
OH
OL
DQ[15:0]
OUT
t
HZ
t
CEW
High-Z
V
V
IH
IL
High-Z
WAIT
Legend:
Don't Care
Figure 65. CE#-Controlled Asynchronous WRITE
Table 51. Asynchronous WRITE Timing Parameters—CE#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
tAW
70
70
85
85
ns
tBW
ns
tCEM
4
4
µs
October 4, 2004 cellRAM_00_A0
CellularRAM
158
P r e l i m i n a r y
Table 51. Asynchronous WRITE Timing Parameters—CE#-Controlled (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tCEW
tCW
Min
1
Max
Min
1
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.5
7.5
70
0
85
0
tDH
tDW
tHZ
23
23
8
8
8
8
tLZ
10
70
10
85
tWC
tWHZ
tWP
tWPH
tWR
46
10
0
55
10
0
159
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
WC
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
t
AS
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
WHZ
LZ
V
V
OH
OL
DQ[15:0]
OUT
t
HZ
t
CEW
High-Z
V
V
IH
IL
High-Z
WAIT
Legend:
Don't Care
Figure 66. LB#/UB#-Controlled Asynchronous WRITE
Table 52. Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
tAW
70
70
85
85
ns
tBW
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
160
P r e l i m i n a r y
Table 52. Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tCEM
tCEW
tCW
Min
Max
4
Min
Max
4
Units
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
70
0
7.5
1
85
0
7.5
tDH
tDW
23
23
tHZ
8
8
8
8
tLZ
10
70
10
85
tWC
tWHZ
tWP
tWPH
tWR
46
10
0
55
10
0
161
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
WC
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
AW
t
WR
V
V
IH
IL
ADV#
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
AS
t
t
WP
WPH
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
t
OW
LZ
WHZ
V
V
OH
OL
DQ[15:0]
OUT
t
t
CEW
HZ
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Figure 67. WE#-Controlled Asynchronous WRITE
Table 53. Asynchronous WRITE Timing Parameters—WE#-Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
Max
Units
tAS
0
0
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
162
P r e l i m i n a r y
Table 53. Asynchronous WRITE Timing Parameters—WE#-Controlled (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tAW
Min
70
Max
Min
85
Max
Units
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBW
70
85
tCEM
tCEW
tCW
4
4
1
70
0
7.5
1
85
0
7.5
tDH
tDW
tHZ
23
23
8
8
8
8
tLZ
10
5
10
5
tOW
tWC
tWHZ
tWP
tWPH
tWR
70
85
46
10
0
55
10
0
163
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
V
V
IH
IL
A[22:0]
VALID ADDRESS
t
t
AVH
AVS
t
VS
t
t
VP
VPH
t
AS
V
V
IH
IL
ADV#
t
AS
t
AW
t
CEM
t
CW
V
V
IH
IL
CE#
t
BW
V
V
IH
IL
LB#/UB#
OE#
V
V
IH
IL
t
t
WPH
WP
V
V
IH
IL
WE#
t
t
DH
DW
High-Z
V
V
IH
IL
DQ[15:0]
IN
VALID
INPUT
t
t
t
OW
LZ
WHZ
V
V
OH
OL
DQ[15:0]
OUT
t
t
CEW
HZ
V
V
IH
IL
High-Z
High-Z
WAIT
Legend:
Don't Care
Figure 68. Asynchronous WRITE Using ADV#
October 4, 2004 cellRAM_00_A0
CellularRAM
164
P r e l i m i n a r y
Table 54. Asynchronous WRITE Timing Parameters Using ADV#
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVH
tAVS
tAW
tBW
tCEM
tCEW
tCW
tDH
5
5
10
70
70
10
85
85
4
4
1
70
0
7.5
1
85
0
7.5
tDW
tHZ
23
23
8
8
tLZ
10
5
10
5
tOW
tAS
0
0
tVP
10
10
70
10
10
85
tVPH
tVS
tWHZ
tWP
8
8
46
10
55
10
tWPH
165
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
KHKL
t
t
KP
t
KP
CLK
V
V
IH
IL
CLK
t
t
SP
HD
V
V
IH
IL
Valid
Address
A[22:0]
ADV#
t
t
SP
HD
V
V
IH
IL
t
SP
t
HD
V
V
IH
IL
LB#/UB#
t
t
CSP
t
HD
CBPH
V
V
IH
IL
CE#
OE#
V
V
IH
IL
t
t
SP
HD
V
V
IH
IL
WE#
t
HZ
t
t
CEW
KHTL
High-Z
V
V
(Note 2)
IH
IL
High-Z
WAIT
t
t
HD
SP
V
V
OH
OL
DQ[15:0]
D[1]
D[2]
D[3]
D[0]
Legend:
READ Burst Identified
(WE# = LOW)
Don't Care
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst
length four; burst wrap enabled.
Figure 69. Burst WRITE Operation
October 4, 2004 cellRAM_00_A0
CellularRAM
166
P r e l i m i n a r y
Table 55. Burst WRITE Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tCBPH
tCEW
tCLK
tCSP
tHD
Min
5
Max
Min
5
Max
Units
ns
1
7.5
1
7.5
ns
12.5
4
15
5
ns
ns
2
2
ns
tHZ
8
1.6
9
8
ns
tKHKL
tKHTL
tKP
1.6
11
ns
ns
3
3
3
3
ns
tSP
ns
167
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
V
V
IH
IL
CLK
t
CLK
V
V
IH
IL
A[22:0]
ADV#
V
V
IH
IL
V
V
IH
IL
LB#/UB#
V
V
IH
IL
CE#
V
V
IH
IL
WE#
V
V
IH
IL
OE#
t
t
KHTL
KHTL
(Note 2)
V
V
OH
OL
WAIT
t
t
HD
SP
V
V
OH
OL
Valid Input
D[n+3]
Valid Input
D[n+2]
Valid Input Valid Input
DQ[15:0]
D[n]
D[n+1]
Legend:
Don't Care
END OF ROW
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status).
Figure 70. Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition
Table 56. Burst WRITE Timing Parameters—BCR[8] = 0
70ns/80 MHz
85ns/66 MHz
Symbol
tCLK
Min
12.5
2
Max
Min
15
2
Max
Units
ns
tHD
ns
tKHTL
tSP
8
3
11
3
ns
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
168
P r e l i m i n a r y
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
t
HD
SP
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
SP
t
t
HD
SP
HD
V
V
IH
IL
ADV#
t
t
HD
SP
V
V
IH
IL
LB#/UB#
CE#
t
t
t
HD
CSP
CBPH
V
V
IH
IL
(Note 2)
t
CSP
t
OHZ
V
V
IH
IL
OE#
t
SP
t
t
HD
t
SP
HD
V
V
IH
IL
WE#
t
BOE
V
V
High-Z
High-Z
OH
OL
WAIT
t
t
KOH
t
t
HD
ACLK
SP
V
V
V
High-Z
IH
IL
High-Z
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
V
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. To allow self-refresh operations to occur between transactions, CE# must remain HIGH for at least 5ns (tCBPH) to
schedule the appropriate internal refresh operation. CE# can stay LOW between burst READ and burst WRITE
operations. See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE#
LOW time (tCEM).
Figure 71. Burst WRITE Followed by Burst READ
Table 57. WRITE Timing Parameters—Burst WRITE Followed by Burst READ
70ns/80 MHz
85ns/66 MHz
Symbol
tCBPH
tCLK
Min
5
Max
Min
5
Max
Units
ns
12.5
4
20
20
15
5
20
20
ns
tCSP
tHD
ns
2
2
ns
tSP
3
3
ns
Table 58. READ Timing Parameters—Burst WRITE Followed by Burst READ
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
Min
Max
Min
Max
ns
Units
9
11
20
20
ns
ns
tCLK
12.5
15
169
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
Table 58. READ Timing Parameters—Burst WRITE Followed by Burst READ (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tCSP
tHD
Min
4
Max
Min
5
Max
Units
ns
2
2
ns
tKOH
tOHZ
tSP
2
2
ns
8
8
ns
3
3
ns
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
HD
WC
WC
CKA
SP
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
WR
AVS
AVH
AW
t
t
HD
t
SP
VPH
V
V
IH
IL
ADV#
t
t
t
VP
VS
t
t
t
BW
SP
HD
CVS
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CSP
CW
CBPH
V
V
IH
IL
(Note 2)
t
OHZ
V
V
IH
IL
OE#
t
WC
t
t
WP
t
AS
WPH
t
t
HD
SP
V
V
IH
IL
WE#
t
t
BOE
CEW
V
V
High-Z
OH
OL
WAIT
t
WHZ
t
ACLK
V
V
High-Z
V
V
High-Z
IH
IL
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DATA
DATA
t
t
t
DH
DW
KOH
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 72. Asynchronous WRITE Followed by Burst READ
October 4, 2004 cellRAM_00_A0
CellularRAM
170
P r e l i m i n a r y
Table 59. WRITE Timing Parameters—Asynchronous WRITE Followed by Burst READ
70ns/80 MHz
85ns/66 MHz
Symbol
tAVH
tAS
Min
5
Max
Min
5
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
tAVS
tAW
10
70
70
70
10
70
0
10
85
85
85
10
85
0
tBW
tCKA
tCVS
tCW
tDH
tDW
tVP
tVPH
tVS
20
10
10
70
70
23
10
10
85
85
tWC
tWHZ
tWP
8
8
46
10
0
55
10
0
tWPH
tWR
Table 60. READ Timing Parameters—Asynchronous WRITE Followed by Burst READ
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
20
20
ns
5
1
5
1
ns
7.5
7.5
ns
12.5
4
15
5
ns
tCSP
ns
tHD
2
2
ns
tKOH
tOHZ
tSP
2
2
ns
8
8
ns
3
3
ns
171
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
CLK
V
V
IH
IL
CLK
t
t
t
t
t
HD
WC
WC
CKA
SP
V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
WR
AW
t
t
HD
SP
V
V
IH
IL
ADV#
t
t
SP
t
BW
HD
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CSP
CW
CSP
V
V
IH
IL
(Note 2)
t
OHZ
V
V
IH
IL
OE#
t
WC
t
t
t
t
HD
WP
WPH
SP
V
V
IH
IL
WE#
t
t
BOE
CEW
V
V
High-Z
OH
OL
WAIT
t
t
WHZ
t
t
KOH
DW
ACLK
V
V
High-Z
V
V
High-Z
IH
IL
OH
OL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0]
DATA
DATA
t
DH
Legend:
Don't Care
Undefined
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 73. Asynchronous WRITE (ADV# LOW) Followed By Burst READ
Table 61. Asynchronous WRITE Timing Parameters—ADV# LOW
70ns/80 MHz
85ns/66 MHz
Symbol
tAW
Min
70
70
70
70
0
Max
Min
85
85
85
85
0
Max
Units
ns
tBW
ns
tCKA
tCW
ns
ns
tDH
ns
tDW
23
70
23
85
ns
tWC
ns
tWHZ
8
8
ns
October 4, 2004 cellRAM_00_A0
CellularRAM
172
P r e l i m i n a r y
Table 61. Asynchronous WRITE Timing Parameters—ADV# LOW (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tWP
Min
46
10
0
Max
Min
55
10
0
Max
Units
ns
tWPH
tWR
ns
ns
Table 62. Burst READ Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
20
20
ns
5
1
5
1
ns
7.5
7.5
ns
12.5
4
15
5
ns
tCSP
ns
tHD
2
2
ns
tKOH
tOHZ
tSP
2
2
ns
8
8
ns
3
3
ns
173
CellularRAM
cellRAM_00_A0 October 4, 2004
P r e l i m i n a r y
t
CLK
V
V
IH
IL
CLK
t
t
t
WC
SP
HD
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
AW
SP
t
WR
t
HD
V
V
IH
IL
ADV#
t
CBPH
t
t
CEM
HD
t
t
t
CSP
CW
HZ
V
V
IH
IL
CE#
OE#
(Note 2)
t
t
OHZ
BOE
V
V
IH
IL
t
AS
t
OLZ
t
t
t
t
t
WPH
SP
SP
HD
WP
V
V
IH
IL
WE#
t
t
BW
HD
V
V
IH
IL
LB#/UB#
t
t
CEW
CEW
t
t
KHTL
HZ
High-Z
V
V
High-Z
OH
OL
WAIT
t
DW
t
DH
t
t
KOH
ACLK
High-Z
V
V
IH
IL
Valid
Output
DQ[15:0]
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 74. Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
October 4, 2004 cellRAM_00_A0
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Table 63. Burst READ Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
tCSP
tHD
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
8
8
Table 64. Asynchronous WRITE Timing Parameters—WE# Controlled
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
Max
Units
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
0
tAW
70
70
85
85
tBW
tCEM
tCW
tDH
4
4
8
70
0
85
0
tDW
tHZ
tWC
tWP
tWPH
tWR
23
23
8
70
46
10
0
85
55
10
0
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P r e l i m i n a r y
t
CLK
V
V
IH
IL
CLK
t
t
HD
SP
V
V
IH
IL
Valid
Address
Valid
Address
A[22:0]
t
t
AVS
AVH
t
t
t
VPH
VS
SP
t
t
HD
VP
V
V
IH
IL
ADV#
t
AW
t
t
AS
CBPH
t
t
CEM
HD
t
t
t
CSP
CW
HZ
V
V
IH
IL
CE#
OE#
(Note 2)
t
t
OHZ
BOE
V
V
IH
IL
t
AS
t
OLZ
t
t
t
t
t
WPH
SP
SP
HD
WP
V
V
IH
IL
WE#
t
t
BW
HD
V
V
IH
IL
LB#/UB#
t
t
CEW
CEW
t
t
KHTL
HZ
High-Z
V
V
High-Z
OH
OL
WAIT
t
DW
t
DH
t
t
KOH
ACLK
High-Z
V
V
OH
OL
Valid
Output
DQ[15:0]
Valid
Input
Legend:
Don't Care
Undefined
READ Burst Identified
(WE# = HIGH)
Notes:
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes
HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How
Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 75. Burst READ Followed by Asynchronous WRITE Using ADV#
October 4, 2004 cellRAM_00_A0
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Table 65. Burst READ Timing Parameters
70ns/80 MHz
85ns/66 MHz
Symbol
tACLK
tBOE
tCBPH
tCEW
tCLK
Min
Max
9
Min
Max
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
5
1
5
1
7.5
7.5
12.5
4
15
5
tCSP
tHD
2
2
tHZ
8
1.6
9
8
tKHKL
tKHTL
tKOH
tKP
1.6
11
2
3
2
3
tOHZ
8
8
Table 66. Asynchronous WRITE Timing Parameters Using ADV#
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVH
tAVS
tAW
5
5
10
70
70
10
85
85
tBW
tCEM
tCEW
tCW
tDH
4
4
1
70
0
7.5
1
85
0
7.5
tDW
tHZ
23
23
8
8
tVP
10
10
70
46
10
10
10
85
55
10
tVPH
tVS
tWP
tWPH
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Table 66. Asynchronous WRITE Timing Parameters Using ADV# (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
Min
Max
Min
Max
Units
tWR
0
0
ns
V
V
IH
IL
Valid
Address
Valid
Valid
Address
A[22:0]
ADV#
Address
t
t
WR
t
AW
AA
V
V
IH
IL
t
t
t
BHZ
BW
BLZ
V
V
IH
IL
LB#/UB#
CE#
t
t
t
CBPH
CEM
t
HZ
CW
V
V
IH
IL
(Note)
t
LZ
t
t
OHZ
OE
V
V
IH
IL
OE#
t
WC
t
t
WP
t
AS
WPH
V
V
IH
IL
WE#
t
t
HZ
HZ
V
V
OH
OL
WAIT
t
WHZ
t
OLZ
High-Z
High-Z
V
V
V
V
IH
IL
OH
OL
Valid
Output
DQ[15:0]
DATA
DATA
t
t
DW
DH
Legend:
Don't Care
Undefined
Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH
for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How Extended Timings Impact Cel-
lularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 76. Asynchronous WRITE Followed by Asynchronous READ—ADV# LOW
Table 67. WRITE Timing Parameters—ADV# LOW
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
tAW
70
70
70
85
85
85
ns
tBW
ns
tCW
ns
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Table 67. WRITE Timing Parameters—ADV# LOW (Continued)
70ns/80 MHz
85ns/66 MHz
Symbol
tDH
Min
0
Max
Min
0
Max
Units
ns
tDW
23
23
ns
tHZ
8
8
8
8
ns
tWC
70
85
ns
tWHZ
tWP
tWPH
tWR
ns
46
10
0
55
10
0
ns
ns
ns
Table 68. READ Timing Parameters—ADV# LOW
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
8
Min
Max
85
8
Units
ns
tBHZ
tBLZ
tCBPH
tCEM
tHZ
ns
10
5
10
5
ns
ns
4
8
4
8
µs
ns
tLZ
10
5
10
5
ns
tOE
20
8
20
8
ns
tOHZ
tOLZ
ns
ns
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cellRAM_00_A0 October 4, 2004
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V
V
IH
IL
Valid
Address
Valid
Address
Valid
Address
A[22:0]
t
t
t
t
t
WR
AA
AVS
AVH
AW
t
t
t
VPH VP
VS
V
V
IH
IL
ADV#
t
t
t
BHZ
t
BW
BLZ
CVS
V
V
IH
IL
LB#/UB#
t
t
CEM
t
CBPH
t
HZ
CW
V
V
IH
IL
CE#
OE#
(Note)
t
t
LZ
AS
t
OHZ
V
V
IH
IL
t
WC
t
t
WP
t
AS
WPH
t
OLZ
V
V
IH
IL
WE#
V
V
OH
OL
WAIT
t
WHZ
t
OE
High-Z
High-Z
V
V
V
V
IH
IL
OH
OL
Valid
Output
DQ[15:0]
DATA
DATA
t
t
DW
DH
Legend:
Don't Care
Undefined
Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH
for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How Extended Timings Impact Cel-
lularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).
Figure 77. Asynchronous WRITE Followed by Asynchronous READ
Table 69. WRITE Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz
85ns/66 MHz
Symbol
tAS
Min
0
Max
Min
0
Max
Units
ns
tAVH
tAVS
tAW
5
5
ns
10
70
70
10
70
0
10
85
85
10
85
0
ns
ns
tBW
ns
tCVS
tCW
ns
ns
tDH
ns
tDW
23
23
ns
October 4, 2004 cellRAM_00_A0
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P r e l i m i n a r y
Table 69. WRITE Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz
85ns/66 MHz
Symbol
tVP
Min
10
10
70
70
Max
Min
10
10
85
85
Max
Units
ns
tVPH
tVS
ns
ns
tWC
ns
tWHZ
tWP
tWPH
tWR
8
8
ns
46
10
0
55
10
0
ns
ns
ns
Table 70. READ Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ
70ns/80 MHz
85ns/66 MHz
Symbol
tAA
Min
Max
70
8
Min
Max
85
8
Units
ns
tBHZ
tBLZ
tCBPH
tCEM
tHZ
ns
10
5
10
5
ns
ns
4
8
4
8
µs
ns
tLZ
10
5
10
5
ns
tOE
20
8
20
8
ns
tOHZ
tOLZ
ns
ns
How Extended Timings Impact CellularRAM™ Operation
Introduction
This section describes CellularRAM™ timing requirements in systems that per-
form extended operations.
CellularRAM products use a DRAM technology that periodically requires refresh to
ensure against data corruption. CellularRAM devices include on-chip circuitry that
performs the required refresh in a manner that is completely transparent in sys-
tems with normal bus timings. The refresh circuitry imposes constraints on
timings in systems that take longer than 4µs to complete an operation. WRITE
operations are affected if the device is configured for asynchronous operation.
Both READ and WRITE operations are affected if the device is configured for page
or burst-mode operation.
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Asynchronous WRITE Operation
The timing parameters provided in Figure 40 require that all WRITE operations
must be completed within 4µs. After completing a WRITE operation, the device
must either enter standby (by transitioning CE# HIGH), or else perform a second
operation (READ or WRITE) using a new address. Figure 78 and Figure 79 dem-
onstrate these constraints as they apply during an asynchronous (page-mode-
disabled) operation. Either the CE# active period (tCEM in Figure 78) or the ad-
dress valid period (tTM in Figure 79) must be less than 4µs during any WRITE
operation, otherwise, the extended WRITE timings must be used.
t
< 4 µs
CEM
CE#
ADDRESS
Figure 78. Extended Timing for t
CEM
CE#
t
<
TM 4µs
ADDRESS
Figure 79. Extended Timing for t
TM
Table 71. Extended Cycle Impact on READ and WRITE Cycles
Page Mode
Timing Constraint
Read Cycle
Write Cycle
Must use extended WRITE
timing.
Asynchronous
Page Mode Disabled
tCEM and tTM > 4µs
(See Figure 78 and Figure 79.)
No impact.
(See Figure 79)
Must use extended WRITE
timing.
Asynchronous
Page Mode Enabled
tCEM > 4µs
(See Figure 78.)
All following intrapage READ
access times are tAA (not tAPA).
(See Figure 80)
Burst
tCEM > 4µs (See Figure 78.)
Burst must cross a row boundary within 4µs.
Extended WRITE Timing— Asynchronous WRITE Operation
Modified timings are required during extended WRITE operations (see Figure 80).
An extended WRITE operation requires that both the write pulse width (tWP) and
the data valid period (tDW) be lengthened to at least the minimum WRITE cycle
time (tWC [MIN]). These increased timings ensure that time is available for both
a refresh operation and a successful completion of the WRITE operation.
October 4, 2004 cellRAM_00_A0
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182
P r e l i m i n a r y
t
or t
> 4µs
TM
CEM
ADDRESS
CE#
LB#/UB#
t
t
> t
(MIN)
(MIN)
WP
DW
WC
WC
WE#
> t
DATA-IN
Figure 80. Extended WRITE Operation
Page Mode READ Operation
When a CellularRAM device is configured for page mode operation, the address
inputs are used to accelerate read accesses and cannot be used by the on-chip
circuitry to schedule refresh. If CE# is LOW longer than the tCEM maximum time
of 4µs during a READ operation, the system must allow tAA (not tAPA, as would
otherwise be expected) for all subsequent intrapage accesses until CE# goes
HIGH.
Burst-Mode Operation
When configured for burst-mode operation, it is necessary to allow the device to
perform a refresh within any 4µs window. One of two conditions will enable the
device to schedule a refresh within 4µs. The first condition is when all burst op-
erations complete within 4µs. A burst completes when the CE# signal is
registered HIGH on a rising clock edge. The second condition that allows a refresh
is when a burst access crosses a row boundary. The row-boundary crossing
causes WAIT to be asserted while the next row is accessed and enables the
scheduling of refresh.
Summary
CellularRAM products are designed to ensure that any possible asynchronous tim-
ings do not cause data corruption due to lack of refresh. Slow bus timings on
asynchronous WRITE operations require that tWP and tDW be lengthened. Slow
bus timings during asynchronous page READ operations cause the next intrapage
READ data to be delayed to tAA.
Burst mode timings must allow the device to perform a refresh within any 4µs
period. A burst operation must either complete (CE# registered HIGH) or cross a
row boundary within 4µs to ensure successful refresh scheduling. These timing
requirements are likely to have little or no impact when interfacing a CellularRAM
device with a low-speed memory bus.
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Revision Summary
Revision A0 (November 10, 2004)
Initial release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
ìas isî without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
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Copyright © 2004 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Span-
sion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective compa-
nies.
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