S75WS-P [SPANSION]
based MCP/POP Products; 基于MCP / POP产品
| 型号： | S75WS-P |
| 厂家： | 
SPANSION |
| 描述： | based MCP/POP Products |
| 文件： | 总15页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S75WS-P based MCP/POP Products
1.8 Volt-only x16 Simultaneous Read/Write, Burst Mode
Flash (NOR Interface)
S30MS-P (NAND Interface) ORNAND™ Flash
pSRAM Type 2
S75WS-P based MCP/POP Products Cover Sheet
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S75WS-P_00
Revision 02
Issue Date September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
ii
S75WS-P based MCP/POP Products
September 6, 2006 S75WS-P_00-02
S75WS-P based MCP/POP Products
1.8 Volt-only x16 Simultaneous Read/Write, Burst Mode
Flash (NOR Interface)
S30MS-P (NAND Interface) ORNAND™ Flash
pSRAM Type 2
Data Sheet (Advance Information)
Features
Power supply voltage of 1.7 to 1.95V
Package:
– 12 x 12 mm PoP
– 9 x 12 mm, 115-ball MCP
Flash access time: 80 ns (NOR), 25 ns (ORNAND)
Flash burst frequencies: 66 MHz, 80 MHz, 108 MHz
pSRAM Access time: 70 ns, 20 ns (Page)
Operating Temperature
– –25°C to +85°C (wireless)
pSRAM burst frequency: 66 MHz, 80 MHz, 104 MHz
The S75WS series is a product line of MCPs or POPs, and consists of:
One S29WS-P NOR flash memory die
One or more S30MS-P NAND interface ORNAND flash memory die
pSRAM Type 2
For detailed specifications, please refer to the individual data sheets
.
Document
S29WS-P
Publication Identification Number (PID)
S29WS-P_00
psram_24
256Mb pSRAM Type 2
S30MS-P
S30MS-P_00
Publication Number S75WS-P_00
Revision 02
Issue Date September 6, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design
in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
1. Product Selector Guide
Flash
Density
(Mb)
pSRAM
Density
(Mb)
ORNAND
Density
(Mb)
Flash
Speed
(MHz)
Model
Number
pSRAM Speed
(MHz)
Device
pSRAM Supplier
Package
AMB128: POP
12 x12 x 1.15 mm
S75WS256PEFKFF
LW
VS
66
80
256
256
512
104
Type 2
FMC115: MCP
12 x 9 mm
S75WS256PEFJF5
2. MCP Block Diagram
A0-A23
A0-A23
RDY
RDY
DQ0-DQ15
DQ0-DQ15
WS256P
Flash
Memory
CLK
AVD#
F-CE#
OE#
F-RST#
F-ACC
F1-WP#
WE#
CLK
AVD#
CE#
OE#
RESET#
ACC
VSS
VSS
WP#
WE#
VCC
F-VCC
VCCQ
A0-A23
WAIT#
DQ0-DQ15
CLK
AVD#
CE#
OE#
256 Mb
UtRAM
Memory
R1-CE#
R-LB#
R-UB#
LB#
UB#
WE#
CRE
R-CRE
VSS
VCC
R-VCC
VCCQ
I/O0-I/O15
N-RY/BY#
I/O0-I/O15
RB#
MS512P
x16 ORNAND
Memory
N-CLE
N-CE#
N-ALE
CLE
CE#
ALE
VSS
N-VSS
N-PRE
N-RE#
N-WP#
N-WE#
RE#
WP#
WE#
PRE
VCC
N-VCC
2
S75WS-P based MCP/POP Products
S75WS-P_00_02 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
3. POP Block Diagram
A0-A23
A0-A23
DQ0-DQ15
DQ0-DQ15
F-RDY/R-WAIT
RDY
WS256P
Flash
Memory
CLK
AVD#
CLK
AVD#
F-CE#
OE#
F-RST#
CE#
OE#
RESET#
VSS
VSS
F-ACC
F1-WP#
ACC
WP#
VSSQ
VSSQ
WE#
WE#
VCC
F-VCC
VCCQ
VCCQ
A0-A23
DQ0-DQ15
WAIT#
R-CLK
R-CE#
CLK
AVD#
256Mb
UtRAM
Memory
CE#
OE#
R-LB#
R-UB#
LB#
UB#
WE#
MRS
R-MRS
VSSQ
VSS
VCC
R-VSS
R-VCC
VCCQ
I/O0-I/O15
I/O0-I/O15
RB#
ACC
N-RY/BY#
MS512P
x16 ORNAND
Memory
N-CLE
N-CE#
N-ALE
CLE
CE#
ALE
VSS
N-RE#
RE#
N-PRE
N-VCC
PRE
N-WP#
N-WE#
WP#
WE#
VCC
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S75WS-P based MCP/POP Products
3
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
4. Connection Diagrams
4.1
12 x 12 mm PoP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
18
Legend
A
B
C
D
E
F
All Shared
NC
NC
A0
A2
A3
A4
A5
A6
A7
N-VCC
VSS
A8
A9
A10
A11
A12
A13
A14
A15
F-VCC A-16
A18
A19
A20
A21
A22
RFU
NC
NC
NC
RFU
VSS
A17
NC
NC
No Connect
NOR Flash Only
RFU
RFU
R-VSS
A1
R-VSS
A23
RFU
RFU
RFU
Reserved for Future Use
pSRAM Only
R-MRS RFU
RFU
RFU
RFU
RFU
VSS
N-WE# RFU
R-VCC AVD#
G
Flash Shared Only
ORNAND Flash Only
NOR/pSRAM Shared Only
H
J
R-CE#
RFU
RFU
WE#
RFU
OE#
RFU
N-CE#
K
L
N-ALE N-CLE
R-CLK F-CLK
N-RY/BY# N-RE#
RFU
VSS
F-CE#
RFU
M
N
F-RDY/ R-VSS
R-WAIT
N-VCC R-VCC
DQ14 DQ15
VCCQ VSSQ
R-VCC F-VCC
P
R
T
DQ1
DQ0
VSSQ VCCQ
N-PRE RFU
RFU
NC
RFU
NC
U
NC
NC
NC
NC
RFU
RFU
DQ13 DQ11 VSSQ
DQ12 DQ10 VCCQ
DQ9
DQ8
RFU N-WP# F-WP# RFU
R-UB# F-ACC F-RST# R-LB#
DQ7
DQ6
VSSQ
VCCQ
DQ5
DQ4
DQ3
DQ2
RFU
RFU
V
NC
NC
4
S75WS-P based MCP/POP Products
S75WS-P_00_02 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
4.2
9 x 12 mm, 115-ball MCP
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
NC
NC
NC
NC
NC
Legend
Reserved for Future Use
No Connect
NC
NC
NC
NC
AVD#
VSS
A7
CLK
R-LB#
R-UB#
A18
IO14
A8
IO13
A11
A12
A13
A14
RFU
IO12
RFU
IO15
F-WP#
A3
IO11
A15
A21
A22
A16
IO10
IO9
N-RY/
BY#
F-ACC WE#
N-RE#
N-CE#
N-VCC
N-VSS
A6
A19
A9
F-RST# RFU
NOR Flash Only
A2
A5
IO8
RDY
RFU
RFU
DQ3
A20
A23
G
NAND Flash Only
pSRAM Only
A1
A4
A17
A10
DQ6
N-VCC
N-VSS
IO7
H
J
A0
VSS
DQ1
RFU
DQ4
NOR Flash/
pSRAM Shared Only
N-CLE# F1-CE# OE#
DQ9
DQ13 DQ15 R-MRS
K
L
N-ALE# R-CE#
DQ0
DQ10
DQ2
DQ12
DQ5
IO1
DQ7
DQ14
IO2
VSS
IO4
IO3
NC
IO6
F-VCC R-VCC
N-WE# N-WP# DQ8
IO5
DQ11
RFU
IO0
M
N
NC
NC
NC
RFU
NC
RFU
VSS
PRE
NC
F-VCC
P
NC
NC
NC
4.3
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150×C for prolonged periods of time.
S75WS-P_00_02 September 6, 2006
S75WS-P based MCP/POP Products
5
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
4.4
Look-ahead Ballout for Future Designs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
NC
18
NC
NC
Legend
Address
A
B
C
D
E
F
NC
NC
NC
NC
A0
A2
A3
A4
A5
A6
A7
F-VCC2
F-VSS
A8
A9
A10
A11
A12
A13
A14 F-VCC1 A-16
A18
A19
A20
A21
A22
RFU
RFU
A15
F-VSS
A17
No Connect
(corner balls)
RFU R-VSS/ NC
R-VSS/ RFU
NC
Data
Reserved for Future Use
Ground
RFU
A1
A23
A25
A24
A26
A27
D-BA1/
D-BA0/
P1-CRE
P2-CRE/S1-CS2
D-RAS#/D-CAS#/
F-RAS# F-CAS#
N-WE#
G
Power
D-WE# F-VSS
R-VCC F-ADV#/
P-ADV#
H
J
Control
D1-CS#/ D2-CS#/
P1-CE# P2-CE#
F-WE#/
P-WE#/S-WE# P-OE#/S-OE#
F-OE#/
F3-CE#/
F4-CE#/
D-CLK# F-CLK#
N2CE#/P1-CE2 N1CE#/P2-CS2
K
L
N-ALE N-CLE
D-CLK/ F-CLK
P-CLK
N-RDY/ N-RE#
BSY#
F2-CE#/ F1-CE#
N3CE#
M
N
F-WAIT/
R-VSS
F-VSS F-DPD
R-VCC F-VCC1
P-WAIT/P-RDY
F-VCC2 R-VCC
P
R
T
DQ14 DQ15
VCCQ VSSQ
DQ1
DQ0
VSSQ VCCQ
N-PRE F-CKE
D-CKE N-RES#/
NC
U
NC
NC
NC
NC
NC
NC
NC
NC
N-MRES# DQ13 DQ11 VSSQ
DQ9 D-DQS1N-WP2#/ F-WP# D-DQS0 DQ7
F-WP2#
VSSQ
VCCQ
DQ5
DQ4
DQ3
DQ2
RFU
RFU
V
D-DM1/
RFU
DQ12 DQ10 VCCQ
DQ8
F-VPP/ F-RST# D-DM0/ DQ6
P-UB#/ S-UB#
N-ACC
P-LB#/S-LB#
6
S75WS-P based MCP/POP Products
S75WS-P_00_02 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
5. Input/Output Descriptions
Table 5.1 identifies the input and output package connections provided on the device.
Table 5.1 Input/Output Descriptions (Sheet 1 of 2)
Signal
Type
WS
(NOR)
MS
(ORNAND)
Symbol
Amax-A0
Description
pSRAM
Input
I/O
NOR Flash Address inputs
X
X
X
Flash Data input/output, shared between NOR and ORNAND
Flash; shared with IO15-IO0 for ORNAND
DQ15-DQ0
F-CE#
X
X
NOR Flash Chip-enable input #1. Asynchronous relative to CLK
for Burst Mode.
Input
X
X
Output Enable input. Asynchronous relative to CLK for Burst
mode.
OE#
Output
X
X
WE#
F-VCC
F-VCCQ
VSS
Input
Power
Power
Ground
—
Write Enable input.
X
X
X
X
NOR Flash device power supply (1.7 V - 1.95V).
Input/Output Buffer power supply.
Ground
X
X
X
RFU
Reserved for Future Use
RDY
Output
Flash ready output. Indicates the status of the Burst read. VOL =
data valid. The Flash RDY pin is shared with the WAIT pin of the
pSRAM.
X
X
CLK
Input
Input
NOR Flash Clock, shared with CLK of burst-mode pSRAM. The
first rising edge of CLK in conjunction with AVD# low latches the
address input and activates burst mode operation. After the initial
word is output, subsequent rising edges of CLK increment the
internal address counter. CLK should remain low during
asynchronous access.
X
X
AVD#
NOR Flash Address Valid input. Shared with AVD# of burst-mode
pSRAM. Indicates to device that the valid address is present on
the address inputs.
V
IL = for asynchronous mode, indicates valid address; for burst
X
mode, causes starting address to be latched on rising edge of
CLK.
VIH= device ignores address inputs
F-RST#
F-WP#
F-ACC
Input
Input
Input
NOR Flash hardware reset input. VIL= device resets and returns
to reading array data
X
X
NOR Flash hardware write protect input. VIL = disables program
and erase functions in the four outermost sectors.
NOR Flash accelerated input. At VHH, accelerates programming;
automatically places device in unlock bypass mode. At VIL
disables all program and erase functions. Should be at VIH for all
other conditions.
,
X
R-CE#
R-MRS
R-VCC
R-UB#
R-LB#
DNU
Input
Input
Power
Input
Input
—
Chip-enable input for pSRAM
Mode Select Register (pSRAM). For Type 2 only.
pSRAM Power Supply
X
X
X
X
X
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Do Not Use
N-CLE
Input
Command Latch Enable: The CLE input signal is used to control
loading of the operation mode command into the internal
command register. The command is latched into the command
register from the I/O port on the rising edge of the WE# signal
while CE# is low and CLE is High.
X
X
N-ALE
Input
Address Latch Enable: The ALE signal is used to control loading
of either address information or input data into the internal
address/data register. Address information is latched on the rising
edge of WE# if CE# is low and ALE is High.
Input data is latched if CE# is low and ALE is Low.
S75WS-P_00_02 September 6, 2006
S75WS-P based MCP/POP Products
7
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
Table 5.1 Input/Output Descriptions (Sheet 2 of 2)
Signal
Type
WS
(NOR)
MS
(ORNAND)
Symbol
N-CE#
Description
pSRAM
Input
Chip Enable: The device enters a low-power Standby mode when
the device is in Ready mode. The CE# signal is ignored when the
device is in a Busy state (RY/BY# = L), such as during a Page
Buffer Load or Erase operation, and will not enter Standby mode
even if the CE# input goes high. The CE# signal may be inactive
during the Page Buffer write and Page Buffer load of the array
data.
X
N-WE#
N-RE#
Input
Write Enable: The WE# signal is used to control the acquisition of
data from the I/O port.
X
X
Output
Read Enable: The RE# signal controls serial data output. Data is
available tREA after the falling edge of RE#. The internal column
address counter is also incremented (Address = Address + 1) on
this falling edge.
N-WP#
Input
Write Protect: The WP# signal is used to protect the device from
accidental programming or erasing. This signal is usually used for
protecting the data during the power-on/off sequence when input
signals are invalid.
X
8
S75WS-P based MCP/POP Products
S75WS-P_00_02 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
6. Ordering Information
The order number is formed by a valid combinations of the following:
S75WS
256
P
EF
KF
F
LW
0
PACKING TYPE
0 = Tray
2 = 7” Tape and Reel
3 = 13” Tape and Reel
MODEL NUMBER
Refer to the Valid Combinations Table
PACKAGE DESCRIPTOR
Depends on Character 12. For a more detailed description see Table 6.1.
PACKAGE TYPE & MATERIAL SET
HF = 1.2mm MCP FBGA, Pb-free
KF = 1.2mm POP FBGA, Pb-free
JF = 1.4mm MCP FBGA, Pb-free
CellularRAM DENSITY
D0 = 128 Mb
PROCESS TECHNOLOGY
P = 90 nm, MirrorBitTM Technology
CODE FLASH DENSITY
256 = 256Mb
512 = 512Mb
PRODUCT FAMILY
S71WS Stacked Products (MCP/PoP)
1.8 V NOR Flash with pSRAM
Table 6.1 Character Position Descriptions
Character 14 Description
Character 12
Character 14
Package Area
7x9 mm
Package Ball Count
Raw Ball Size
0
1
56
80
7x9 mm
2
8x11.6 mm
8x11.6 mm
9x12 mm
64
3
84
4
84
H, J, or G
0.35 mm
5
9x12 mm
115
137
84
6
9x12 mm
7
11x13 mm
11x13 mm
11x13 mm
11x11 mm
11x11 mm
12x12 mm
12x12 mm
14x14 mm
14x14 mm
15x15 mm
15x15 mm
17x17 mm
17x17 mm
8
115
137
112
112
128
128
152
152
160
160
192
192
9
A
B
D
F
G
H
J
0.45 mm
0.50 mm
0.45 mm
0.50 mm
0.45 mm
0.50 mm
0.45 mm
0.50 mm
0.45 mm
0.50 mm
K
K
L
M
S75WS-P_00_02 September 6, 2006
S75WS-P based MCP/POP Products
9
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
6.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
S75WS-P Valid Combinations
Package &
Package
Model
NOR Flash
pSRAM
pSRAM
Package
Device
S75WS256PEF
Material Set
Descriptor Number
Packing Type
Speed (MHz)
Speed (MHz)
Supplier
Package Type Markings
KF
JF
F
5
LW
VS
66
80
104
104
Type 2
Type 2
12 x 12 mm
(Note 2)
9 x 12 mm
0, 2, 3 (Note 1)s
Notes:
1. Packing Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading S and packing type designator from ordering part number.
10
S75WS-P based MCP/POP Products
S75WS-P_00_02 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
7. Physical Dimensions
7.1
AMB128— 128-ball 12 x 12 mm Package-on-Package
A
D
D1
PIN A1
CORNER
9
PIN A1
CORNER
eD
SD
7
INDEX MARK
A
B
C
D
E
F
SE
7
G
H
J
E
B
E1
K
L
M
N
P
R
T
eE
U
V
0.15
(2X)
C
18 17 16 15 14 13 12 11 10
9
7
6
8
5
4
3
2
1
BOTTOM VIEW
0.15
(2X)
C
TOP VIEW
0.20
0.10
C
C
A2
A
A1
C
SIDE VIEW
6
128X
b
0.15
0.08
M
C
C
A
B
M
NOTES:
PACKAGE
JEDEC
AMB 128
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 12.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3.0, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
1.15
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.39
0.55
---
BALL HEIGHT
---
0.70
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E"
DIRECTION.
12.00 BSC
12.00 BSC
11.05 BSC
11.05 BSC
18
E
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL
POSITIONS FOR MATRIX SIZE MD X ME.
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
SD AND SE ARE MEASURED WITH RESPECT TO
DATUMS A AND B AND DEFINE THE POSITION OF THE
CENTER SOLDER BALL IN THE OUTER ROW.
18
128
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS
IN THE OUTER ROW SD OR SE = 0.000.
N
128
MAXIMUM NUMBER OF BALLS
NUMBER OF LAND PERIMETERS
BALL DIAMETER
R
2
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS
IN THE OUTER ROW, SD OR SE = e/2
b
0.45
0.50
0.55
Ø
eE
eD
0.65 BSC
0.65 BSC
0.325 BSC
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
BALL PITCH
9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER
OR INK MARK, METALLIZED MARK INDENTATION OR
OTHER MEANS.
SD SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
C3~C16, D3~D16, E3~E16, F3~F16
G3~G16, H3~H16, J3~J16, K3~K16
L3~L16, M3~M16, N3~N16, P3~P16
R3~R16, T3~T16
3559 \ 16-038.56 \ 4.28.6
S75WS-P_00_02 September 6, 2006
S75WS-P based MCP/POP Products
11
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
7.2
FMC115 — 115-ball 12 x 9 mm MCP
NOTES:
PACKAGE
JEDEC
FMC 115
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D x E
12.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
1.40
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
0.17
0.96
---
BALL HEIGHT
---
1.11
BODY THICKNESS
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E"
DIRECTION.
12.00 BSC.
9.00 BSC.
10.4 BSC.
7.20 BSC.
14
E
BODY SIZE
n IS THE NUMBER OF POPULTED SOLDER BALL
POSITIONS FOR MATRIX SIZE MD X ME.
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO
DATUMS A AND B AND DEFINE THE POSITION OF THE
CENTER SOLDER BALL IN THE OUTER ROW.
10
115
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS
IN THE OUTER ROW SD OR SE = 0.000.
b
0.35
0.40
0.45
BALL DIAMETER
Ø
eE
eD
0.80 BSC.
0.80 BSC
0.40 BSC.
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS
IN THE OUTER ROW, SD OR SE = e/2
BALL PITCH
SD SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
A3,A4,A5,A6,A7,A8
B3,B4,B5,B6,B7,B8,C1
N3,N4,N5,N6,N7,N8
P3,P4,P5,P6,P7,P8
9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER
OR INK MARK, METALLIZED MARK INDENTATION OR
OTHER MEANS.
3603 \ 16-038.19 \ 9.6.6
12
S75WS-P based MCP/POP Products
S75WS-P_00_02 September 6, 2006
D a t a S h e e t
( A d v a n c e I n f o r m a t i o n )
8. Revision History
8.1
8.2
Revision 01 (May 5, 2006)
Initial release.
Revision 02 (September 6, 2006)
Added the MCP S75WS256PEF
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
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damages of any kind arising out of the use of the information in this document.
Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
S75WS-P_00_02 September 6, 2006
S75WS-P based MCP/POP Products
13
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