MN5915 [SPECTRUM]

ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDIP28, PLASTIC, DIP-28;


型号：	MN5915
厂家：	SPECTRUM MICROWAVE, INC.
描述：	ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDIP28, PLASTIC, DIP-28 光电二极管转换器
文件：	总9页 (文件大小：68K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MN5915

10-Bit, 20MHz

Sampling A/D Converter

DESCRIPTION

FEATURES

The MN5915 is a monolithic 10-bit, 20MHz

sampling A/D converter with an on-board input

buffer and T/H amplifier. This device is packaged

in a small 32-pin plastic DIP and consumes

140mW of power from a single +5V supply.

10-Bit Resolution

20MHz Sampling Rate

On-Chip T/H Amplifier

The MN5915 is TTL-compatible and provides an

over-range output bit. The device is clocked from

a single sampling clock. Digital output data lines

are presented via onboard 3-state output buffers.

140mW Power

Consumption

Single +5V Supply

Operation

The device is available for commercial and

industrial applications and is specified for 0°C to

+70°C applications.

TTL-Compatible Digital

Inputs/Outputs

APPLICATIONS

Small 28-Pin Plastic DIP

Video Digitizer

RADAR

Pulse Measurement

Systems

Infrared Imaging

IF Digitizer

Imaging

Low 5pF Input

Capacitance

3-State Output Buffers

Communications

Medical Imaging

m ic ro ne tworks

324 Clark Street Worcester MA 01606-1293

Phone: (508) 852-5400 FAX (508) 853-8296

MN5915 10-Bit 20MHz Sampling A/D Converter

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION

PART NUMBER

Operating Temperature Range

Specified Temperature Range

Storage Temperature Range

Power Supplies

0°C to +70°C

MN5915

0°C to +70°C

-65°C to +150°C

+6 Volts

Standard model is specified for

0°C to +70°C operation.

Digital Inputs

+V_CC

Analog Input

V_REF

-0.5V to +V_CC+0.5V

0 to +V_CC

SPECIFICATIONS Typical at +25°C, +V =+5V, V_IN=0 to +4V, f_S=20MSPS, f_CLK=40MHz, V_RHS=+4.0V,

V_RLS=0.0V, unless otherwise specified.

SPECIFICATIONS

ANALOG INPUT

MIN.

TYP.

MAX.

UNITS

Input Voltage Range

Input Capacitance

Input Resistance

Input Bandwidth (3dB Small Signal)

V_RLS

250

V_RHS

Volts

k Ohms

MHz

300

100

DIGITAL INPUTS

Logic Levels: Logic “1”

Logic “0”

Logic Currents: Logic “1”

Logic “0”

+2.0

+3.5

Volts

+0.8

+/-10

DIGITAL OUTPUTS

Logic Levels: Logic “1” @ I_OH=0.5mA

Logic “0” @ I_OL=1.6mA

Output Rise and Fall Time (15pF load)

Output Enable to Data Output Delay (20pF load)

Volts

nsec

0.4

TRANSFER CHARACTERISTICS

Integral Nonlinearity Error

Differential Nonlinearity Error

Offset Error

+/-1

+/-0.5

+/-2

LSB

Gain Error

+/-2

No Missing Codes

Guaranteed

REFERENCE INPUT

Resistance

Bandwidth

Voltage Range: V_RLS

V_RHS

400

100

3.0

1.0

500

150

600

MHz

Volts

2.0

AV_DD

5.0

V_RHS- V_RLS

D(V_RHF-V_RHS

D(V_RLS-V_RLF

4.0

)

DYNAMIC CHARACTERISTICS

Conversion Rate

Pipeline Delay (Latency)

Aperture Delay

MHz

Clock Cycles

nsec

Aperture Jitter

psec-

Signal-to-Noise Ratio (SNR)

f_IN= 3.58MHz

f_IN= 10.3MHz

Total Harmonic Distortion (THD)

f_IN= 3.58MHz

f_IN= 10.3MHz

Signal-to-(Noise + Distortion) (SINAD)

f_IN= 3.58MHz

f_IN= 10.3MHz

SPECIFICATIONS

MIN.

TYP.

MAX.

UNITS

Bits

Effective Number of Bits:

f_IN= 1MHz

8.8

8.7

8.5

f_IN= 3.58MHz

f_IN= 5MHz

f_IN= 10.3MHz

Spurious Free Dynamic Range (SFDR)

f_IN=1MHz

POWER SUPPLY REQUIREMENTS

Power Supplies: Analog Supply

Digital Supply

Current Drains: Analog Supply

Digital Supply

+4.75

+5.00

+5.25

Volts

Power Consumption

140

165

PIN DESIGNATIONS

1. Analog Ground

2. V_RHF

3. V_RHS

28. Overrange Output

27. Bit 1 (MSB)

26. Bit 2

4. N/C

25. Bit 3

5. V_RLS

24. Bit 4

6. V_RLF

23. Bit 5

7. Analog Input

8. Analog Ground

9. V_CAL

22. Digital Supply

21. Digital Ground

20. Bit 6

10. Analog Supply

11. Digital Supply

12. Digital Ground

13. Clock Input

14. DAV (Data Valid)

19. Bit 7

18. Bit 8

17. Bit 9

16. Bit 10 (LSB)

15. Output Enable

m ic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296

shown above in order to avoid possible

latch-up conditions.

APPLICATIONS INFORMATION - The

figure below indicates the typical interface

requirements for the MN5915 under normal

operating conditions. To reduce the

possibility of latch-up, avoid connecting the

device’s digital ground pins (pins 12 and 21)

to the system digital ground. These pins

should be connected as described below in

the section labeled Power Supplies and

Grounding. The following sections provide

additional application information and

descriptions of the devices major functions

as well as outline critical performance

criteria for achieving the optimal device

performance.

DESCRIPTION OF OPERATION - An

outline of this CMOS devices is shown in

the block diagram. The design of the

MN5915 contains eight identical successive

approximation ADC sections, all operating

in parallel; a 16-phase clock generator; an

11-bit, 8:1 digital output multiplexer and

correction logic; and a voltage reference

generator

which

provides

common

reference levels for each ADC section.

The device’s high sampling rate is achieved

by utilizing multiple SAR ADC sections in

parallel, each of which samples the input

signal in sequence. Each ADC section uses

16-clock cycles to complete a conversion.

The clock cycles are allocated as follows:

Clock Cycle Operation

Reference Zero Sampling

Auto-Zero Comparison

Auto-Calibrate Comparison

Input Sample

5 - 15

11-bit SAR Conversion

Data Transfer

The 16-phase clock, derived from the input

clock, synchronizes these events. The

timing signals for adjacent ADC sections are

shifted by two clock cycles so that the

analog input is sampled on every other

cycle of the input clock by exactly one ADC

section. After 16-clock periods, the timing

cycle repeats. The sample rate for the

device is therefore one half of the devices

clock rate. For example, the sampling rate

for a MN5915 operated with an applied

40MHz clock is 20MHz. The latency from

analog input signal sampled until the

corresponding digital output is valid is 12

clock cycles.

POWER SUPPLIES AND GROUNDING -

It is recommended that the device’s analog

and digital ground pins be connected

together at the device and tied to system

analog ground, preferably through a large

area, low impedance ground plane beneath

the device. Additionally, both of the device’s

digital and analog supply voltages should be

derived from a single analog supply as

VOLTAGE REFERENCE - The MN5915

requires the use of a single external voltage

reference for driving the high side of the

reference input resistor ladder. It must be

driven to within the range of 3V to 5V (+4.0V

nominal). The reference low side of the

ladder is typically tied to analog ground

(0.00V), but can be driven up to +2.0V with

a second reference source. The analog

input voltage range will track the total

voltage difference measured between the

reference ladder sense lines, V_RHSand V_RLS

(pins 3 and 5 respectively).

In cases where wider variations in offset

and gain can be tolerated, the reference

source can be directly tied to V_RHF(pin 2)

and system analog ground can be

connected to V_RLFas shown above.

Decouple force and sense lines to analog

ground as shown with 0.01uF capacitors

(chip capacitors are recommended) to

minimize high-frequency noise injection. If

this simplified configuration is employed, the

following recommendations should be

considered:

The reference ladder circuit as shown is a

simplified representation of the actual

reference ladder circuit. Due to the actual

internal structure of the ladder, the voltage

drop from V_RHFto V_RHSis not equivalent to

Force and sense lines are provided to

ensure accurate and stable setting of the

upper and lower sense line voltages across

part-to-part and temperature variations.

Utilization of the circuit shown above will

yield offset and gain errors of less than

+/-2LSBs.

the voltage drop from V_RLFto V_RLS

Typically, the top side voltage drop for V_RHF

to V_RHSwill equal:

accuracy over time and temperature. Gain

and offset errors are continually adjusted to

10-bit accuracy during device operation.

This process is transparent to the user.

V_RHF- V_RHS= 2.25% of (V_RHF-V_RLF) (typical)

and the bottom side voltage drop for VRLS

to VRLF will equal:

Upon power-up, the MN5915 begins its

calibration algorithm. In order to achieve the

calibration accuracy required, the offset and

gain adjustment step size is a fraction of a

10-bit LSB. Since the calibration algorithm is

an oversampling process, a minimum of

10,000 clock cycles are required. This

results in a minimum initial calibration time

of 250usec upon power-up (with a 20MHz

clock applied). Once calibrated, the

MN5915 remains in calibration over time

and temperature.

V_RLS- V_RLF= 1.9% of (V_RHF- V_RLF) (typical)

The figure above shows an example of

expected voltage drops for a specific case.

In this case, VREF source of +4V is utilized

while VRLF is tied to analog ground. A

90mV voltage drop is observed at VRHS

(+3.91V is measured) and a 75mV is

observed at VRLS (0.075V is measured).

Calibration cycles are initiated on the rising

edge of the clock, therefor, the clock must

always be applied for the device to remain

in calibration.

ANALOG INPUT - The input voltage range

of the MN5915 is determined by the voltage

levels of reference source (typically +4.0V

see section above). The input range will

scale proportionally with respect to the

reference.

CLOCK INPUT - The MN5915 is driven

from a single-ended TTL-compatible clock.

Because the pipelined architecture operates

on the rising edge of the clock input, the

device can operate over a wide range of

clock duty cycles without degrading device

performance.

The drive requirements for the analog input

are very minimal when compared other A/D

converters due to the MN5915’s low input

capacitance and high input impedance

(typically 250kW).

DIGITAL OUTPUTS - The format of the

output data is straight binary (see table

below). The outputs are latched on the

rising edge of the clock. Output lines can be

switched to 3-state mode by bringing

Enable to a logic “1”.

The analog input of the MN5915 should be

protected through a series resistor and

diode clamping circuit as shown below.

Output Code

Analog Input

+F.S + 1/2 LSB

+F.S. -1/2 LSB

+1/2 F.S.

+1/2 LSB

0.0V

Overrange

MSB

LSB

11 1111 1111

11 1111 1110

00 0000 0000

OVERRANGE OUTPUT - The Overrange

Output (pin 28) is an indication that the

analog input signal has exceeded the

positive full scale input voltage by at least 1

LSB. When this condition occurs, the

overrange bit will switch to a logic “1”. All

CALIBRATION - The MN5915 utilizes an

auto calibration scheme to ensure 10-bit

other data output bits remain at logic “1” as

long as overrange remains at logic “1”. This

allows users to add the MN5915 into higher

resolution systems.

TIMING DIAGRAMS

TIMING PARAMETERS

Description

Symbol

t_C

Min

2t_CLK

Typ

Max

Units

nsec

Conversion Time

Clock Period

t_CLK

t_CH

Clock High Duty Cycle

Clock Low Duty Cycle

Output Delay (15pF Load)

DAV Pulse Width

Colck to DAV

t_CL

t_OD

nsec

t_DAV

t_S

t_CLK

PACKAGE OUTLINE - 28-PIN PLASTIC DIP

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

0.200

0.135

MIN

MAX

5.08

3.43

0.120

3.05

0.020

0.51

2.54 TYP

1.70

0.33

4.57

15.24 TYP

14.10

37.08

0.100 TYP

0.067

0.013

0.180

0.600 TYP

0.555

0.170

4.32

1.460

mic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296

BLOCK DIAGRAM

mic ro ne tworks 324 Clark Street, Worcester, MA 01606-1293 Phone: (508)852-5400; FAX (508) 853-8296

MN5915 [SPECTRUM]

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