SSM4575M [SSC]

COMPLEMENTARY N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS; 互补N型和P沟道增强型功率MOSFET


型号：	SSM4575M
厂家：	SILICON STANDARD CORP.
描述：	COMPLEMENTARY N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS 互补N型和P沟道增强型功率MOSFET
文件：	总7页 (文件大小：299K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SSM4575M

COMPLEMENTARY N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS

Simple drive requirement

Low on-resistance

N-Ch BV _DSS

60V

R _DS(ON)

36mW

Fast switching performance

I _D

P-Ch BV_DSS

R_DS(ON)

-60V

72mW

-4.2A

SO-8

Description

I_D

Power MOSFETs from Silicon Standard provide the

designer with the best combination of fast switching,

ruggedized device design, low on-resistance and cost-

effectiveness.

The SO-8 package is widely preferred for commercial and

industrial surface mount applications and is well suited for

low-voltage applications such as DC/DC converters.

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

N-channel

P-channel

-60

V_DS

V_GS

Drain-Source Voltage

±20

Gate-Source Voltage

±20

I_D@ TA=25°C

I_D@ T_A=70°C

I_DM

Continuous Drain Current³

Pulsed Drain Current¹

-4.2

4.7

-3.3

-30

P_D@ T_A=25°C

Total Power Dissipation

Linear Derating Factor

2.0

0.016

W/°C

°C

T_STG

T_J

Storage Temperature Range

Operating Junction Temperature Range

-55 to 150

Thermal Data

Symbol

Parameter

Value

62.5

Unit

Rthj-a

Thermal Resistance Junction-ambient³

Max.

°C/W

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SSM4575M

N-channel Electrical Characteristics @ T _j=25^oC(unless otherwise specified)

Symbol

BV_DSS

Parameter

Test Conditions

V_GS=0V, I_D=250uA

Min. Typ. Max. Units

Drain-Source Breakdown Voltage

0.04

DBV_DSS/DT_j

Breakdown Voltage Temperature Coefficient Reference to 25°C,I_D=1mA

V/°C

R_DS(ON)

Static Drain-Source On-Resistance²V_GS=10V, I_D=5A

_GS=4.5V, I_D=3A

V_GS(th)

g_fs

Gate Threshold Voltage

Forward Transconductance

Drain-Source Leakage Current (T_j=25^oC)

Drain-Source Leakage Current (T_j=70^oC)

Gate-Source Leakage

Total Gate Charge²

V_DS=V_GS, I_D=250uA

V_DS=10V, I_D=5A

V_DS=60V, V_GS=0V

V_DS=48V, V_GS=0V

V_GS=±20V

I_DSS

I_GSS

Q_g

±100

I_D=5A

Q_gs

Q_gd

t_d(on)

t_r

Gate-Source Charge

Gate-Drain ("Miller") Charge

Turn-on Delay Time²

Rise Time

V_DS=48V

V_GS=4.5V

V_DS=30V

I_D=1A

t_d(off)

t_f

Turn-off Delay Time

R_G=3.3W ,V_GS=10V

R_D=30W

Fall Time

C_iss

C_oss

C_rss

Input Capacitance

V_GS=0V

1670 2670

Output Capacitance

V_DS=25V

160

117

Reverse Transfer Capacitance

f=1.0MHz

Source-Drain Diode

Symbol

Parameter

Test Conditions

Min. Typ. Max. Units

V_SD

t_rr

Forward On Voltage²

Reverse Recovery Time²

I_S=1.7A, V_GS=0V

I_S=5A, V_GS=0V

dI/dt=100A/µs

1.2

Q_rr

Reverse Recovery Charge

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SSM4575M

P-channel Electrical Characteristics @ T _j=25^oC(unless otherwise specified)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Units

BV_DSS

Drain-Source Breakdown Voltage

V_GS=0V, I_D=-250uA

-60

V/°C

DBV_DSS/DTj

Breakdown Voltage Temperature Coefficient Reference to 25°C,I_D=-1mA

Static Drain-Source On-Resistance²V_GS=-10V, I_D=-4A

-0.04

R_DS(ON)

V_GS=-4.5V, I_D=-3A

V_GS(th)

g_fs

Gate Threshold Voltage

V_DS=V_GS, I_D=-250uA

V_DS=-10V, I_D=-4A

V_DS=-60V, V_GS=0V

V_DS=-48V, V_GS=0V

V_GS=±20V

-1

-3

Forward Transconductance

Drain-Source Leakage Current (T=25^oC)

I_DSS

-1

Drain-Source Leakage Current (T=70^oC)

-25

I_GSS

Q_g

Gate-Source Leakage

Total Gate Charge²

Gate-Source Charge

Gate-Drain ("Miller") Charge

Turn-on Delay Time²

Rise Time

±100

I_D=-4A

Q_gs

Q_gd

t_d(on)

t_r

V_DS=-48V

V_GS=-4.5V

V_DS=-30V

I_D=-1A

t_d(off)

t_f

Turn-off Delay Time

Fall Time

R_G=3.3W ,V_GS=-10V

R_D=30W

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

V_GS=0V

1780 2850

V_DS=-25V

157

130

f=1.0MHz

Source-Drain Diode

Symbol

Parameter

Forward On Voltage²

Reverse Recovery Time²

Test Conditions

I_S=-1.7A, V_GS=0V

I_S=-4A, V_GS=0V

Min. Typ. Max. Units

V_SD

t_rr

-1.2

Q_rr

Reverse Recovery Charge

dI/dt=-100A/µs

Notes:

1.Pulse width limited by max. junction temperature.

2.Pulse width <300us , duty cycle <2%.

3.Surface mounted on 1 in²copper pad of FR4 board ; 135°C/W when mounted on min. copper pad.

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SSM4575M

N-channel

T _A= 25 ^oC

T _A= 1 5 0 ^oC

10V

7.0V

5.0V

4.5V

10V

7.0V

5.0V

4.5V

_G=3.0V

V_DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1.8

I _D=5A

1.6

1.4

1.2

1.0

0.8

0.6

I _D= 3 A

_A=25 ^oC

V_G=10V

-50

100

150

T _j, Junction Temperature ( ^oC)

V_GS, Gate-to-Source Voltage (V)

Fig 3. On-Resistance vs. Gate Voltage

Fig 4. Normalized On-Resistance

v.s. Junction Temperature

1.5

1.3

1.1

0.9

0.7

0.5

0.3

T _j=150 ^o

T _j=25 ^oC

-50

100

150

0.2

0.4

0.6

0.8

1.2

T _j,Junction Temperature ( ^oC)

V_SD, Source-to-Drain Voltage (V)

Fig 5. Forward Characteristic of

Reverse Diode

Fig 6. Gate Threshold Voltage vs.

Junction Temperature

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SSM4575M

N-channel

f=1.0MHz

10000

1000

100

I _D=5A

V_DS=48V

C _iss

C _oss

C _rss

V_DS, Drain-to-Source Voltage (V)

Q_G, Total Gate Charge (nC)

Fig 7. Gate Charge Characteristics

Fig 8. Typical Capacitance Characteristics

100

Duty factor=0.5

0.2

0.1

0.05

1ms

0.02

10ms

0.01

P_DM

0.01

Single Pulse

100ms

0.1

T _A=25 ^oC

Duty factor = t/T

Peak T_j= P_DMx R_thja+ T_a

R_thja=135^oC/W

Single Pulse

0.01

0.001

0.1

100

1000

0.0001

0.001

0.01

0.1

100

1000

V_DS, Drain-to-Source Voltage (V)

t , Pulse Width (s)

Fig 9. Maximum Safe Operating Area

Fig 10. Effective Transient Thermal Impedance

V_DS

V_G

90%

Q_G

4.5V

Q_GS

Q_GD

10%

V_GS

t_r

_d(off)t_f

t_d(on)

Charge

Fig 11. Switching Time Waveform

Fig 12. Gate Charge Waveform

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SSM4575M

P-channel

T _A= 1 5 0 ^oC

T _A= 25 ^oC

-10V

-7.0V

-5.0V

-4.5V

-10V

-7.0V

-5.0V

-4.5V

V _G=-3.0V

-V _DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1.8

1.6

1.4

1.2

1.0

0.8

0.6

I _D= - 4 A

V _G=-10V

I _D= - 3 A

T _A=25°C

-50

100

150

T _j, Junction Temperature ( ^oC)

Fig 4. Normalized On-Resistance

vs. Junction Temperature

-V _GS,Gate-to-Source Voltage (V)

Fig 3. On-Resistance vs. Gate Voltage

1.6

1.3

1.1

0.8

0.6

0.3

T _j=150 ^oC

T _j=25 ^oC

0.2

0.4

0.6

0.8

1.2

-50

100

150

T _j, Junction Temperature ( ^oC)

Fig 6. Gate Threshold Voltage vs.

Junction Temperature

-V _SD, Source-to-Drain Voltage (V)

Fig 5. Forward Characteristic of

Reverse Diode

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SSM4575M

P-channel

f=1.0MHz

10000

1000

100

I _D=-4A

_DS=-48V

C _iss

C _oss

C _rss

0.0

10.0

20.0

30.0

40.0

50.0

60.0

-V _DS, Drain-to-Source Voltage (V)

Q _G, Total Gate Charge (nC)

Fig 7. Gate Charge Characteristics

Fig 8. Typical Capacitance Characteristics

100

Duty factor=0.5

0.2

0.1

0.05

1ms

10ms

100ms

0.02

0.01

P_DM

0.01

Single Pulse

0.1

T _A=25 ^oC

Duty factor = t/T

Peak T_j= P_DMx R_thja+ T_a

R_thja=135^oC/W

Single Pulse

0.001

0.01

0.0001

0.001

0.01

0.1

100

1000

0.1

100

1000

-V _DS, Drain-to-Source Voltage (V)

t , Pulse Width (s)

Fig 9. Maximum Safe Operating Area

Fig 10. Effective Transient Thermal Impedance

V_G

V_DS

90%

Q_G

-4.5V

Q_GS

Q_GD

10%

V_GS

t_d(off)

t_r

t_d(on)

t_f

Charge

Fig 12. Gate Charge Waveform

Fig 11. Switching Time Waveform

Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no

guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no

responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its

use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including

without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to

the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of

Silicon Standard Corporation or any third parties.

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