74ACT573TTR [STMICROELECTRONICS]

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED); 八D型具有三态输出锁存器(非反相)
74ACT573TTR
型号: 74ACT573TTR
厂家: ST    ST
描述:

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)
八D型具有三态输出锁存器(非反相)

总线驱动器 总线收发器 锁存器 逻辑集成电路 光电二极管 输出元件
文件: 总11页 (文件大小:237K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
74ACT573  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUTS (NON INVERTED)  
HIGH SPEED: t = 5ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
ORDER CODES  
PACKAGE  
|I | = I = 24mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
TUBE  
t
t
PLH  
PHL  
DIP  
SOP  
74ACT573B  
74ACT573M  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
74ACT573MTR  
74ACT573TTR  
V
CC  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 573  
IMPROVED LATCH-UP IMMUNITY  
When the LE is taken low, the Q outputs will be  
latched precisely or inversely at the logic level of D  
input data. While the (OE) input is low, the 8  
outputs will be in a normal logic state (high or low  
logic level) and while high level the outputs will be  
in a high impedance state.  
This device is designed to interface directly High  
Speed CMOS systems with TTL and NMOS  
components.  
DESCRIPTION  
The 74ACT573 is an advanced high-speed CMOS  
OCTAL D-TYPE LATCH with 3 STATE OUTPUT  
NON INVERTING fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
technology.  
2
These 8 bit D-Type latch are controlled by a latch  
enable input (LE) and an output enable input (OE).  
While the LE inputs is held at a high level, the Q  
outputs will follow the data input .  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/11  
74ACT573  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
PIN DESCRIPTION  
PIN No  
SYMBOL  
OE  
NAME AND FUNCTION  
1
3 State Output Enable  
Input (Active LOW)  
2, 3, 4, 5, 6,  
7, 8, 9  
D0 to D7 Data Inputs  
12, 13, 14,  
15, 16, 17,  
18, 19  
Q0 to Q7 3-State Latch Outputs  
11  
10  
20  
LE  
Latch Enable Input  
Ground (0V)  
GND  
V
Positive Supply Voltage  
CC  
TRUTH TABLE  
INPUTS  
OUTPUT  
Q
OE  
LE  
D
H
L
L
L
X
L
X
X
L
Z
NO CHANGE  
H
H
L
H
H
X : Don’t care  
Z : High Impedance  
NOTE: Outputs are latched at the time when the input is taken LOW logic level  
LOGIC DIAGRAM  
This logic diagram has not be used to estimate propagation delays  
2/11  
74ACT573  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Unit  
V
Supply Voltage  
-0.5 to +7  
V
V
CC  
V
DC Input Voltage  
-0.5 to V + 0.5  
I
CC  
V
DC Output Voltage  
DC Input Diode Current  
DC Output Diode Current  
DC Output Current  
-0.5 to V + 0.5  
V
O
CC  
I
± 20  
± 20  
mA  
mA  
mA  
mA  
°C  
°C  
IK  
I
OK  
I
± 50  
O
I
or I  
T
DC V  
or Ground Current  
CC  
± 400  
CC  
GND  
Storage Temperature  
-65 to +150  
300  
stg  
T
Lead Temperature (10 sec)  
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is  
not implied.  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Value  
Unit  
V
Supply Voltage  
4.5 to 5.5  
V
V
CC  
V
Input Voltage  
0 to V  
I
CC  
V
Output Voltage  
0 to V  
V
O
CC  
T
Operating Temperature  
-55 to 125  
8
°C  
ns/V  
op  
Input Rise and Fall Time V = 4.5 to 5.5V (note 1)  
dt/dv  
CC  
1) V from 0.8V to 2.0V  
IN  
3/11  
74ACT573  
DC SPECIFICATIONS  
Test Condition  
Value  
T
= 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
A
V
CC  
(V)  
Min. Typ. Max. Min. Max. Min. Max.  
V
High Level Input  
Voltage  
4.5  
5.5  
4.5  
5.5  
4.5  
V
= 0.1 V or  
O
2.0  
2.0  
1.5  
1.5  
2.0  
2.0  
2.0  
2.0  
IH  
V
-0.1V  
V
V
CC  
V
Low Level Input  
Voltage  
V = 0.1 V or  
O
1.5  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
IL  
V
-0.1V  
1.5  
CC  
V
High Level Output  
Voltage  
I =-50 µA  
4.4  
5.4  
4.49  
4.4  
5.4  
4.4  
5.4  
3.7  
4.7  
OH  
O
I =-50 µA  
5.5  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
5.49  
O
I =-24 mA  
3.86  
4.86  
3.76  
4.76  
O
I =-24 mA  
O
V
Low Level Output  
Voltage  
I =50 µA  
0.001 0.1  
0.001 0.1  
0.36  
0.1  
0.1  
0.1  
0.1  
0.5  
0.5  
OL  
O
V
I =50 µA  
O
I =24 mA  
0.44  
0.44  
O
I =24 mA  
0.36  
O
I
Input Leakage Cur-  
rent  
I
V = V  
or GND  
CC  
5.5  
± 0.1  
± 1  
± 1  
µA  
µA  
I
I
High Impedance  
Output Leakege  
Current  
OZ  
V = V or V  
IL  
I
IH  
5.5  
± 0.5  
± 5  
± 5  
V
= V or GND  
CC  
O
I
Max I /Input  
V = V - 2.1V  
5.5  
5.5  
0.6  
1.5  
40  
1.6  
80  
mA  
CCT  
CC  
I
CC  
I
Quiescent Supply  
Current  
CC  
V = V  
or GND  
CC  
4
µA  
I
I
V
= 1.65 V max  
= 3.85 V min  
75  
50  
mA  
mA  
OLD  
OLD  
Dynamic Output  
Current (note 1, 2)  
5.5  
I
V
OHD  
-75  
-50  
OHD  
1) Maximum test duration 2ms, one output loaded at time  
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50  
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, R = 500 , Input t = t = 3ns)  
L
L
r
f
Test Condition  
Value  
-40 to 85°C -55 to 125°C Unit  
Min. Typ. Max. Min. Max. Min. Max.  
T
= 25°C  
Symbol  
Parameter  
A
V
CC  
(V)  
t
t
t
Propagation Delay  
Time LE to Q  
PLH PHL  
(*)  
5.0  
5.0  
5.5  
6.5  
1.0  
0.0  
0.0  
10.0  
10.0  
10.0  
11.0  
3.0  
12.0  
12.0  
12.0  
12.0  
4.0  
12.0  
12.0  
12.0  
12.0  
4.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
t
Propagation Delay  
Time D to Q  
PLH PHL  
(*)  
(*)  
(*)  
(*)  
(*)  
(*)  
t
t
Output Enable  
Time  
PZL PZH  
t
t
Output Disable  
Time  
PLZ PHZ  
t
Minimum Pulse  
Width HIGH LE  
W
t
Setup Time D to  
LE, HIGH or LOW  
s
2.0  
3.0  
3.0  
t
Hold Time D to LE,  
HIGH or LOW  
h
2.0  
3.0  
3.0  
(*) Voltage range is 5.0V ± 0.5V  
4/11  
74ACT573  
CAPACITIVE CHARACTERISTICS  
Test Condition  
Value  
-40 to 85°C -55 to 125°C Unit  
T
= 25°C  
Symbol  
Parameter  
A
V
CC  
(V)  
Min. Typ. Max. Min. Max. Min. Max.  
C
Input Capacitance  
5.0  
5.0  
4
pF  
pF  
IN  
Output  
Capacitance  
C
8
OUT  
C
Power Dissipation  
Capacitance (note  
1)  
PD  
f
= 10MHz  
5.0  
25  
pF  
IN  
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without  
PD  
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I  
= C x V x f + I /n (per circuit)  
PD CC IN CC  
CC(opr)  
TEST CIRCUIT  
TEST  
SWITCH  
t
t
t
, t  
Open  
PLH PHL  
, t  
2V  
CC  
PZL PLZ  
, t  
Open  
PZH PHZ  
C
R
R
= 50pF or equivalent (includes jig and probe capacitance)  
L
L
T
= R = 500or equivalent  
1
= Z  
of pulse generator (typically 50)  
OUT  
5/11  
74ACT573  
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH,  
Dn to LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)  
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)  
6/11  
74ACT573  
WAVEFORM 3: PROPAGATION DELAYS TIME (f=1MHz; 50% duty cycle)  
7/11  
74ACT573  
Plastic DIP-20 (0.25) MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
0.254  
1.39  
TYP.  
MAX.  
MIN.  
0.010  
0.055  
MAX.  
a1  
B
b
1.65  
0.065  
0.45  
0.25  
0.018  
0.010  
b1  
D
E
e
25.4  
1.000  
8.5  
2.54  
0.335  
0.100  
0.900  
e3  
F
22.86  
7.1  
0.280  
0.155  
I
3.93  
L
3.3  
0.130  
Z
1.34  
0.053  
P001J  
8/11  
74ACT573  
SO-20 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
TYP.  
MAX.  
2.65  
0.20  
2.45  
0.49  
0.32  
MIN.  
MAX.  
0.104  
0.007  
0.096  
0.019  
0.012  
A
a1  
a2  
b
0.10  
0.004  
0.35  
0.23  
0.013  
0.009  
b1  
C
0.50  
0.020  
c1  
D
45 (typ.)  
12.60  
10.00  
13.00  
10.65  
0.496  
0.393  
0.512  
0.419  
E
e
1.27  
0.050  
0.450  
e3  
F
11.43  
7.40  
0.50  
7.60  
1.27  
0.75  
0.291  
0.19  
0.299  
0.050  
0.029  
L
M
S
8 (max.)  
P013L  
9/11  
74ACT573  
TSSOP20 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
TYP.  
MAX.  
1.1  
MIN.  
MAX.  
0.433  
0.006  
0.374  
0.0118  
0.0079  
0.260  
0.256  
0.176  
A
A1  
A2  
b
0.05  
0.85  
0.19  
0.09  
6.4  
0.10  
0.9  
0.15  
0.95  
0.30  
0.2  
0.002  
0.335  
0.0075  
0.0035  
0.252  
0.246  
0.169  
0.004  
0.354  
c
D
6.5  
6.4  
6.6  
0.256  
0.252  
E
6.25  
4.3  
6.5  
E1  
e
4.4  
4.48  
0.173  
0.65 BSC  
4o  
0.0256 BSC  
4o  
K
0o  
8o  
0o  
8o  
L
0.50  
0.60  
0.70  
0.020  
0.024  
0.028  
A2  
A
K
L
b
e
A1  
E
c
D
E1  
PIN 1 IDENTIFICATION  
1
10/11  
74ACT573  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the  
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from  
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications  
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information  
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or  
systems without express written approval of STMicroelectronics.  
© The ST logo is a registered trademark of STMicroelectronics  
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco  
Singapore - Spain - Sweden - Switzerland - United Kingdom  
© http://www.st.com  
11/11  

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