74LVQ138MTR [STMICROELECTRONICS]
3 TO 8 LINE DECODER (INVERTING); 3至8线译码器（反相）
| 型号： | 74LVQ138MTR |
| 厂家： | 
ST |
| 描述： | 3 TO 8 LINE DECODER (INVERTING) |
| 文件： | 总12页 (文件大小：325K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVQ138
3 TO 8 LINE DECODER (INVERTING)
■
HIGH SPEED:
= 5.5ns (TYP.) at V = 3.3 V
t
PD
CC
■
■
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
= 4 µA (MAX.) at T =25°C
A
CC
■
■
■
LOW NOISE:
= 0.2V (TYP.) at V = 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
SOP
TSSOP
V
OLP
CC
Table 1: Order Codes
PACKAGE
|I | = I = 12mA (MIN) at V = 3.0 V
T & R
OH
OL
CC
■
■
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
SOP
74LVQ138MTR
74LVQ138TTR
TSSOP
t
t
PLH
PHL
■
■
■
OPERATING VOLTAGE RANGE:
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
V
CC
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ138 is a low voltage CMOS 3 TO 8
LINE DECODER (INVERTING) fabricated with
sub-micron silicon gate and double-layer metal
wiring C MOS technology. It is ideal for low power
and low noise 3.3V applications.
2
Figure 1: Pin Connection And IEC Logic Symbols
Rev. 5
1/12
July 2004
74LVQ138
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
SYMBOL
NAME AND FUNCTION
1, 2, 3
4, 5
6
A, B, C
Address Inputs
G2A, G2B Enable Inputs
G1
Enable Input
Outputs
15, 14, 13,
12, 11, 10, 9,
7
Y0 to Y7
8
GND
Ground (0V)
16
V
Positive Supply Voltage
CC
Table 3: Truth Table
INPUTS
OUTPUTS
ENABLE
G2A
SELECT
B
G2B
G1
C
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
L
X
X
X
L
X
X
X
L
X
X
X
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
X
X
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
X : Don’t Care
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
2/12
74LVQ138
Table 4: Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7
V
V
CC
V
DC Input Voltage
-0.5 to V + 0.5
I
CC
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
O
CC
I
± 20
± 20
mA
mA
mA
mA
°C
°C
IK
I
OK
I
± 50
O
I
or I
DC V or Ground Current
± 200
CC
GND
CC
T
Storage Temperature
-65 to +150
300
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Table 5: Recommended Operating Conditions
Symbol
Parameter
Value
Unit
V
Supply Voltage (note 1)
Input Voltage
2 to 3.6
V
V
CC
V
0 to V
I
CC
V
Output Voltage
0 to V
V
O
CC
T
Operating Temperature
-55 to 125
0 to 10
°C
ns/V
op
Input Rise and Fall Time V = 3.0V (note 2)
dt/dv
CC
1) Truth Table guaranteed: 1.2V to 3.6V
2) V from 0.8V to 2V
IN
Table 6: DC Specifications
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
High Level Input
Voltage
IH
2.0
2.0
2.0
V
V
3.0 to
3.6
V
Low Level Input
Voltage
IL
0.8
0.8
0.8
V
High Level Output
Voltage
I =-50 µA
2.9
2.99
2.9
2.48
2.2
2.9
2.48
2.2
OH
O
I =-12 mA
3.0
3.0
2.58
V
V
O
I =-24 mA
O
V
Low Level Output
Voltage
I =50 µA
0.002 0.1
0.1
0.1
OL
O
I =12 mA
0
0.36
0.44
0.55
0.44
0.55
O
I =24 mA
O
I
Input Leakage
Current
I
V = V or GND
3.6
3.6
± 0.1
± 1
± 1
µA
µA
I
CC
I
Quiescent Supply
Current
CC
V = V or GND
4
40
40
I
CC
I
V
= 0.8 V max
= 2 V min
36
25
mA
mA
OLD
OLD
Dynamic Output
Current (note 1, 2)
3.6
I
V
OHD
-25
-25
OHD
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
3/12
74LVQ138
Table 7: Dynamic Switching Characteristics
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
Dynamic Low
0.2
0.8
OLP
Voltage Quiet
Output (note 1, 2)
3.3
3.3
V
V
V
-0.8
2
-0.2
OLV
V
Dynamic High
Voltage Input (note
1, 3)
IHD
C = 50 pF
L
V
Dynamic Low
Voltage Input (note
1, 3)
3.3
0.8
V
ILD
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V ), 0V to threshold
ILD
(V ), f=1MHz.
IHD
Table 8: AC Electrical Characteristics (C = 50 pF, R = 500 Ω, Input t = t = 3ns)
L
L
r
f
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
t
t
t
t
Propagation Delay
Time
A, B, C to Y
2.7
6.6
5.5
6.7
5.6
6.3
5.2
10.5
8.0
12.0
9.0
14.0
10.5
14.0
10.5
14.0
10.5
PLH PHL
ns
ns
ns
ns
(*)
3.3
t
Propagation Delay
Time
G1 to Y
2.7
10.5
8.0
12.0
9.0
PLH PHL
(*)
3.3
t
Propagation Delay
Time
G2A or G2B to Y
2.7
10.5
8.0
12.0
9.0
PLH PHL
(*)
3.3
t
t
Output To Output
Skew Time
(note1, 2)
2.7
0.5
0.5
1.0
1.0
1.0
1.0
1.0
1.0
OSLH
(*)
OSHL
3.3
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
= |t
- t
|, t
= |t
- t
|)
OSLH
PLHm PLHn OSHL
PHLm PHLn
Table 9: Capacitive Characteristics
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
3.3
4
pF
pF
IN
C
Power Dissipation
Capacitance (note
1)
PD
f
= 10MH
3.3
50
IN
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I
CC(opr)
PD CC IN CC
4/12
74LVQ138
Figure 4: Test Circuit
C
L
R
L
R
T
= 50pF or equivalent (includes jig and probe capacitance)
= 500Ω or equivalent
= Z
of pulse generator (typically 50Ω)
OUT
Figure 5: Waveform - Propagation Delays For Inverting Outputs (f=1MHz; 50% duty cycle)
5/12
74LVQ138
Figure 6: Waveform - Propagation Delays For Non-inverting Outputs (f=1MHz; 50% duty cycle)
6/12
74LVQ138
SO-16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.25
1.64
0.46
0.25
MIN.
MAX.
0.068
0.010
0.063
0.018
0.010
A
a1
a2
b
0.1
0.004
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45° (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8° (max.)
0016020D
7/12
74LVQ138
TSSOP16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0079
0.201
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
5.1
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.004
0.039
1
0.19
0.09
4.9
c
D
5
6.4
0.197
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0˚
8˚
0˚
8˚
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
8/12
74LVQ138
Tape & Reel SO-16 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
6.65
10.5
2.3
0.882
0.262
0.414
0.090
0.161
0.319
Ao
Bo
Ko
Po
P
6.45
10.3
2.1
0.254
0.406
0.082
0.153
0.311
3.9
4.1
7.9
8.1
9/12
74LVQ138
Tape & Reel TSSOP16 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
6.9
5.5
1.8
4.1
8.1
0.882
0.272
0.217
0.071
0.161
0.319
Ao
Bo
Ko
Po
P
6.7
5.3
1.6
3.9
7.9
0.264
0.209
0.063
0.153
0.311
10/12
74LVQ138
Table 10: Revision History
Date
Revision
Description of Changes
Ordering Codes Revision - pag. 1.
29-Jul-2004
5
11/12
74LVQ138
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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