74VHC174TTR [STMICROELECTRONICS]
HEX D-TYPE FLIP FLOP WITH CLEAR; HEX D型触发器与Clear FLOP
| 型号： | 74VHC174TTR |
| 厂家： | 
ST |
| 描述： | HEX D-TYPE FLIP FLOP WITH CLEAR |
| 文件： | 总14页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74VHC174
HEX D-TYPE FLIP FLOP WITH CLEAR
■
■
■
HIGH SPEED:
= 175MHz (TYP.) at V = 5V
f
MAX
CC
LOW POWER DISSIPATION:
= 4 µA (MAX.) at T =25°C
I
CC
A
HIGH NOISE IMMUNITY:
= V = 28% V (MIN.)
V
NIH
NIL
CC
SOP
TSSOP
■
■
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
OH
OL
Table 1: Order Codes
PACKAGE
■
■
■
t
t
PLH
PHL
T & R
OPERATING VOLTAGE RANGE:
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
SOP
74VHC174MTR
74VHC174TTR
V
CC
TSSOP
■
■
IMPROVED LATCH-UP IMMUNITY
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
LOW NOISE: V
= 0.8V (MAX.)
OLP
DESCRIPTION
The 74VHC174 is an advanced high-speed
CMOS HEX D-TYPE FLIP FLOP WITH CLEAR
fabricated with sub-micron silicon gate and
2
double-layer metal wiring C MOS technology.
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the clock pulse.
Figure 1: Pin Connection And IEC Logic Symbols
Rev. 4
1/14
November 2004
74VHC174
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
SYMBOL
NAME AND FUNCTION
1
CLEAR
Asynchronous Master
Reset (Active LOW)
2, 5, 7, 10,
12, 15
Q0 to Q5 Flip-Flop Outputs
3, 4, 6, 11,
13, 14
D0 to D5 Data Inputs
9
CLOCK
GND
Clock Input (LOW-to-HIGH,
Edge Triggered)
8
Ground (0V)
16
V
Positive Supply Voltage
CC
Table 3: Truth Table
INPUTS
OUTPUTS
FUNCTION
CLEAR
D
X
L
CLOCK
Q
L
L
X
CLEAR
H
L
H
H
H
X
H
Q
NO CHANGE
n
X : Don’t Care
Figure 3: Logic Diagram
This logic diagram has not to be used to estimate propagation delays
2/14
74VHC174
Table 4: Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7.0
-0.5 to +7.0
V
V
CC
V
DC Input Voltage
I
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
O
CC
I
- 20
± 20
mA
mA
mA
mA
°C
°C
IK
I
OK
I
± 25
O
I
or I
DC V or Ground Current
± 50
CC
GND
CC
T
Storage Temperature
-65 to +150
300
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
Parameter
Value
Unit
V
Supply Voltage
2 to 5.5
0 to 5.5
V
V
CC
V
Input Voltage
I
V
Output Voltage
0 to V
V
O
CC
T
Operating Temperature
-55 to 125
°C
op
Input Rise and Fall Time (note 1) (V = 3.3 ± 0.3V)
0 to 100
0 to 20
CC
dt/dv
ns/V
(V
= 5.0 ± 0.5V)
CC
1) V from 30% to 70% of V
IN
CC
3/14
74VHC174
Table 6: DC Specifications
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
High Level Input
Voltage
2.0
1.5
1.5
1.5
IH
V
V
3.0 to
5.5
0.7VCC
0.7VCC
0.7VCC
V
Low Level Input
Voltage
2.0
0.5
0.5
0.5
IL
3.0 to
5.5
0.3VCC
0.3VCC
0.3VCC
V
High Level Output
Voltage
I =-50 µA
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
1.9
2.9
2.0
3.0
4.5
1.9
2.9
1.9
2.9
4.4
2.4
3.7
OH
O
I =-50 µA
O
I =-50 µA
4.4
4.4
V
V
O
I =-4 mA
2.58
3.94
2.48
3.8
O
I =-8 mA
O
V
Low Level Output
Voltage
I =50 µA
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
OL
O
I =50 µA
O
I =50 µA
0.1
0.1
0.1
O
I =4 mA
0.36
0.36
0.44
0.44
0.55
0.55
O
I =8 mA
O
I
Input Leakage
Current
0 to
5.5
I
V = 5.5V or GND
± 0.1
± 1
± 1
µA
µA
I
I
Quiescent Supply
Current
CC
V = V or GND
5.5
4
40
40
I
CC
4/14
74VHC174
Table 7: AC Electrical Characteristics (Input t = t = 3ns)
r
f
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T = 25°C
Symbol
Parameter
A
V
C
L
(V) (pF)
CC
(*)
t
Propagation Delay
Time
CLOCK to Q
15
50
15
50
15
50
15
50
5.8
7.5
4.1
5.5
7.4
9.9
5.1
6.6
11.0
14.5
7.2
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
13.0
16.5
8.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
13.0
16.5
8.5
PLH
3.3
t
(*)
PHL
3.3
ns
ns
(**)
(**)
(*)
5.0
5.0
9.2
10.5
13.5
17.0
9.0
10.5
13.5
17.0
9.0
t
Propagation Delay
Time
CLEAR to Q
11.4
14.9
7.6
PHL
3.3
(*)
3.3
(**)
(**)
(*)
5.0
5.0
9.6
11.0
5.0
11.0
5.0
t
CLEAR Pulse
Width LOW
5.0
W
3.3
ns
ns
(**)
5.0
5.0
5.0
5.0
3.3
(*)
t
CLEAR Pulse
Width HIGH or
LOW
5.0
5.0
5.0
W
(**)
(*)
5.0
5.0
4.5
0.0
0.5
5.0
6.0
4.5
0.0
0.5
5.0
6.0
4.5
0.0
0.5
5.0
t
Setup Time D to
CLOCK, HIGH or
LOW
s
3.3
ns
ns
ns
(**)
5.0
3.3
(*)
t
Hold Time D to
CLOCK, HIGH or
LOW
h
(**)
(*)
5.0
t
Recovery Time
CLEAR to CLOCK
3.0
2.5
3.0
2.5
3.0
2.5
REM
3.3
(**)
5.0
3.3
3.3
(*)
(*)
f
Maximum Clock
Frequency
15
50
15
50
95
55
150
85
80
50
80
50
MAX
MHz
(**)
(**)
130
90
175
120
110
80
110
80
5.0
5.0
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
Table 8: Capacitive Characteristics
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
6
10
10
10
pF
pF
IN
C
Power Dissipation
Capacitance
(note 1)
PD
15
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
Flip-Flop)
= C x V x f + I /6 (per
CC(opr)
PD CC IN CC
5/14
74VHC174
Table 9: Dynamic Switching Characteristics
Test Condition
Value
T = 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
Dynamic Low
0.3
0.8
OLP
Voltage Quiet
Output (note 1, 2)
5.0
V
V
V
V
-0.8
3.5
-0.3
OLV
Dynamic High
Voltage Input
(note 1, 3)
V
C = 50 pF
L
5.0
5.0
IHD
Dynamic Low
Voltage Input
(note 1, 3)
V
1.5
ILD
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V ), 0V to threshold
ILD
(V ), f=1MHz.
IHD
Figure 4: Test Circuit
C
R
=15/50pF or equivalent (includes jig and probe capacitance)
L
T
= Z
of pulse generator (typically 50Ω)
OUT
6/14
74VHC174
Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)
Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
7/14
74VHC174
Figure 7: Waveform - Recovery Time (f=1MHz; 50% duty cycle)
8/14
74VHC174
SO-16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.25
1.64
0.46
0.25
MIN.
MAX.
0.068
0.010
0.063
0.018
0.010
A
a1
a2
b
0.1
0.004
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45° (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8° (max.)
0016020D
9/14
74VHC174
TSSOP16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0079
0.201
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
5.1
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.004
0.039
1
0.19
0.09
4.9
c
D
5
6.4
0.197
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0˚
8˚
0˚
8˚
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
10/14
74VHC174
Tape & Reel SO-16 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
6.65
10.5
2.3
0.882
0.262
0.414
0.090
0.161
0.319
Ao
Bo
Ko
Po
P
6.45
10.3
2.1
0.254
0.406
0.082
0.153
0.311
3.9
4.1
7.9
8.1
11/14
74VHC174
Tape & Reel TSSOP16 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
6.9
5.5
1.8
4.1
8.1
0.882
0.272
0.217
0.071
0.161
0.319
Ao
Bo
Ko
Po
P
6.7
5.3
1.6
3.9
7.9
0.264
0.209
0.063
0.153
0.311
12/14
74VHC174
Table 10: Revision History
Date
Revision
Description of Changes
Order Codes Revision - pag. 1.
12-Nov-2004
4
13/14
74VHC174
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
© 2004 STMicroelectronics - All Rights Reserved
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14/14
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