ESDA25L [STMICROELECTRONICS]

DUAL TRANSIL ARRAY FOR ESD PROTECTION; 双TRANSIL阵列的ESD保护


型号：	ESDA25L
厂家：	ST
描述：	DUAL TRANSIL ARRAY FOR ESD PROTECTION 双TRANSIL阵列的ESD保护瞬态抑制器二极管光电二极管 PC 局域网
文件：	总6页 (文件大小：62K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ESDAxxL

DUAL TRANSIL ARRAY

FOR ESD PROTECTION

Application Specific Discretes

A.S.D.

APPLICATIONS

Where transient overvoltage protection in ESD

sensitive equipment is required, such as :

- COMPUTERS

- PRINTERS

- COMMUNICATION SYSTEMS

It is particulary recommended for the RS232 I/O

port protection where the line interface withstands

only with 2kV ESD surges.

FEATURES

SOT23

2 UNIDIRECTIONAL TRANSIL FUNCTIONS.

LOW LEAKAGE CURRENT : I_Rmax. < 20µA at

V_BR.

300 W PEAK PULSE POWER (8/20µs)

DESCRIPTION

FUNCTIONAL DIAGRAM

The ESDAxxL is a dual monolithic voltage

suppressor designed to protect components which

are connected to data and transmission lines

against ESD.

It clamps the voltage just above the logic level

supply for positive transients, and to a diode drop

below ground for negative transients.

It can also work as bidirectionnal suppressor by

connecting only pin1 and 2.

BENEFITS

High ESD protection level : up to 25 kV.

High integration.

Suitable for high density boards.

COMPLIES WITH THE FOLLOWING STANDARDS :

IEC61000-4-2 level 4

MIL STD 883C-Method 3015-6 : class 3.

(human body model)

Marchr 2000 - Ed: 4A

1/6

ESDAxxL

ABSOLUTE MAXIMUM RATINGS (T_amb= 25°C)

Symbol

Parameter

Value

Unit

V_PP

Electrostatic discharge

MIL STD 883C - Method 3015-6

IEC61000-4-2 air discharge

IEC61000-4-2 contact discharge

P_PP

Peak pulse power (8/20 µs)

300

T_stg

T_j

Storage temperature range

Maximum junction temperature

- 55 to + 150

150

°C

T_L

Maximum lead temperature for soldering during 10s

Operating temperature range

260

°C

T_op

- 40 to + 125

note 1: Evolution of functional parameters is given by curves.

ELECTRICAL CHARACTERISTICS (T_amb= 25°C)

Symbol

V_RM

V_BR

V_CL

I_RM

Parameter

Stand-off voltage

Breakdown voltage

Clamping voltage

Leakage current

I_PP

Peak pulse current

Voltage temperature coefficient

Capacitance

αT

Slope:

Dynamic resistance

Forward voltage drop

V_F

I_R

Types

V_BR

I_RM

V_RM

typ.

αT

max.

V_F

I_F

min.

max.

typ.

max.

note 1

mΩ

note 2 0V bias

µA

10^-4/ C

5.3

5.9

280

220

1.25

200

ESDA5V3L

ESDA6V1L

ESDA14V2L

ESDA25L

6.1

14.2

7.2

15.8

5.25

350

650

140

1.25

1.2

200

1000

note 1 : Square pulse Ipp = 15A, tp=2.5µs.

note 2 : ∆ V

= αT* (Tamb -25°C) * V

(25°C)

2/6

ESDAxxL

CALCULATION OF THE CLAMPING VOLTAGE

USE OF THE DYNAMIC RESISTANCE

The ESDA family has been designed to clamp fast

spikes like ESD. Generally the PCB designers

need to calculate easily the clamping voltage V_CL.

This is why we give the dynamic resistance in

addition to the classical parameters. The voltage

across the protection cell can be calculated with

the following formula:

As the value of the dynamic resistance remains

stable for a surge duration lower than 20µs, the

2.5µs rectangular surge is well adapted. In

addition both rise and fall times are optimized to

avoid any parasitic phenomenon during the

measurement of Rd.

V_CL= V_BR+ Rd I_PP

Where Ipp is the peak current through the ESDA cell.

DYNAMIC RESISTANCE MEASUREMENT

The short duration of the ESD has led us to prefer

a more adapted test wave, as below defined, to the

classical 8/20µs and 10/1000µs surges.

Ipp

2µs

tp = 2.5µs

2.5µs duration measurement wave.

3/6

ESDAxxL

Fig. 1: Peak power dissipation versus initial junc-

tion temperature.

Fig. 2: Peak pulse power versus exponential

pulse duration (Tj initial = 25 °C).

Ppp[Tj initial]/Ppp[Tj initial=25°C]

Ppp(W)

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

3000

1000

100

Tj initial(°C)

tp(µs)

0.1

0.0

100

125

150

Fig. 3: Clamping voltage versus peak pulse cur-

rent (Tj initial = 25 °C).

Rectangular waveform tp = 2.5 µs.

Fig. 4: Capacitance versus reverse applied volt-

age (typical values).

Ipp(A)

C(pF)

50.0

200

ESDA5V3L

ESDA6V1L

ESDA14V2L

ESDA25L

F=1MHz

ESDA5V3L

Vosc=30mV

100

10.0

1.0

ESDA6V1L

ESDA14V2L

tp=2.5µs

ESDA25L

Vcl(V)

VR(V)

0.1

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

Fig. 5: Relative variation of leakage current versus

junction temperature (typical values).

Fig. 6: Peak forward voltage drop versus peak for-

ward current (typical values).

IR[Tj] / IR[Tj=25°C]

IFM(A)

200

5.00

ESDA5V3L

Tj=25°C

ESDA6V1L

ESDA14V2L

100

ESDA14V2L

ESDA6V1L

1.00

ESDA25L

0.10

ESDA5V3L

Tj(°C)

VFM(V)

0.01

100

125

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4/6

ESDAxxL

1. ESD protection by the ESDAxxL

the transient rises above the operating voltage of

the device, the TVS array becomes a low

impedance path diverting the transient current to

ground.

Electrostatic discharge (ESD) is a major cause of

failure in electronic systems.

Transient Voltage Suppressors (TVS) are an ideal

choice for ESD protection. They are capable of

clamping the incoming transient to a low enough

level such that damage to the protected

semiconductor is prevented.

The ESDAxxL array is the ideal board level

protection of ESD sensitive semiconductor

components.

The tiny SOT23 package allows design flexibility in

the design of high density boards where the space

saving is at a premium. This enables to shorten the

routing and contributes to hardening againt ESD.

Surface mount TVS arrays offer the best choice for

minimal lead inductance.

They serve as parallel protection elements,

connected between the signal line to ground. As

I/O

ESD

sensitive

device

GND

2 * ESDAXXL

2. Circuit Board Layout

Circuit board layout is a critical design step in the

suppression of ESD induced transients. The

following guidelines are recommended :

All conductive loops, including power and

ground loops should be minimized

The ESD transient return path to ground should

be kept as short as possible.

The ESDAxxL should be placed as close as pos-

sible to the input terminals or connectors.

Ground planes should be used whenever possi-

ble.

The path length between the ESD suppressor

and the protected line should be minimized

5/6

ESDAxxL

ORDER CODE

ESDA 6V1 L

ESD ARRAY

PACKAGE : SOT23 PLASTIC

V_BRmin

PACKAGE MECHANICAL DATA

SOT23 (Plastic)

DIMENSIONS

REF.

Millimeters

Min. Max.

Inches

Min.

Max.

0.055

0.004

0.02

0.89

1.4

0.1

0.035

0.3

0.51

0.18

3.04

1.05

2.1

0.012

0.003

0.108

0.033

0.067

0.047

0.083

0.085

2.75

0.85

1.7

0.007

0.12

0.041

0.083

0.063

0.108

1.2

1.6

2.1

2.75

0.6 typ.

0.024 typ.

0.35

0.65

0.014

0.026

FOOT PRINT (in millimeters)

MARKING

0.9

0.035

TYPE

MARKING

EL53

ESDA5V3L

ESDA6V1L

ESDA14V2L

ESDA25L

1.9

0.075

EL61

inch

1.45

0.037

EL15

EL25

0.9

0.035

Packaging: Standard packaging is tape and reel.

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of

use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by

implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied.

STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap-

proval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia

Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

6/6

ESDA25L [STMICROELECTRONICS]

相关型号：

ESDA25LY

ESDA25SC6

ESDA25SC6Y

ESDA25W

ESDA25W5

ESDA3302P3

ESDA4-LFC-LF-T73-1

ESDA5V3

ESDA5V3L

ESDA5V3LY

ESDA5V3SC5

ESDA5V3SC5_07