HCF4029BC1 [STMICROELECTRONICS]

BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER; 二进制或BCD十年预置UP / DOWN COUNTER
HCF4029BC1
型号: HCF4029BC1
厂家: ST    ST
描述:

BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER
二进制或BCD十年预置UP / DOWN COUNTER

CD
文件: 总13页 (文件大小:297K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
HCC4029B  
HCF4029B  
PRESETTABLE UP/DOWN COUNTER  
BINARY OR BCD DECADE  
.
.
MEDIUM SPEED OPERATION - 8MHz (typ.) @  
CL = 50pF AND VDD-VSS = 10V  
MULTI-PACKAGE PARALLEL CLOCKINGFOR  
SYNCHRONOUS HIGH SPEED OUTPUT RES-  
PONSE OR RIPPLE CLOCKING FOR SLOW  
CLOCK INPUT RISE AND FALL TIMES  
”PRESET ENABLEAND INDIVIDUAL ”JAM”  
INPUTS PROVIDED  
BINARY OR DECADE UP/DOWN COUNTING  
BCD OUTPUTS IN DECADE MODE  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
.
EY  
F
.
.
.
(Plastic Package)  
(Ceramic Package)  
.
.
M1  
C1  
.
(Micro Package)  
(Chip Carrier)  
.
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD No. 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
ORDER CODES :  
HCC4029BF  
HCF4029BEY  
HCF4029BM1  
HCF4029BC1  
DESCRIPTION  
The HCC4029B (extended temperature range) and  
HCF4029B (intermediate temperature range) are  
monolithic integrated circuit, available in 16-lead  
dual in-line plastic or ceramic package and plastic  
micro package. The HCC/HCF4029B consists of a  
four-stage binary or BCD-decade up/down counter  
with provisions for look-ahead carry in both counting  
modes. The inputs consist of a single CLOCK,  
CARRY-IN (CLOCK ENABLE), BINARY/DECADE,  
UP/DOWN, PRESET ENABLE, and four individual  
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT  
signal are provided as outputs. A high PRESET EN-  
ABLE signal allows information on the JAM INPUTS  
to preset the counter to any state asynchronously  
with the clock. A low on each JAM line, when the  
PRESET-ENABLE signal is high, resets the counter  
to its zero count. Thecounter isadvanced one count  
at the positive transition of the clock when the  
CARRY-IN and PRESET ENABLE signals, are low.  
Advancement is inhibited when the CARRY-IN or  
PRESET ENABLE signals are high. The CARRY-  
OUT signal is normally high and goes low when the  
PIN CONNECTIONS  
NC = No Internal Connection  
September 1988  
1/13  
HCC/HCF4029B  
counter reaches its maximum count in the UP mode  
or the minimum count in the DOWN mode provided  
the CARRY-IN signal is low. The CARRY-IN signal  
in the low state can thus be considered a CLOCK  
ENABLE. The CARRY-IN terminal must be con-  
nected to VSS whennot in use. Binary counting isac-  
complished when the BINARY/DECADE input is  
high ; the counter counts in the decade mode when  
the BINARY/DECADE input is low. The counter  
counts Up when to UP/DOWN INPUT is high, and  
Down when the UP/DOWN INPUT is low. Multiple  
packages can be connected in either a parallel-  
clocking or a ripple-clocking arrangement as shown  
in cascading counter packages. Parallel clocking  
provides synchronous control and hence faster re-  
sponse from all counting outputs. Ripple-clocking  
allows for longer clock input rise and fall times.  
FUNCTIONAL DIAGRAM  
ABSOLUTE MAXIMUM RATING  
Symbol  
Parameter  
Supply Voltage: HCC Types  
HCF Types  
Value  
Unit  
VDD  
*
-0.5 to +20  
-0.5 to +18  
V
V
Vi  
II  
Input Voltage  
-0.5 to VDD + 0.5  
V
DC Input Current (any one input)  
± 10  
mA  
mW  
Ptot  
Total Power Dissipation (per package)  
Dissipation per Output Transistor  
200  
for Top = Full Package Temperature Range  
100  
mW  
Top  
Operating Temperature: HCC Types  
HCF Types  
-55 to +125  
-40 to +85  
oC  
oC  
oC  
Tstg  
Storage Temperature  
-65 to +150  
Stressesabove those listedunder Absolute Maximum Ratings” may cause permanent damage to thedevice. This isa stress ratingonly and functional  
operation of the device at these or any other conditions above those indicated in theoperational sections of this specification is not implied. Exposure  
to absolute maximum rating conditions for external periods may affect device reliability.  
All voltage values are referred to VSS pin voltage.  
2/13  
HCC/HCF4029B  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Supply Voltage: HCC Types  
HCF Types  
Value  
Unit  
VDD  
3 to 18  
3 to 15  
V
V
VI  
Input Voltage  
0 to VDD  
V
Top  
Operating Temperature: HCC Types  
HCF Types  
-55 to +125  
-40 to +85  
oC  
oC  
LOGIC DIAGRAMS  
TRUTH TABLES  
CLOCK  
TE  
X
O
X
I
PE  
O
I
J
O
X
I
Q
O
Q
I
Q
I
Control Input  
Logic Level  
Action  
X
BIN/DEC  
(B/D)  
I
O
Binary Count  
Decade Count  
Q
UP/DOWN  
(U/D)  
I
O
Up Count  
Down Count  
X
O
I
O
X
X
Q
Q
Q NC  
Q NC  
Preset Enable  
(PE)  
I
O
Jam In  
No Jam  
X
I
X DON’T CARE  
No Counter  
I
Advance at Pos.  
Clock Transition  
Carry In (Cl)  
(Clock Enable)  
Advance Counter  
at Pos. Clock  
Transition  
O
3/13  
HCC/HCF4029B  
TIMING DIAGRAMS  
Binary Mode  
Decade Mode  
4/13  
HCC/HCF4029B  
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)  
Test Conditios  
Value  
o
Symbol  
Parameter  
Unit  
VI  
VO  
|IO| VDD  
TLOW  
*
25 C  
THIGH *  
(V)  
(V)  
(µA) (V)  
Min. Max. Min. Typ. Max. Min. Max.  
IL  
Quiescent  
Current  
0/5  
0/10  
0/15  
0/20  
0/5  
5
5
10  
20  
100  
20  
40  
80  
0.04  
0.04  
0.04  
5
150  
300  
600  
3000  
150  
300  
600  
HCC  
Types  
10  
15  
20  
5
10  
20  
µA  
0.08 100  
0.04  
0.04  
0.04  
20  
40  
80  
HCF  
Types  
0/10  
0/15  
0/5  
10  
15  
VOH  
VOL  
VIH  
VIL  
Output High  
Voltage  
< 1  
5
4.95  
4.95  
9.95  
4.95  
9.95  
V
V
V
V
0/10  
0/15  
5/0  
< 1 10 9.95  
< 1 15 14.95  
14.95  
14.95  
Output Low  
Voltage  
< 1  
5
0.05  
0.05  
0.05  
0.05  
0.05  
0.05  
0.05  
0.05  
0.05  
10/0  
15/0  
< 1 10  
< 1 15  
Input High  
Voltage  
0.5/4.5 < 1  
1/9 < 1 10  
1.5/13.5 < 1 15  
4.5/0.5 < 1  
9/1 < 1 10  
13.5/1.5 < 1 15  
5
3.5  
7
3.5  
7
3.5  
7
11  
11  
11  
Input Low  
Voltage  
5
1.5  
3
1.5  
3
1.5  
3
4
4
4
IOH  
Output  
Drive  
Current  
0/5  
0/5  
2.5  
4.6  
9.5  
13.5  
2.5  
4.6  
9.5  
13.5  
0.4  
0.5  
1.5  
0.4  
0.5  
1.5  
5
5
-2  
-1.6 -3.2  
-0.51 -1  
-1.3 -2.6  
-3.4 -6.8  
-1.36 -3.2  
-0.44 -1  
-1.1 -2.6  
-3.0 -6.8  
-1.15  
-0.36  
-0.9  
-2.4  
-1.1  
-0.36  
-0.9  
-2.4  
0.36  
0.9  
HCC  
Types  
-0.64  
0/10  
0/15  
0/5  
10 -1.6  
15 -4.2  
mA  
5
5
-1.53  
-0.52  
HCF  
Types  
0/5  
0/10  
0/15  
0/5  
10 -1.3  
15 -3.6  
IOL  
Output  
Sink  
Current  
5
0.64  
1.6  
0.51  
1.3  
1
HCC  
Types  
0/10  
0/15  
0/5  
10  
15  
5
2.6  
6.8  
1
4.2  
3.4  
2.4  
mA  
0.52  
1.3  
0.44  
1.1  
0.36  
0.9  
HCF  
Types  
0/10  
0/15  
10  
15  
2.6  
6.8  
3.6  
3.0  
2.4  
IIH, I  
Input  
Leakage  
Current  
HCC  
Types  
IL  
0/18  
0/15  
18  
15  
±0.1  
±0.3  
±10-5 ±0.1  
±1  
±1  
Any Input  
µA  
HCF  
Types  
±10-5 ±0.3  
CI  
Input Capacitance  
Any Input  
5
7.5  
pF  
* TLOW = -55 oC forHCC device: -40 oC for HCF device.  
* THIGH =+125 oC for HCC device: +85 oC for HCF device.  
The Noise Margin for both ”1” and ”0” level is: 1V min. with VDD = 5 V, 2 V min. with VDD =10 V, 2.5 V min. withVDD = 15 V  
5/13  
HCC/HCF4029B  
o
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 C, CL = 50 pF, RL = 200 K,  
typical temperature coefficent for all VDD values is 03 %/oC, all input rise and fall times= 20 ns)  
Test Conditions  
DD (V) Min.  
Value  
Typ.  
250  
120  
90  
280  
130  
95  
100  
50  
40  
90  
45  
Symbol  
Parameter  
Unit  
V
Max.  
500  
240  
180  
560  
260  
190  
200  
100  
80  
180  
90  
60  
15  
15  
15  
60  
20  
12  
340  
140  
100  
tPLH  
tPHL  
Propagation Delay Time (Q Outputs)  
5
ns  
10  
15  
5
10  
15  
5
10  
15  
5
10  
15  
5
10  
15  
5
10  
15  
5
tPLH  
tPHL  
Propagation Delay Time (Carry Output)  
Transition Time (Q Outputs, Carry Output)  
Minimum Clock Pulse Width  
ns  
ns  
ns  
µs  
tTLH  
tTHL  
tW  
30  
tr, tf **  
Clock Rise and Fall Time  
tsetup  
*
Minimum Setup Time (Carry Input)  
Minimum Setup Time (B/D or UD)  
Maximum Clock Input Frequency  
30  
10  
6
170  
70  
50  
4
ns  
tsetup  
10  
15  
5
10  
15  
fmax  
2
4
5.5  
MHz  
8
11  
PRESET ENABLE  
tPLH Propagation Delay Time (Q Outputs)  
tPHL  
5
235  
100  
80  
320  
145  
105  
65  
35  
25  
100  
55  
40  
470  
200  
160  
640  
290  
210  
130  
70  
10  
15  
5
10  
15  
5
10  
15  
5
10  
15  
ns  
tPLH  
tPHL  
Propagation Delay Time (Carry Output)  
Minimum Preset Enable (Pulse Width)  
Minimum Preset Enable (Removal Time)  
tW  
ns  
ns  
50  
trem  
*
200  
110  
80  
CARRY INPUT  
tPHL Propagation Delay Time (Carry Output)  
tPLH  
5
170  
70  
50  
25  
15  
12  
100  
35  
340  
140  
100  
50  
30  
25  
200  
70  
60  
ns  
ns  
10  
15  
5
10  
15  
5
tsetup *** Minimum Setup Time (Carry In)  
thold  
Minimum Hold Time (Carry In)  
10  
15  
30  
*
From Up/Down, Binary/Decade, Carry In or Preset Enable Control Inputs to Clock Edge  
** If more than one unit is cascated in the parallel clocked application tr should be made less than or equal to the sum of the fixed propagation  
delay at 15 pF and the transition time of the carry output driving stage for the estimated capacitance load.  
*** From Carry in to Clock Edge.  
6/13  
HCC/HCF4029B  
Typical Output Low (sink) Current Characteristics.  
Minimum Output Low (sink) Current Charac-  
Typical Output High (source) Current Charac-  
teristics.  
Minimum Output High (source) Current Charac-  
teristics.  
7/13  
HCC/HCF4029B  
APPLICATIONS  
Conversion of Clock up, Clock Down Input Sig-  
nals to Clock and Up/Down Inputs Signals.  
The HCC/HCF4029B CLOCK and UP/DOWN in-  
puts are used directly in most applications. In appli-  
cations where CLOCK UP and CLOCK DOWN  
inputs are provided, conversion to the  
HCC/HCF4029B CLOCK and UP/DOWN inputs  
can easily be realized by use of the circuit.  
HCC/HCF4029B changes count on positive transi-  
tions of CLOCK UP or CLOCK DOWN inputs. For  
the gate configuration shown below, when counting  
up the CLOCK DOWN input must be maintained  
high and conversely when counting down the  
CLOCK UP input must be maintained high.  
Cascading Counter Packages.  
*
CARRY-OUT lines at the 2nd, 3rd, et., stages may have a negative-going glitch pulse resulting from differential delays of different  
HCC/HCF4029B IC’s. These negative-going glitches do not affect proper HCC/HCF4029B operation. However, if the CARRY-OUTsignals  
are used to trigger other edge-sensitive logicdevices, suchas FF’s or counters, the CARRY-OUTsignals should be gated with the clocksignal  
using a 2-input NOR gate such as HCC/HCF4001B.  
Ripple Clocking Mode : The Up/Down control can be changed at any count. The only restriction on changing the Up/Down control is that the  
clock inputto the first counting stage must be high.  
8/13  
HCC/HCF4029B  
Plastic DIP16 (0.25) MECHANICAL DATA  
mm  
inch  
DIM.  
MIN.  
0.51  
0.77  
TYP.  
MAX.  
MIN.  
0.020  
0.030  
TYP.  
MAX.  
a1  
B
b
1.65  
0.065  
0.5  
0.020  
0.010  
b1  
D
E
e
0.25  
20  
0.787  
8.5  
2.54  
17.78  
0.335  
0.100  
0.700  
e3  
F
7.1  
5.1  
0.280  
0.201  
I
L
3.3  
0.130  
Z
1.27  
0.050  
P001C  
9/13  
HCC/HCF4029B  
Ceramic DIP16/1 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
TYP.  
MAX.  
20  
MIN.  
MAX.  
0.787  
0.276  
A
B
7
D
E
3.3  
0.130  
0.700  
0.38  
0.015  
e3  
F
17.78  
2.29  
0.4  
2.79  
0.55  
1.52  
0.31  
1.27  
10.3  
8.05  
5.08  
0.090  
0.016  
0.046  
0.009  
0.020  
0.110  
0.022  
0.060  
0.012  
0.050  
0.406  
0.317  
0.200  
G
H
L
1.17  
0.22  
0.51  
M
N
P
7.8  
0.307  
Q
P053D  
10/13  
HCC/HCF4029B  
SO16 (Narrow) MECHANICAL DATA  
mm  
inch  
DIM.  
MIN.  
TYP.  
MAX.  
1.75  
0.2  
MIN.  
TYP.  
MAX.  
0.068  
0.007  
0.064  
0.018  
0.010  
A
a1  
a2  
b
0.1  
0.004  
1.65  
0.46  
0.25  
0.35  
0.19  
0.013  
0.007  
b1  
C
0.5  
0.019  
c1  
D
45° (typ.)  
9.8  
5.8  
10  
0.385  
0.228  
0.393  
0.244  
E
6.2  
e
1.27  
8.89  
0.050  
0.350  
e3  
F
3.8  
4.6  
0.5  
4.0  
5.3  
0.149  
0.181  
0.019  
0.157  
0.208  
0.050  
0.024  
G
L
1.27  
0.62  
M
S
8° (max.)  
P013H  
11/13  
HCC/HCF4029B  
PLCC20 MECHANICAL DATA  
mm  
inch  
TYP.  
DIM.  
MIN.  
9.78  
8.89  
4.2  
TYP.  
MAX.  
10.03  
9.04  
MIN.  
0.385  
0.350  
0.165  
MAX.  
0.395  
0.356  
0.180  
A
B
D
4.57  
d1  
d2  
E
2.54  
0.56  
0.100  
0.022  
7.37  
8.38  
0.290  
0.330  
0.004  
e
1.27  
5.08  
0.38  
0.050  
0.200  
0.015  
e3  
F
G
0.101  
M
M1  
1.27  
1.14  
0.050  
0.045  
P027A  
12/13  
HCC/HCF4029B  
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the  
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No  
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned  
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.  
SGS-THOMSON Microelectronicsproductsare notauthorized foruse ascritical componentsin life support devices or systems without express  
written approval of SGS-THOMSON Microelectonics.  
1994 SGS-THOMSON Microelectronics - All Rights Reserved  
SGS-THOMSON Microelectronics GROUP OF COMPANIES  
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -  
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A  
13/13  

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