L5953 [STMICROELECTRONICS]
MULTIPLE SWITCHING VOLTAGE REGULATOR; 多开关电压调节
| 型号： | L5953 |
| 厂家： | 
ST |
| 描述： | MULTIPLE SWITCHING VOLTAGE REGULATOR |
| 文件： | 总24页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L5953
MULTIPLE SWITCHING VOLTAGE REGULATOR
PRODUCT PREVIEW
■ PWM: ADJUSTABLE 2.5/10V - 1A
SWITCHING VOLTAGE REGULATOR
■ EXTERNAL POWER MOS ABILITY FOR
OUTPUT CURRENT ENHANCEMENT
■ SYNCHRONIZATION FUNCTION
■ REG1- LINEAR LOW DROP 3.3/5V - 250mA
STBY VOLTAGE REGULATOR (LOW
CURRENT CONSUMPTION) with RESET
■ REG2- LINEAR VOLTAGE REGULATOR 1.5V
to 3.3V EXTERNALLY ADJUSTABLE - 300mA
MAXIMUM CURRENT
PowerSO36
ORDERING NUMBER: L5953
– HSD1 & HSD2 short to gnd, open load and
short to battery (Test mode)
– Thermal warning
■ HSD1 : 500mA HIGH SIDE DRIVER
■ HSD2 : 200mA HIGH SIDE DRIVER
■ SPI INTERFACE
PROTECTIONS
■ SPI DIAGNOSTICS HSD1, HSD2
■ DOUBLE SWITCHING FREQUENCY SPI
SELECTABLE
■ OVERVOLTAGE PROTECTION
■ INTERNAL CURRENT LIMITING
■ THERMAL SHUTDOWN
■ ESD
■ DOUBLE INPUT LVW
SPI FUNCTIONS
■ INPUT CONTROLS
DESCRIPTION
The L5953 is the integration of one switching regula-
tor, two linear voltage regulators, two low voltage
warnings and two high side drivers. It has a stand-by
operation mode (low current consumption) where
only the stand-by voltage regulator plus the low volt-
age warnings are active. The other regulators and
high side drivers are controlled by the SPI interface.
– Turn-on/off PWM
– Turn-on/off REG2
– Turn-on/off HSD1
– Turn-on/off HSD2
– Switching frequency selection f1- f2
■ OUTPUT FUNCTIONS:
BLOCK DIAGRAM
S1
W1
S2
W2
VDD-LIN
VDD-SW
STCAP
CT
RES
FGND
REC1
VSTBY
ADJ
ST-BY LINEAR VOLTAGE
REGULATOR
VOLTAGE WARNING
HSD1
3.3-5V/250mA
HSD1
HSD2
PWM
STRAP
STEP DOWN
REGULATOR
2.5-10V/1A
HSD2
DRAINOUT
VSW
GATEIN
GATEOUT
FB
COMP
REC2
VSPI
IRQ
LINEAR VOLTAGE
REGULATOR
1.5-3.3V/300mA
SPI INTERFACE
OSCILLATOR &
SYNC
SWGND
GND
D01AU1330A
Q
D
S
C
VLR
FBLR
VIN
SYNC
DGND
September 2003
1/24
This is preliminary information on a new product now in development. Details are subject to change without notice.
L5953
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
-0.6 to 30
50
Unit
V
V
DD
DC Operating Supply Voltage
Transient Supply Overvoltage (250ms)
Supply Voltage for SPI I/O
V
V
SPI
-0.6 to 6
V
I
Voltage Regulator Output Current
Internally limited
0 to 6
O
V
V
Input Voltage (C,D,Q,S,SYNC)
inlog
RESR
Output Capacitor Series Eq. Resistance (Linear reg.)(Allowed
range)
From 0.2 to 10
Ω
T
Operating Temperature Range
Storage Temperature Ranges
Operative Junction Temperature
-40 to 85
-55 to 150
-40 to 150
°C
°C
°C
op
T
stg
T
j
THERMAL DATA
Symbol
Parameter
Value
Unit
R
Thermal Resistance Junction to Case
1.7
°C/W
thj-case
PIN CONNECTION
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
FGND
S2
ADJ
2
VSTBY
VSPI
3
S1
4
W2
STCAP
FB
5
W1
6
RES
CT
COMP
FBLR
7
8
D
VIN
9
C
VLR
10
11
12
13
14
15
16
17
18
Q
SYNC
STRAP
GATEOUT
GATEIN
VSW
S
DGND
IRQ
HSD2
VDD-LIN
N.C.
HSD1
SWGND
GND
N.C.
DRAINOUT
VDD-SW
D02AU1345A
2/24
L5953
PIN FUNCTION
Pin Number
Pin Name
Function
1
FGND
S2
Analog Ground
Input Voltage for LVW2
Input Voltage for LVW1
LVW2 Output
2
3
S1
4
W2
W1
RES
CT
5
LVW1 Output
6
Reset
7
Timing capacitor
SPI Serial Input
SPI Clock
8
D
9
C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Q
SPI Serial Output
SPI Chip Select
SPI Ground
S
DGND
IRQ
HSD2
Interrupt
HSD2 Output
VDD-LIN
N.C.
Battery
Not Connected
HSD1 Output
HSD1
SWGND
VDD-SW
DRAINOUT
N.C.
Switching Ground
PWM Battery
Drain of the exrternal MOS
Not Connected
Ground
GND
VSW
Source of the external MOS
Gate of the internal MOS
GATEIN
GATEOUT
STRAP
SYNC
VLR
Switching Output for power mos gate
Bootstrap
Synchronization
REG2 Linear Voltage Regulator Output
REG2 Linear Voltage Regulator Input
REG2 Linear Voltage Regulator Feedback
PWM Compensation
VIN
FBLR
COMP
FB
PWM Feedback
STCAP
VSPI
ST-CAP
Supply Voltage for SPI I/O
REG1 Stand-by Linear Voltage Regulator Output
3.3V/5V REG1 Voltage Select
VSTBY
ADJ
3/24
L5953
ELECTRICAL CHARACTERISTCS
( T
= 25°C, V = 14.4V)
DD
amb
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
I
Quiescent current with regulators W1, W2, RES, IRQ, not active;
100
µA
Q,STBY
and High-side drivers off
REG2, HSD1, HSD2, PWM off;
S, C, D fixed at high/low logic
level
T
Thermal Shutdown Junction
Temperature
150
°C
sd
SMPS.PWM
T
= 25°C, V = 14.4V, V = 5V; unless otherwise specified.)
DD o
amb
Vo,min
Minimum Output Voltage
Maximum Output Voltage
I = 200mA
2.4
9.6
2.5
10
2.6
V
V
o
V
o,max
I = 200mA
o
10.4
Vref,PWM Voltage Reference
1.275
V
V
Input Voltage Range
Line Regulation
V = 5V; I = 0.5A
6
18
100
50
0.5
1
V
i
o
o
∆V
I = 0.5A
o
mV
mV
V
o
∆V
Load Regulation
V = 5V; I = 0.2A to 0.5A
o o
o
V
Dropout Voltage between Pin 19 I = 0.5A, V = 5V
o o
and Pin 23
d
I = 1A, V = 5V
V
o
o
I
Current Limit
Efficiency
1.5
A
Lim
η
f = 260kHz; I = 0.5A
90
86
%
%
o
f = 400kHz; I = 0.5A
o
SVR
Supply Voltage Ripple Rejection
∆V = 1Vrms;
50
dB
i
f
= 300Hz; I = 0.4A
ripple
o
OSCILLATOR
f
Swiching frequency
Swiching frequency
249
384
260
400
Tbd
271
416
kHz
kHz
%
1
2
f
Voltage Stability of Switching
Frequency
V
= 8 to 18V
DD
∆f
--------
∆Vi
Temperature Stability of Switching T = -40°C to 85°C
Frequency
Tbd
%
j
∆ f
∆ T j
--------
SYNC
V
Low Input Voltage
High Input Voltage
Low Output Voltage
0.8
0.4
V
V
V
V
IL
V
IH
2
4
V
OL
V
OH
High Output Voltage
I
=1.5mA
SOURCE
4/24
L5953
ELECTRICAL CHARACTERISTCS (continued)
( T = 25°C, V = 14.4V)
amb
Symbol
DD
Parameter
Slave Sink Current
Output Pulse Width
REG1 - 3.3V/5V STBY LINEAR VOLTAGE REGULATOR
Test Condition
Min.
Typ.
100
300
Max.
Unit
µA
I
SLAVE
T
W
ns
V
Output Voltage
no load; ADJ pin = open
no load; ADJ pin = VSTBY pin
4.9
3.20
5
3.3
5.1
3.4
V
V
STBY
∆V
Line Regulation
Load Regulation
no load; 7 < Vdd < 26V
5
50
80
mV
mV
V
line
∆V
5mA < I < 250mA
12
load
o
V
V
- V
I = 100mA, V = 5V
0.36
0.47
0.5
0.65
dropout
STCAP
STBY
o
o
I = 100mA, V = 3.3V
o
o
I
Current Limit
Out short to GND
300
mA
dB
lim
SVR
Supply Voltage Rejection
∆V = 1Vrms: f = 300Hz
55
DD
I = 250mA
o
REG2 - LINEAR VOLTAGE REGULATOR 1.5V to 3.3V
V
Linear Regulator Output Voltage
no load; 4.75 ≤ V ≤ 16V;
1+ (R5/R6) = 2.588
3.2
1.45
3.135
4.75
3.3
1.5
3.4
1.55
16
V
LR
IN
no load; 3.135 ≤ V ≤ 16V;
IN
1+ (R5/R6) = 1.176
V
Input Voltage
I
= 150mA
O
V
V
IN
1.5V ≤ V ≤ 2V
LR
I
= 300mA
16
O
1.5V ≤ V ≤ 3.3V
LR
∆V
Load Regulation
Line Regulation
5mA ≤ I ≤ 300mA
12
1
mV
mV
load
O
4.75V
≤
V
IN
≤
≤
16V; 1.5V
16V; 1.5V
≤
≤
V
V
≤
≤
3.3V
3.3V
LR
∆V
no load;
4.75V
line
≤
V
IN
LR
V
Voltage Reference
Current Limit
1.275
V
ref,REG2
I
Out Short to ground
= 5Vdc, 0.5Vacpp, 300Hz
400
mA
dB
Lim
SVR
Supply Voltage Rejection
V
55
55
IN
I
= 300mA; 1.5V
≤
V
LR
≤
3.3V
O
V
= 3.3Vdc, 0.5Vacpp, 300Hz
dB
IN
I
= 150mA; 1.5V
≤
V
LR
≤ 2V
O
O
HSD1
V
Saturation Voltage
Current Limit
I
= 0.5A
250
100
mV
mA
mH
sat, peak
I
lim
600
L
load
Load Inductance
5/24
L5953
ELECTRICAL CHARACTERISTCS (continued)
( T
= 25°C, V = 14.4V)
DD
amb
Symbol
HSD2
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
Saturation Voltage
I
= 0.2A
O
250
mV
mA
mH
sat, peak
I
lim
Current Limit
300
L
load
Load Inductance
100
VOLTAGE WARNING
V
Sense Low Threshold
1.245
35
1.275
45
1.305
60
V
mV
V
st
V
V
Sense Threshold Hysteresis
Sense Output Low Voltage
Sense Output Leakage
Sense Input Current
sth
I = 1mA
0.4
10
SL
o
I
SH
V
= 5V; V
≥
1.5V
µA
µA
W
SI
I
V =5V
SI
1
SI
RESET
V
Reset Threshold Voltage
Reset Threhold Hysteresis
0.95 x
V
V
RT
V
STBY
V
RTH
0.02 x
V
STBY
V
Reset Output Voltage
I = 1mA
0.4
10
V
RL
o
I
Reset Output Leakage
Delay Comparator Threshold
V
= V
µA
RH
RT
STBY
V
CTth
0.5 x
V
STBY
V
I
Delay Comparator Threshold
Hysteresys
180
mV
µA
Ω
CThy
Timing Capacitor Output Source
Current
7.5
CT1
R
Timing Capacitor Output Pull-
Down equivalent Resistor
150
CT2
DIAGNOSTIC PARAMETERS
Symbol Parameter
Test Condition
Min.
Typ.
Max.
Unit
HSD1W1 High Side Driver 1 Overcurrent
Warning activation
0.95
A
HSD1W2 High Side Driver 1 Open Load
Warning activation
HSD1 output voltage in test mode
HSD1 in test mode
3
V
V
A
HSD1W2 High Side Driver 1 V Short
1.5
0.7
DD
TEST
Measure V
-V
Warning activation in test mode
VDD-LIN HSD1
HSD2W1 High Side Driver 2 Overcurrent
Warning activation
6/24
L5953
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
HSD2W2 High Side Driver 2 Open Load
Warning activation
HSD2 output voltage in test mode
3
V
HSD2W3 High Side Driver 2 V Short
HSD2 in test mode
1.5
V
DD
Measure V
-V
Warning activation in test mode
VDD-LIN HSD1
THW
IRQ - Interrupt Request Pin
IRQ-L IRQ Low voltage
Thermal warning activation
145
°C
I = 1mA
0.4
1
V
o
IRQ-H IRQ Leakage
V
= 5V
µA
irq
SPI INTERFACE
Symbol
Recommended DC Operating Voltage
Supply Voltage for SPI I/O
Input Parameters (Tamb = 25°C, f = 1MHz)
Alt
Parameter
Test Conditions
Min.
Max.
Unit
V
SPI
3
5.5
V
C
Input Capacitance (D)
8
6
pF
pF
ns
IN
IN
C
Input Capacitance (others pins)
Input Signal Pulse Width
t
10
LPF
DC Characteristics (T
= -40 to 85°C, V
= 3V to 5.5V)
amb
SPI
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
2
µA
µA
V
LI
I
LO
±2
V
-0.3
0.3V
SPI
IL
IH
V
Input High Voltage
0.7
V
V
SPI+1
V
SPI
V
Output Low Voltage
Output High Voltage
I
I
= 2mA
0.2
V
SPI
V
OL
OL
V
OH
= -2mA
0.8
V
V
OH
SPI
AC Characteristics (Tamb = -40 to 85°C, V
= 3V to 5.5V
SPI
t
t
t
t
S Setup Time
50
50
ns
ns
ns
ns
µs
µs
ns
ns
µs
SCLH
CLSH
SU
S Hold Time
SH
t
t
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
Data In Setup Time
Data In Hold Time
Data In Rise Time
200
300
CH
WH
t
t
WL
CL
t
t
t
1
CLCH
CHCL
DVCH
CHDX
RC
t
1
FC
t
t
50
50
DSU
t
t
DH
t
t
RI
1
DLDH
7/24
L5953
Symbol
Alt
Parameter
Data in Fall Time
Test Conditions
Min.
Max.
Unit
t
t
FI
1
µs
DHDL
t
t
S Deselect Time
4.5V < V < 5.5V
SPI
200
250
ns
ns
SHSL
CS
3V < V
< 4.5V
SPI
t
t
Output Disable Time
Clock Low to Output Valid
Output Hold Time
150
250
ns
ns
ns
ns
ns
SHQZ
DIS
t
t
t
V
QVCL
CLQX
QLQH
QHQL
t
0
HO
t
t
t
t
Output Rise Time
100
100
RO
FO
Output Fall Time
Figure 1. AC Testing Input Output WaveformsI
0.8VSPY
0.7VSPY
0.3VSPY
0.2VSPY
D03AU1479
Figure 2. SPI Clocking Scheme
S
(MODE 0: CPOL=0,CPHA=0)
C
(MODE 3: CPOL=1,CPHA=1)
C
D
Q
MSB
6
5
4
3
2
1
0
8/24
L5953
Figure 3. Output Timing
S
C
tCH
tCLQX
tQVCL
tCL
tSHQZ
MSB OUT
MSB-1 OUT
LSB OUT
Q
tQLQH
tQHQL
ADDR.LSB IN
D
(CPOL=0, CPHA=0)
AI01070B
Figure 4. Serial Input Timing
tSHSL
S
tSLCH
tCLSH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
tDLDH
tDHDL
HIGH IMPEDANCE
Q
AI01071
(CPOL=0, CPHA=0)
FUNCTIONAL DESCRIPTION
REG1 Stand-by Regulator (Figure 5)
The stand-by regulator output voltage can be 5V or 3.3V. It is externally selectable by means of the ADJ pin:
- leaving the ADJ pin open, the output voltage is 5V;
- connecting the ADJ pin to the Vstby pin the output voltage becomes 3.3V.
This regulator is supplied by STCAP pin and provide the reset information.
It has a current protection which limits the maximum allowable output current.
Reset (Figure 6)
The RES pin is an open collector that is activated (that is forced to zero) when the stand-by regulator is not in
regulation (including thermal shutdown and faults). The indication that REG1 is in regulation is delayed by a time
9/24
L5953
set up by the external capacitor CT.
When the RES is switched on, HSD1, HSD2, REG2, PWM are turned off and until the RES is forced to zero
only the REG1 and low Voltage Warnings are active.
Low Voltage Warning(Figure 7)
This circuit is able to sense two different voltages through external resistors to increase the overall flexibility.
If S1 pin voltage is higher than Vst, the output mos M1 is off: W1 is floating and can be pulled up by an external
resistor. If S1 pin voltage goes down and becomes lower than Vst, the mos M1 is turned on and forces W1 to
zero. The same thing happens for S2 - W2.
The outputs W1 and W2 can be connected together to get a single output.
REG2 Linear Voltage Regulator (Figure 5)
REG2 is a linear voltage regulator with a dedicated supply pin VIN. The output voltage (between 1.5V and 3.3V)
is fixed by an external divider. It can be turned on/off by SPI. It has a current protection which limits the maximum
allowable output current.
High Side Drivers (Figure 8)
Two high-side driver with charge pump controlled by SPI are available inside L5953. They are protected against
short to ground: the short circuit potection limits the maximum output current.
A diagnostic procedure is available to detect open load, short to battery and overcurrent.
Open load and short to battery can be reveal only in test mode while overcurrent is active only during normal
operationof the device. (see OPERATION -page 13
PWM Step Down Voltage Regulator (Figure 9)
The switching regulator inside the L5953 is a voltage control mode (also known as "direct duty cycle") Buck reg-
ulator: the error signal coming from the error amplifier is compared with a sawtooth to set on and off times of the
power switch.
The feedforward control is introduced to get a quickly response to input voltage changes: the sawtooh has a
fixed frequency and an amplitude variable with the battery voltage.
Continuous mode operation is recommended in order to reduce the stress of the output capacitor and of the
free-wheeling diode.
Error amplifier and compensation network
The error amplifier (EA) is a voltage amplifier whose non-inverting input is fixed to the reference voltage (1.275V
bandgap voltage) and whose inverting input and output are externally available for feedback and frequency
compensation.
10/24
L5953
Figure 5. Linear regulators - Internal pin connections
STCAP
VREF
POWER MOS
VSTBY
1.275V
VSTBY
CONTROLLER
VSTBY
ADJ
FGND
FBLR
VLR
LINEAR REGULATOR
CONTROLLER
POWER MOS
VREF
1.275V
VIN
D03AU1493
Figure 6. Reset Internal pin Connection
RES
CT
Vref
2.5V/1.65V
7.5µA
FROM VST-BY
Vref 1.275V
D03AU1480
Figure 7. Low Voltage Warning Block Diagram.
V1
W1
Vref =1.275V
S1
+
-
M1
V2
W2
Vref =1.275V
S2
+
-
M2
D03AU1478
11/24
L5953
Figure 8. HSD - Internal pin connections
HSD1
POWER
MOS
HSD1
HSD1
CONTROLLER
VDD-LIN
HSD2
POWER
MOS
HSD2
HSD2
CONTROLLER
D01AU1333
Figure 9. PWM - Internal pin connections
STRAP
COMP
FB
ERROR AMPLIFIER
VDD-SW
RS2
DRAINOUT
CURRENT
SENSING
RS1
VREF
1.275V
VSW
PWM
CONTROLLER
POWER
MOS
FROM THE
OSCILLATOR
GATEIN
GATEOUT
D03AU1482
Figure 10. SPI & IRQ Internal pin connections
IRQ
S
Q
SPI
INTERFACE
D
C
DGND
D03AU1481
12/24
L5953
SPI INTERFACE
Signals Description (Figure 10)
The SPI interface available inside L5953 is able to work both in Mode 0 and Mode 3.
Serial Output (Q). The output pin is used to transfer data serially out of the L5953. Data is shifted out on the
falling edge of the serial clock.
Serial Input (D). The input pin is used to transfer data serially into the device. It receives instructions, address-
es, and data to be written. Input is latched on the rising edge of the serial clock.
Serial Clock (C). The serial clock provides the timing of the serial interface. Instructions, addresses, or data
present at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes after
the falling edge of the clock input.
Chip Select (S). This input is used to select the L5953. The chip is selected by a high to low transition on the
S pin. At any time, the chip is deselected by a low to high transition on the S pin. As soon as the chip is dese-
lected, the Q pin is at high impedance state. The pin allows multiple L5953 to share the same SPI bus. After
power up, the chip is at the deselect state.
SPI Input/Output are supplied by an external supply voltage VSPI while the core is supplied by the stand-by
regulator VSTBY. The SPI is resetted by an internal signal whose buffered version is RES .
OPERATIONS
All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on
the first rising edge of clock (C) after the chip select (S) goes low. Prior to any operation, a one-byte instruction
code must be entered in the chip. This code is entered in the chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been
previously selected (S = low). Table 1 shows the instruction set and format for device operation. An invalid in-
struction (one not contained in table 1) leaves the chip as previously selected.
Write Enable (WREN and Write Disable (WRDI)
The L5953 contains a write enable latch. This latch must be set prior to every WRITE operation. The WREN
instruction will set the latch and the WRDI istruction will reset the latch. The latch is reset under all the following
conditions:
– Power on
– WRDI instruction executed
As soon as the WREN or WRDI instruction is received by the L5953, the circuit executes the instruction and
enters a wait mode until it is deselected.
Table 1. Instruction Set.
Instruction
WREN
WRDI
Description
Instruction Format
00000110
Set Write Enable Latch
Reset Write Enable Latch
Write Status Register
Read Diagnostic Register
Read Status Register
00000100
WSTA
00000010
RDIA
00000101
RSTA
00000011
13/24
L5953
Table 2. Status Register.
s15
s14
s13
s12
s11
s10
s9
s8
s7
s6
s5
s4
s3
s2
s1
s0
REG2 HSD1 HSD2 TBD TBD PWM PWM TBD TBD TBD TBD TBD TBD TBD Test START
Freq.
Mode DIAG
Table 3. Status Register Description
0
1
REG2 Linear Voltage
s15
Regulator off
Regulator on
Regulator 1.5 to 3.3V
s14
s13
s12
s11
s10
s9
High Side Driver 1
HSD1 off
HSD2 off
HSD1 on
HSD2 on
High Side Driver 2
TBD
TBD
PWM switching frequency
260kHz
400kHz
PWM Voltage Regulator
PWM1 off
PWM1 on
s8
TBD
s7
TBD
s6
TBD
s5
TBD
s4
TBD
s3
TBD
s2
TBD
Test Mode
Test Mode off
Diagnostic off
Test Mode on
NOTE: in this case the bits s15 - s2 are internally
set to 0 (regulators and high side drivers are in off
condition)
s1
s0
Diagnostic
Starts the diagnostic procedure:
- in Test Mode if s1=1;
- during normal operation if s1=0
If s1=0 and s0=1, must be s14 = 1 (HSD1 ON)
and s13=1 (HSD2 ON)
Table 4. Diagnostic Register.
d7
d6
d5
d4
d3
d2
d1
d0
Test mode HSD1W1
HSD1W2
HSD1W3
HSD2W1
HSD2W2
HSD2W3
THW
14/24
L5953
Table 5. Diagnostic Register Description.
0
1
d7
d6
d5
d4
d3
d2
d1
d0
Test mode
HSD1W1
The Diagnostic Register is
referred to a test performed referred to a test performed
during the normal working
of the L5953
The Diagnostic Register is
in Test mode
If d7=0: HSD1 in normal
condition;
If d7=1: bit value
meaningless
If d7=0: HSD1 is in
overcurrent
If d7=1: bit value
meaningless
HSD1W2
If d7=0: bit value
meaningless;
If d7=1: HSD1 in normal
condition
If d7=0: bit value
meaningless
If d7=1: an open load is
present on HSD1
HSD1W3
If d7=0: bit value
meaningless;
If d7=1: HSD1 in normal
If d7=0: bit value
meaningless
If d7=1: HSD1 is shorted to
the supply voltage VDD
condition
HSD2W1
If d7=0: HSD1 in normal
condition;
If d7=1: bit value
If d7=0: HSD2 is in
overcurrent;
If d7=1: bit value
meaningless
meaningless
HSD2W2
If d7=0: bit value
meaningless
If d7=1: HSD2 in normal
condition
If d7=0: bit value
meaningless
If d7=1: an open load is
present on HSD2
HSD1W3
If d7=0: bit value
meaningless
If d7=1: HSD2 in normal
condition;
If d7=0: bit value
meaningless
If d7=1: HSD1 is shorted to
the supply voltage VDD
Thermal Warning
Normal condition
Overtemperature protection
activated(Tj>150°C)
SUMMARY OF THE MAIN OPERATIONS
Operation A
■ Test Mode Diagnostic Procedure Start
■ 1) WREN instruction (Fig.11)
■ 2) WSTA instruction (Fig.12)
Operation B
■ Read the Diagnostic Register
Case1: after a Test Mode Diagnostic Procedure Start
1) RDIA instruction (Fig.13)
2) Diagnostic Register output (Fig.13)
■ NOTE: an operation B must follow an operation A. The delay between the end of the operations A to
the start of the operations B must be longer than 100µS
Operation C
■ Write the Status Register
15/24
L5953
1) WREN instruction (Fig.11)
2) WSTA instruction (Fig.16)
Operation D
■ Read the Status Register
1) RSTA instruction (Fig.17)
2) Status Register output (Fig.17)
Operation E
■ Diagnostic Procedure Start
1) WREN instruction (Fig.11)
2) WSTA instruction (Fig.14)
Operation F
■ Read the Diagnostic Register
Case 2: after a Diagnostic Procedure Start
1) RDIA instruction (Fig.15)
2) Diagnostic Register output (Fig.15)
An operation F must follow an operation E if the pin IRQ is not activated.
The delay between the Operation E and an Operation F must be longer than 100µs.
To be recognized, the fault must be present without interruptions during all the delay above mentionned .
After an Operation F, the bit s0 of the Status Register is resettled (0)
Operation G
■ Write operation disabled
1) WRDI instruction (Table 1)
Operation H
■ Read the Diagnostic Register case 3: after an IRQ pin activation
1) RDIA instruction (Fig. 15)
2) Diagnostic Register Output (Fig. 15)
The delay between the IRQ activation and an Operation F must be longer than 100µs
Figure 11. Write Enable Latch Sequence
S
00
01
02
03
04
05
06
07
C
CPOL=0
CPHA=0
D
Q
HIGH IMPEDANCE
D03AU1483
16/24
L5953
Figure 12. Test Mode Diagnostic Procedure Start (after a Write Enable Latch Sequence, Fig.11)
CPOL=0, CPHA=0
S
C
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
s6
18
s5
19
s4
20
s3
21
s2
22
s1
23
s0
INSTRUCTION
STATUS REGISTER
s9 s8 s7
s15 s14 s13 s12 s11 s10
D
Q
HIGH IMPEDANCE
D03AU1484
Figure 13. Read the Diagnostic registerCase1: after a Test Mode diagnostic procedure start (Fig.
12)
CPOL=0, CPHA=0
S
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
C
D
Q
INSTRUCTION
DIAGNOSTIC REGISTER OUT
d6 d5 d4 d3 d2 d1
HIGH IMPEDANCE
d7
d0
D03AU1485
Figure 14. Diagnostic Procedure Start (after a Write Enable Latch Sequence, operation A)
CPOL=0, CPHA=0
S
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
s6
18
s5
19
s4
20
s3
21
s2
22
s1
23
s0
C
INSTRUCTION
STATUS REGISTER
s9 s8 s7
s15 s14 s13 s12 s11 s10
D
Q
HIGH IMPEDANCE
D03AU1486
Figure 15. Read the Diagnostic RegisterCase2: during the normal working of the L5953 (after a
Diagnostic Procedure Start, Fig.14)
CPOL=0, CPHA=0
S
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
C
D
Q
INSTRUCTION
DIAGNOSTIC REGISTER OUT
d6 d5 d4 d3 d2 d1
HIGH IMPEDANCE
d7
d0
D03AU1487
17/24
L5953
Figure 16. Write the Status Register (after a Write Enable Latch Sequence, operation A)
CPOL=0, CPHA=0
S
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
s6
18
s5
19
s4
20
s3
21
s2
22
s1
23
s0
C
INSTRUCTION
STATUS REGISTER
s9 s8 s7
s15 s14 s13 s12 s11 s10
D
Q
HIGH IMPEDANCE
D03AU1488
Figure 17. Read the Status Register
CPOL=0, CPHA=0
S
C
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
INSTRUCTION
D
Q
STATUS REGISTER OUT
s9 s8 s7 s6
HIGH IMPEDANCE
s15 s14 s13 s12 s11 s10
s5
s4
s3
s2
s1
s0
D03AU1489
IRQ - Interrupt Request Pin
■ It is an open drain pin activated (low) every time a variation occurs in the Diagnostic Register.
■ Purpose: to alert the µP that one or more warning bit of the Diagnostic Register has changed from 0 to
1 or from 1 to 0.
■ An activation of this pin puts the bit s0 of the Status Register to 1 (START DIAGNOSTIC) like an
Operation E (Diagnostic Procedure Start). Then an Operation F has to be executed without an
Operation E before.
■ After an Operation F, the IRQ pin is disactivated, and goes to 1 if connected to a pull-up resistor.
L5953 - Application Note
18/24
L5953
Figure 18. Block and Application Diagram
C2
C5
C3
C11
CT
D1
C1
VDD
S1
W1
S2
W2
RES
VDD-LIN
VDD-SW
STCAP
FGND
VSTBY
REG1
ST-BY LINEAR VOLTAGE
REGULATOR
3.3-5V/250mA
VOLTAGE WARNING
HSD1
C4
ADJ
HSD1
HSD2
STRAP
PWM
STEP DOWN
REGULATOR
2.5-10V/1A
C6
HSD2
DRAINOUT
VSW
L1
Vo
GATEIN
D2
R1
R2
C7
GATEOUT
FB
REG2
COMP
SWGND
GND
R4
R3
VSPI
IRQ
C9
LINEAR VOLTAGE
REGULATOR
1.5-3.3V/300mA
SPI INTERFACE
OSCILLATOR &
SYNC
C8
D01AU1331B
VLR
FBLR
R5
VIN
SYNC
DGND
Q
D
S
C
R6
C10
Figure 19. Block Diagram And Application With External Power MOS
C2
C5
C3
D1
C1
VDD
W2
S1
W1
S2
VDD-LIN
VDD-SW
STCAP CT
RES
FGND
VSTBY
REG1
ST-BY LINEAR VOLTAGE
REGULATOR
VOLTAGE WARNING
HSD1
C4
C6
3.3-5V/250mA
ADJ
HSD1
HSD2
STRAP
PWM
STEP DOWN
REGULATOR
2.5-10V/1A
HSD2
DRAINOUT
VSW
L1
Vo
D2
R1
C7
GATEIN
GATEOUT
FB
M1
R2
REG2
LINEAR VOLTAGE
REGULATOR
COMP
VSPI
IRQ
SPI INTERFACE
R4
R3
C9
1.5-3.3V/300mA
SWGND
GND
OSCILLATOR &
SYNC
C8
D01AU1332B
VLR
FBLR
R5
VIN
SYNC
DGND
Q
D
S
C
R6
C10
19/24
L5953
PART LIST on Evaluation Board
C1 = 470
µ
F
C2 = 220 nF
C8 = 56nF
C3 = 470
µ
F
C4 = 10
µ
F
C5 = 1
µ
F
C6 = 100 nF
C7 = 470
µ
F
C9 = 2.7 nF
C10 = 10 µF
C11 = 4.7 nF
ESR=65 m
Ω
R1 = 2.2 k
Ω
R2 = 2 x 1.5 k
in parallel
Ω
R3 = 10 k
Ω
R4 = 220 k
Ω
R5 = 3.3 k
Ω
R6 = 1 kΩ
L1 = 180
µ
H
D1 = 1N4007 or
MBR160
D2 = MBR360
REG1 OUTPUT VOLTAGE
V
STBY
V
STBY
= 5V if pin ADJ left floating
= 3.3V if pin ADJ is conneted to the pin V
STBY
Timing Capacitor
The value for this capacitor has to be chosen according the wanted power-on delay T :
d
ICT1 Td
C11 = -------------------------------------------------------------
(0.5 VSTBY) + VCTLRy
where I
is the source current used to charge the timing capacitor and V
is the REG1 output voltage.
STBY
CT1
Feedback resistors for REG2
VLR
------------------------
Vref, REG2
R5 = R6
– 1
where VLR is the required output voltage for REG2.
External components for PWM regulator
Bootstrap capacitor
The suggested value for the bootstrap capacitor is C6 = 100nF
Here following you find the criteria for the selection of the inductor L1, the free-wheeling diode D2, the output
filter capacitor C7, the feedback resistor R1, R2 and the compensation network R3, C8, R4, C9 to have a Buck
regulator working in Continuos mode. Continuous mode operation is recommended in order to reduce the stress
of the output capacitor and of the free-wheeling diode.
Inductor Selection
The minimum value of the inductor L7 has to be so that the maximum inductor current ripple
∆I
is 20% to
L,max
30% of the maximum load current load I .The maximum ripple is present when the switching frequency is
o,max
minimum ( f
) and the input voltage is maximum ( V
) so the minimum value for the inductor L
is :
min
sw,min
in,max
V O
VO
1
--------------------
---------------- ------------------
Lmin
=
1 –
∆IL, max
V i, max f sw, min
Output Capacitor Selection
The criteria for the selection of the capacitor C7 is based on the output voltage ripple requirements. The ripple
on the output voltage is due to a capacitive contribute, often negligible, equal to
20/24
L5953
∆IL, max
∆Vc = --------------------------------------
8 C7 fsw, min
and a resistive contribute given by the ESR of the capacitor and which is equal to
∆ V ESR = ESR ∆IL, max
∆VC fixes the value for C7 while ∆VESR limits the ESR of the capacitor.Usually the capacitor is chosen so that
the total ripple on the output regulated voltage Vo is equal to 1% of the value of Vo. If V
is the maximum
ripple
allowed voltage ripple on Vo then it should result:
2
Vripple
≥
∆Vc2 + ∆VESR
More often the minimum value of C7 is imposed by other considerations such as to get a good dynamic behav-
iour of the output voltage in case of large load variations.
Free-wheeling diode
The diode must withstand an average current Id equal to Id = I ( 1- D
)
lim
min
where I is the current of intervention of the short circuit protection and D
is the minimum duty cycle. As D
min
lim
min
is vey low, the current Id can be assumed equal to I
.
lim
Compensation Network
In continuous mode, the voltage controlled buck converter showes two poles due to the output LC filter and one
zero due to the ESR of the output capacitor. The suggested compensation network introduces two zeros and
two poles:
– the zeros compensate the double poles of the LC filter
– one pole compensates the zero due to ESR of the output capacitor
– the second pole is nominally located in the origin which means an infinite gain at frequency null. In
the reality the DC value of the closed loop gain can not be greater than the DC value of the EA open
loop gain and the pole is located at very low frequency.
The values for the components of the compensation network can be fixed when the inductor L1 and the output
capacitor C7 are chosen.
The necessary steps are following:
1.fix the cross-over frequency f of the overall loop gain.
C
Usually
fc = 0.1 fsw,min
is the minimum switching frequency
where f
sw,min
2.Calculate the high frequency error amplifier gain
Gc = 0.25 fc 2 π
L1
ESR
------------
3.Chose R3 and calculate
L1 C7
R3
-----------------------
C8 = 2
The value for R3 has not to be very high (for example 10K
offset current.
Ω) so to limit the error due to an error amplifier input
21/24
L5953
4.Calculate
R3
Rp = --------------------------------------------
2
L1
------------
------- – 1
ESR
C7
VO
------------------------
Vref, PWM
RA = Rp
Rp
R2 = --------------------------------
Vref,PWM
1 – -----------------------
VO
5.Finally calculate
and
R4 = GC R1
L1 C7
-----------------------
C9 = 2
R4
22/24
L5953
mm
inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
OUTLINE AND
MECHANICAL DATA
A
a1
a2
a3
b
3.60
0.141
0.012
0.130
0.004
0.015
0.012
0.630
0.385
0.570
0.10
0.30 0.004
3.30
0
0.10
0
0.22
0.23
0.38 0.008
0.32 0.009
16.00 0.622
9.80 0.370
14.50 0.547
c
D (1) 15.80
D1
E
9.40
13.90
e
0.65
0.0256
0.435
e3
11.05
E1 (1) 10.90
E2
11.10 0.429
2.90
0.437
0.114
0.244
0.126
0.004
0.626
0.043
0.043
E3
E4
G
H
5.80
2.90
0
6.20 0.228
3.20 0.114
0.10
0
15.50
15.90 0.610
1.10
h
L
0.80
1.10 0.031
10°(max.)
8 °(max.)
N
S
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
N
N
a2
A
c
a1
e
A
DETAIL B
lead
E
DETAIL A
e3
H
DETAIL A
D
slug
a3
BOTTOM VIEW
36
19
E3
B
E1
E2
D1
DETAIL B
0.35
Gage Plane
- C -
SEATING PLANE
1
1
8
S
L
G
C
M
b
0.12
A B
PSO36MEC
h x 45˚
(COPLANARITY)
23/24
L5953
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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