L5991AD [STMICROELECTRONICS]
PRIMARY CONTROLLER WITH STANDBY; 主控制器具有待机
| 型号： | L5991AD |
| 厂家： | 
ST |
| 描述： | PRIMARY CONTROLLER WITH STANDBY |
| 文件： | 总19页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L5991
L5991A
PRIMARY CONTROLLER WITH STANDBY
CURRENT-MODE CONTROL PWM
SWITCHING FREQUENCY UP TO 1MHz
MULTIPOWER BCD TECHNOLOGY
LOW START-UP CURRENT (< 120 A)
µ
HIGH-CURRENT OUTPUT DRIVE SUITABLE
FOR POWER MOSFET (1A)
FULLY LATCHED PWM LOGIC WITH DOU-
BLE PULSE SUPPRESSION
PROGRAMMABLE DUTY CYCLE
100%AND 50%MAXIMUMDUTY CYCLELIMIT
STANDBY FUNCTION
DIP16
SO16
PROGRAMMABLE SOFT START
PRIMARY OVERCURRENT FAULT DETEC-
TION WITH RE-START DELAY
PWM UVLO WITH HYSTERESIS
IN/OUT SYNCHRONIZATION
LATCHED DISABLE
INTERNAL 100ns LEADING EDGE BLANK-
ING OF CURRENT SENSE
ORDERING NUMBERS:
L5991/L5991A (DIP16)
L5991D/L5991AD (SO16)
line or DC-DC power supply applications using a
fixed frequencycurrent mode control.
Based on a standard current mode PWM control-
ler this device includes some features such as
programmable soft start, IN/OUT synchronization,
disable (to be used for over voltage protection and
for power management), precise maximum Duty
Cycle Control, 100ns leading edge blanking on
current sense, pulse by pulse current limit, over-
current protection with soft start intervention, and
Standbyfunction for oscillator frequencyreduction
when the converteris lightly loaded.
PACKAGE:DIP16 AND SO16
DESCRIPTION
This primary controller I.C., developed in BCD60II
technology, has been designed to implement off
BLOCK DIAGRAM
VCC
SYNC
DC-LIM
15
VREF
4
1
8
2
TIMING
RCT
25V
Vref
+
-
3
+
-
DC
T
15V/10V
PWM UVLO
14
9
-
DIS
DIS
VC
+
2.5V
13V
10
OUT
BLANKING
PWM
S
Q
R
OVER CURRENT
VREF
VREF OK
CLK
DIS
11
16
13
PGND
ST-BY
FAULT
SOFT-START
ISEN
SS
+
-
STAND-BY
2.5V
1.2V
7
+
E/A
-
5
VFB
2R
1V
R
12
6
D97IN725A
SGND
COMP
1/23
August 1999
L5991 - L5991A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply Voltage (ICC < 50mA) (*)
Output Peak Pulse Current
Value
selflimit
1.5
Unit
V
VCC
IOUT
A
Analog Inputs & Outputs (6,7)
-0.3 to 8
-0.3 to 6
V
Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16)
V
Ptot
Power Dissipation @ Tamb = 70 C (DIP16)
1
0.83
W
W
°
@ Tamb = 50°C (SO16)
Junction Temperature, Operating Range
Storage Temperature, Operating Range
Tj
-40 to 150
-55 to 150
°C
°C
Tstg
(*) maximum package power dissipation limits must be observed
PIN CONNECTION
SYNC
RCT
DC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ST-BY
DC-LIM
DIS
VREF
VFB
ISEN
SGND
PGND
OUT
COMP
SS
VCC
VC
THERMAL DATA
Symbol
Parameter
Value
80
Unit
Rth j-amb
Thermal Resistance Junction -Ambient (DIP16)
Thermal Resistance Junction -Ambient (SO16)
C/W
°
120
C/W
°
PIN FUNCTIONS
N.
1
Name
SYNC
RCT
Function
Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct
Oscillator pin for external CT, RA, RB components
Duty Cycle control
2
3
DC
4
VREF
VFB
5.0V +/-1.5% reference voltage @ 25°C
Error Amplifier Inverting input
5
6
COMP
SS
Error Amplifier Output
7
Soft start pin for external capacitor Css
Supply for internal ”Signal” circuitry
Supply for Power section
8
VCC
9
VC
10
11
12
13
14
15
OUT
PGND
SGND
ISEN
DIS
High current totem pole output
Power ground
Signal ground
Current sense
Disable. It must never be left floating. TIE to SGND if not used.
DC-LIM
Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is
imposed
16
ST-BY
Standby. Connect a resistor to RCT. Connect to VREF or floating if not used.
2/23
L5991 - L5991A
ELECTRICAL CHARACTERISTICS CC
j
°
Ω
(V = 15V; T = 0 to 105 C; RT = 13.3k (*) CT = 1nF;
unless otherwisespecified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
REFERENCE SECTION
VREF
Output Voltage
Line Regulation
Tj = 25 C; IO = 1mA
VCC = 12 to 20V; Tj = 25°C
IO = 1 to 10mA; Tj = 25°C
4.925
5.0
2.0
2.0
0.4
5.0
5.075
10
10
V
mV
mV
mV/°C
V
°
Load Regulation
Temperature Stability
Total Variation
Short Circuit Current
Power Down/UVLO
TS
Line, Load, Temperature
Vref = 0V
VCC = 6V; Isink = 0.5mA
4.80
30
5.130
150
0.5
IOS
mA
V
0.2
OSCILLATOR SECTION
Initial Accuracy
pin 15 = Vref;
Tj = 25°C
comp = 4.5V
pin 15 = Vref; VCC = 12 to 20V
comp = 4.5V
pin 15 = Vref; VCC = 12 to 20V
comp = 2V
95
93
100
100
50
105
107
53.5
kHz
kHz
kHz
V
V
46.5
V
Duty Cycle
pin 3 = 0,7V, pin 15 = VREF
pin 3 = 0.7V, pin 15 = OPEN
0
0
%
%
pin 3 = 3.2V, pin 15 = VREF
pin 3 = 3.2V, pin 15 = OPEN
47
93
%
%
Duty Cycle Accuracy
Oscillator Ramp Peak
Oscillator Ramp Valley
pin 3 = 2.79V, pin 15 = OPEN
75
2.8
0.75
80
3.0
0.9
85
3.2
1.05
%
V
V
ERROR AMPLIFIER SECTION
Input Bias Current
VFB to GND
VCOMP = VFB
VCOMP = 2 to 4V
VCC = 12 to 20V
0.2
2.5
90
3.0
2.58
µA
V
dB
dB
V
VI
Input Voltage
2.42
60
GOPL
SVR
VOL
VOH
IO
Open Loop Gain
Supply Voltage Rejection
Output Low Voltage
Output High Voltage
Output Source Current
Output Sink Current
Unit Gain Bandwidth
Slew Rate
85
Isink = 2mA
1.1
2.5
Isource = 0.5mA, VFB = 2.3V
VCOMP > 4V, VFB = 2.3V
VCOMP = 1.1V, VFB = 2.7V
5
0.5
2
6
1.3
6
4
8
V
mA
mA
MHz
V/µs
1.7
SR
PWM CURRENT SENSE SECTION
Ib
IS
Input Bias Current
Maximum Input Signal
Delay to Output
Gain
Isen = 0
VCOMP = 5V
3
15
A
µ
V
ns
V/V
V
0.92
1.0
70
3
1.08
100
3.15
1.3
2.85
1.1
Vt
Fault Threshold Voltage
1.2
SOFT START SECTION
ISSC SS Charge Current
ISSD
VSSSAT
VSSCLAMP
Tj = 25°C
VSS = 0.6V Tj = 25 C
DC = 0%
14
5
20
10
26
15
0.6
µA
A
µ
V
V
SS Discharge Current
SS Saturation Voltage
SS Clamp Voltage
°
7
LEADING EDGE BLANKING
Internal Masking Time
OUTPUT SECTION
100
ns
VOL
VOH
Output Low Voltage
Output High Voltage
IO = 250mA
1.0
20
V
V
V
V
µA
IO = 20mA; VCC = 12V
IO = 200mA; VCC = 12V
IO = 5mA; VCC = 20V
VCC = 20V VC = 24V
10
9
10.5
10
13
2
VOUT CLAMP Output Clamp Voltage
Collector Leakage
Ω
(*) RT = RA//RB, RA = RB = 27k , see Fig. 22.
3/23
L5991 - L5991A
ELECTRICAL CHARACTERISTICS
(continued.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
OUTPUT SECTION
Fall Time
Rise Time
UVLO Saturation
SUPPLY SECTION
CO = 1nF
CO = 2.5nF
CO = 1nF
CO = 2.5nF
VCC = VC = 0 to VCCON
Isink = 10mA
20
35
50
70
60
100
1.0
ns
ns
ns
ns
V
VCCON
VCCOFF
Vhys
Startup voltage
L5991
L5991A
L5991
L5991A
L5991
L5991A
14
7.8
15
8.4
10
7.6
5
0.8
75
16
9
11
V
V
V
V
V
V
µA
Minimum Operating Voltage
UVLO Hysteresis
9
7
4.5
0.5
40
8.2
IS
Start Up Current
Before Turn-on at:
120
VCC = VC = VCCON -0.5V
CT = 1nF, RT = 13.3kΩ, CO =1nF
(After turn on), CT = 1nF,
RT = 13.3kΩ, CO =0nF
I8 = 20mA
Iop
Iq
Operating Current
Quiescent Current
9
7.0
13
10
mA
mA
VZ
Zener Voltage
21
25
30
V
STANDBY FUNCTION
VREF-VST-BY
IST-BY = 2mA
Vcomp Falling
Vcomp Rising
45
2.5
4.0
mV
V
V
VT1
Standby Threshold
SYNCHRONIZATION SECTION
Master Operation
ISOURCE = 0.8mA
Vclock = 3.5V
Slave Operation
Low Level
V1
I1
Clock Amplitude
Clock Source Current
4
3
V
mA
7
V1
I1
Sync Pulse
1
V
V
mA
High Level
VSYNC = 3.5V
3.5
0.5
Sync Pulse Current
OVER CURRENT PROTECTION
Vt Fault Threshold Voltage
DISABLE SECTION
Shutdown threshold
Shutdown Current
1.1
2.4
1.2
1.3
2.6
V
2.5
330
V
µA
ISH
VCC = 15V
Figure 1. L5991 - Quiescentcurrent vs. input
voltage.
Figure 2. L5991 - Quiescentcurrent vs. input
voltage (after disable).
(X = 7.6V and Y= 8.4V for L5991A)
(X = 7.6V and Y= 8.4V for L5991A)
Iq [mA]
30
Iq [µ A ]
3 5 0
V 14 = 0, Pin2 = open
Tj = 25°C
20
8
3 0 0
2 5 0
2 0 0
6
4
1 5 0
V 14 = Vref
T j = 25 °C
0 .2
1 0 0
0 .15
0 .1
Y
X
5 0
Y
X
0 .05
0
0
0
4
8
1 2
1 6
2 0
2 4
0
4
8
12
16
Vcc [V ]
20
24
28
V cc [V ]
4/23
L5991 - L5991A
Figure 3. Quiescent current vs. input voltage.
Figure 4. Quiescentcurrent vs. input voltage
and switching frequency.
Iq [mA]
9.0
Iq [mA]
36
V 14 = 0, V5 = Vref
30
24
18
12
6
Co = 1nF, Tj = 25°C
R t = 4.5Kohm,Tj = 25°C
8.5
DC = 0%
1M hz
500Khz
300Khz
1M Hz
8.0
500KHz
300KHz
100Khz
7.5
100KHz
0
7.0
8
10
12
14
16
18
20
22
8
10
12
14
16
18
20
22
24
Vcc [V]
Vc c [V]
Figure 5. Quiescent current vs. input voltage
Figure 6. Reference voltage vs. load current.
and switchingfrequency.
Iq[mA]
Vref [V]
5.1
36
Co= 1nF, Tj = 25°C
30
DC = 100%
Vcc=15V
5.05
1MHz
24
Tj = 25°C
500KHz
5
18
300KHz
12
100KHz
4.95
4.9
6
0
0
5
10
Iref [mA]
15
20
25
8
10
12
14
16
18
20
22
Vcc[V]
Figure 7. Vref vs. junction temperature.
Figure 8. Vref vs. junction temperature.
Vref [V])
5.1
Vref [V]
5.1
Vcc = 15V
Vcc = 15V
5.05
5.05
Iref= 20mA
Iref = 1mA
5
5
4.95
4.9
4.95
4.9
-50
-25
0
25
50
75
100 125 150
-50
-25
0
25
50
Tj (°C)
75
100 125 150
5/23
Tj (°C)
L5991 - L5991A
Figure 9. Vref SVRR vs. switching frequency.
Figure 10. Output saturation.
Vsat = V [V]
SVRR (dB)
10
16
Vcc = Vc = 15V
Vcc=15V
Vp-p=1V
120
14
12
10
8
Tj = 25°C
80
40
0
6
0
0.2
0.4
0.6
Isource [A]
0.8
1
1.2
1
10
100
1000
10000
fsw (Hz)
Figure 11. Output saturation.
Figure 12. UVLO Saturation
Vsat = V10 [V]
2.5
Ipin10 [mA]
50
Vcc < Vccon
40
2
Vcc = Vc = 15V
Tj = 25°C
beforeturn-on
1.5
30
1
0.5
0
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
0
200 400 600 800 1,000 1,200 1,400
Vpin10 [mV]
Isink [A]
Figure 14. Switching frequency vs. tempera-
ture.
Figure13.Timingresistorvs.switchingfrequency.
fsw (KHz)
fsw (KHz)
320
5000
Vcc = 15V, V15 =0V
2000
Rt= 4.5Kohm, Ct = 1nF
Tj = 25°C
1000
310
Vcc = 15V, V15=Vref
500
100pF
300
290
280
200
220pF
100
470pF
50
1nF
2.2nF
5.6nF
20
10
-50
-25
0
25
50
75
100
125
150
10
20
30
40
Tj (°C)
Rt (kohm)
6/23
L5991 - L5991A
Figure 15. Switching frequency vs. temperature.
Figure 16. Dead time vs Ct.
Dead time [ns]
fsw (KHz)
320
1,500
1,200
900
Rt =4.5Kohm
Rt= 4.5Kohm, Ct = 1nF
V15 = 0V
310
Vcc = 15V, V15= 0
300
290
280
V15 = Vref
600
300
-50
-25
0
25
50
75
100
125 150
2
4
6
8
10
Tj (°C)
Timingcapacitor Ct [nF]
Figure 17. Maximum Duty Cycle vs Vpin3.
Figure18.Delaytooutputvsjunctiontemperature.
DC Control Voltage Vpin3 [V]
3.5
Delay to output (ns)
42
V15 = 0V
V15 = Vref
40
38
36
34
3
2.5
2
Rt = 4.5Kohm,
Ct = 1nF
32
PIN10 = OPEN
1V pulse
on PIN13
1.5
1
30
28
-50
-25
0
25
50
75
100
125
150
0
10 20 30 40 50 60 70 80 90 100
Duty Cycle [%]
Tj (°C)
Figure 19. E/A frequency response.
Phase
140
G [dB]
150
120
100
80
100
50
0
60
40
20
0.01
0.1
1
10
100
1000 10000 100000
f (KHz)
7/23
L5991 - L5991A
Figure 20. Standby dynamic operation.
STANDBY FUNCTION
Pin
The standby function, optimized for flyback topol-
ogy, automatically detects a light load condition
for the converter and decreases the oscillator fre-
quency on that occurrence. The normal oscillation
frequency is automaticallyresumed when the out-
put load builds up and exceeds a defined thresh-
old.
fosc
Normal operation
This function allows to minimize power losses re-
lated to switching frequency, which represent the
majority of losses in a lightly loaded flyback, with-
out giving up the advantagesof a higherswitching
frequency at heavy load.
PNO
fSB
PSB
Stand-by
This is accomplished by monitoring the output of
the Error Amplifier (VCOMP) that depends linearly
on the peak primary current, except for an offset.
V
T2
V
T1
1
2
3
4
VCOMP
If the the peak primary current decreases (as a re-
sult of a decrease of the power demanded by the
load) and VCOMP falls below a fixed threshold
(VT1), the oscillator frequency will be set to a
lower value (fSB). When the peak primary current
increases and VCOMP exceedsa secondthreshold
(VT2) the oscillator frequency is set to the normal
value (fosc). An appropriate hysteresis (VT2-VT1)
prevents undesired frequency change when
power is such that VCOMP moves close to the
threshold.This operationis shown in fig. 20.
matically the master.
During the ramp-up of the oscillator the pin is
pulled low by a 600µA internal sink current gener-
ator. During the falling edge, that is when the
µ
pulse is released, the 600 A pull-down is discon-
nected. The pin becomes a generator whose
source capability is typically 7mA (with a voltage
still higher than 3.5V).
In fig. 21, some practical examples of synchroniz-
ing the L5991 are given.
Since the device automatically diminishes its op-
erating frequency under light load conditions, it is
reasonable to suppose that synchronization will
refer to normal operationand not to standby.
Both the normal and the standby frequency are
externally programmable. VT1 and VT2 are inter-
nally fixed but it is possible to adjust the thresh-
olds in terms of input power level.
Pin 2.
RCT (Oscillator). Two resistors (RA and RB)
APPLICATION INFORMATION
Detailed Pin Function Description
and one capacitor (CT), connected as shown in
fig. 22, allow to set separately the operating fre-
Pin 1. SYNC (In/Out Synchronization). This func-
tion allows the IC’s oscillator either to synchronize
other controllers (master) or to be synchronized to
an externalfrequency(slave).
As a master, the pin delivers positive pulses dur-
ing the falling edge of the oscillator (see pin 2). In
slave operationthe circuit is edge triggered. Refer
to fig. 22 to see how it works. When several IC
work in parallel no master-slave designation is
needed because the fastest one becomes auto-
quency of the oscillator in normal operation (fosc
and in standbymode (fSB).
)
CT is chargedfrom Vref through RA and RB in nor-
mal operation (STANDBY = HIGH), through RA
only in standby ( STANDBY = LOW). See pin 16
description to see how the STANDBY signal is gen-
erated.
When the voltage on CT reaches 3V, the capaci-
tor is quickly internally discharged. As the voltage
has dropped to 1V it starts being charged again.
Figure 21. Synchronizing the L5991.
RA
RB
SYNC
ST-BY
VREF
SYNC
ST-BY
VREF
RB
1
16
4
1
L4981A
(MASTER)
16
4
4
L4981A
(SLAVE)
L5991
(SLAVE)
1
RCT
SYNC
L5991
2
L5991
SYNC
VREF
2
1
L5991
(MASTER)
16
16
SYNC
2
17
18
2
17
18
RA
16
RA
RB
CT
RCT
RCT
RCT
ST-BY
ROSC
ROSC
CT
COSC
CT
COSC
(a)
(b)
D97IN728A
(c)
8/23
L5991 - L5991A
Figure 22. Oscillatorand synchronization internal schematic.
SYNC
1
VREF
4
R1
R2
D
Q
R
CLAMP
600µA
RA
R3
+
-
CLK
RCT
2
D1
RB
CT
50Ω
ST-BY
16
STANDBY
D97IN729A
from fig. 13 or resulting from (1) and (2).
The oscillation frequency can be established with
the aid of the diagrams of fig. 13, where RT will be
intended as the parallel of RA and RB in normal
operation and RT = RA in standby, or considering
the following approximate relationships:
To prevent the oscillator frequency from switching
back and forth from fosc to fSB, the ratio fosc / fSB
must not exceed5.5.
If during normal operation the IC is to be synchro-
nized to an external oscillator, RA, RB and CT
should be selected for a fosc lower than the master
frequency in any condition (typically, 10-20% ),
dependingalso on the tolerance of the parts.
1
fosc
(1),
(
(
) +
CT 0.693 RA // RB KT
which gives the normal operatingfrequency, and:
1
Pin 3.
DC (Duty Cycle Control). By biasing this
pin with a voltage between 1 and 3 V it is possible
to set the maximum duty cycle between 0 and the
upper extreme Dx (see pin 15).
fSB
(2),
CT (0.693 R + K )
A
T
If Dmax is the desired maximum duty cycle, the
voltageV3 to be applied to pin 3 is:
which gives the standby frequency, that is the one
the converter will operateat when lightly loaded.
In the above expressions, RA // RB means:
V3 = 5 - 2(2-Dmax) (5)
RA RB
RA//RB =
,
RA + RB
Dmax is determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 23),
thus in case the device is synchronized to an ex-
ternal frequency fext (and therefore the oscillator
amplitude is reduced), (5) changes into:
while KT is defined as:
90 V15 = VREF
=
( )
3 ,
KT
160
= GND
/OPEN
V15
Dmax
and is related to the duration of the falling-edge of
the sawtooth:
V3 = 5 − 4 exp −
(6)
RT CT fext
Td
10−9 KT
+ CT ( )
4 .
≈ 30
A voltage below 1V will inhibit the driver output
stage. This could be used for a not-latcheddevice
disable, for example in case of overvoltage pro-
tection (see applicationideas).
If no limitation on the maximum duty cycle is re-
quired (i.e. DMAX = DX), the pin has to be left float-
ing. An internal pull-up (see fig. 23) holds the volt-
age above 3V. Should the pin pick up noise (e.g.
Td is also the duration of the sync pulses deliv-
ered at pin 1 and definesthe upper extreme of the
duty cycle range, Dx (see pin 15 for DX definition
and calculation) since the output is held low dur-
ing the falling edge.
In case V15 is connected to VREF, however, the
switching frequency will be a half the values taken
9/23
L5991 - L5991A
during ESD tests), it can be connected to VREF
through a 4.7kΩ resistor.
duce the oscillator frequency when the converter
is lightly loaded (standby).
Pin 7. SS (Soft-Start). At device start-up, a ca-
pacitor (Css) connected between this pin and
SGND (pin 12) is charged by an internal current
generator, ISSC, up to about 7V. During this
ramp, the E/A output is clamped by the voltage
across Css itself and allowed to rise linearly, start-
ing from zero, up to the steady-state value im-
posed by the control loop. The maximum time in-
terval during which the E/A is clamped, referred to
as soft-starttime, is approximately:
Figure 23. Duty cycle control.
VREF
4
3
R1
R2
3µA
DC
23K
28K
RA
3 Rsense IQpk
Tss
Css
(7)
ST-BY
RCT
I
SSC
16
2
TO PWM LOGIC
+
RB
where Rsense is the current sense resistor (see pin
13) and IQpk is the switch peak current (flowing
through Rsense), which depends on the output
load. Usually, CSS is selected for a TSS in the or-
der of milliseconds.
-
CT
D97IN727A
As mentioned before, the soft-start intervenes
also in case of severe overload or short circuit on
the output. Referring to fig. 24, pulse-by-pulse
current limitation is somehow effective as long as
Pin 4.
VREF (Reference Voltage). The device is
provided with an accurate voltage reference
(5V±1.5%) able to deliver some mA to an external
circuit.
µ
A small film capacitor (0.1 F typ.), connected
Figure 24. Regulation characteristicand re-
lated quantities.
between this pin and SGND, is recommended to
ensure the stability of the generator and to prevent
noisefromaffectingthereference.
VOUT
IQpk
Before device turn-on,this pin has a sink current ca-
pabilityof0.5mA.
A
D.C.M.
C.C.M.
1-2 ·IQpk
IQpk(max)
Pin 5. VFB (Error Amplifier Inverting Input). The
feedback signal is applied to this pin and is com-
pared to the E/A internal reference (2.5V). The
E/A output generates the control voltage which
fixes the duty cycle.
C
B
TON
D
TON(min)
The E/A features high gain-bandwidth product,
which allows to broaden the bandwidth of the
overall control loop, high slew-rate and current ca-
pability, which improves its large signal behavior.
Usually the compensation network, which stabi-
lizes the overall control loop, is connected be-
tween this pin and COMP (pin 6).
D97IN495
ISHORT IOUT(max)
IOUT
the ON-time of the power switch can be reduced
(from A to B). After the minimum ON-time is
reached (from B onwards) the current is out of
control.
To prevent this risk, a comparator trips an over-
current handling procedure, named ’hiccup’ mode
operation, when a voltage above 1.2V (point C) is
detected on current sense input (ISEN, pin 13).
Basically, the IC is turned off and then soft-started
as long as the fault condition is detected. As a re-
sult, the operating point is moved abruptly to D,
creating a foldback effect. Fig. 25 illustrates the
operation.
Pin 6.
COMP (Error Amplifier Output). Usually,
this pin is used for frequency compensation and
the relevant network is connected between this
pin and VFB (pin 5). Compensation networks to-
wards ground are not possible since the L5991
E/A is a voltage mode amplifier (low output im-
pedance). See application ideas for some exam-
ple ofcompensationtechniques.
It is worth mentioning that the calculation of the
part values of the compensation network must
take the standby frequency operation into ac-
count. In particular, this means that the open-loop
crossover frequency must not exceed fSB/4 ÷
fSB/5.
The oscillation frequency appearing on the soft-
start capacitor in case of permanent fault, referred
to as ’hiccup” period, is approximatelygiven by:
1
1
ISSD
Thic 4.5
+
Css (8)
The voltage on pin 6 is monitored in order to re-
I
SSC
10/23
L5991 - L5991A
MOS. At turn-on the gate resistance is Rg + Rg’, at
turn-off is Rg only.
Since the system tries restarting each hiccup cy-
cle, there is not any latchoff risk.
”Hiccup” keeps the system in control in case of
short circuits but does not eliminate power com-
ponents overstress during pulse-by-pulse limita-
tion (from A to C). Other external protection cir-
cuits are needed if a better control of overloads is
required.
Figure 26. Turn-on and turn-off speeds adjust-
ment.
Rg’
VCC
VC
9
Rg(ON)=Rg+Rg’
Rg(OFF)=Rg
8
Pin 8.
VCC (Controller Supply). This pin supplies
13V
the signal part of the IC. The device is enabled as
VCC voltage exceeds the start threshold and
works as long as the voltage is above the UVLO
threshold. Otherwise the device is shut down and
the current consumption is extremely low
10
DRIVE
&
CONTROL
OUT
Rg
L5991
11
µ
(<150 A). This is particularly useful for reducing
D97IN726
PGND
the consumption of the start-up circuit (in the sim-
plest case, just one resistor), which is one of the
most significant contributions to power losses in
standby.
An internal Zener limits the voltage on VCC to
25V. The IC current consumption increases con-
siderably if this limit is exceeded.
Pin 10.
OUT (Driver Output). This pin is the out-
put of the driver stage of the external power
switch. Usually, this will be a PowerMOS, al-
though the driver is powerful enough to drive
BJT’s (1.6A source, 2A sink, peak).
A small film capacitor between this pin and SGND
(pin 12), placed as close as possible to the IC, is
recommendedto filter high frequency noise.
The driver is made up of a totem pole with a high-
side NPN Darlington and a low-side VDMOS, thus
there is no need of an external diode clamp to
prevent voltage from going below ground. An in-
ternal clamp limits the voltage delivered to the
gate at 13V. Thus it is possible to supply the
driver (Pin 9) with higher voltages without any risk
of damage for the gate oxide of the external MOS.
The clamp does not cause any additional in-
crease of power dissipation inside the chip since
the current peak of the gate charge occurs when
the gate voltage is few volts and the clamp is not
active. Besides, no current flows when the gate
voltageis 13V, steady state.
Pin 9. VC (Supply of the Power Stage). It supplies
the driver of the external switch and therefore ab-
sorbs a pulsed current. Thus it is recommendedto
place a buffer capacitor (towards PGND, pin 11,
as close as possible to the IC) able to sustain
these current pulses and in order to avoid them
inducing disturbances.
This pin can be connected to the buffer capacitor
directly or through a resistor, as shown in fig. 26,
to control separately the turn-on and turn-off
speed of the external switch, typically a Power-
Under UVLO conditions an internal circuit (shown
Figure 25. Hiccup mode operation.
I
OUT
SHORT
I
SEN
FAULT
SS
5V
7V
0.5V
time
D98IN986
T
hic
11/23
L5991 - L5991A
in fig.27) holds the pin low in order to ensure that
the external MOS cannot be turned on acciden-
tally. The peculiarity of this circuit is its ability to
mantain the same sink capability (typically, 20mA
@ 1V) from VCC = 0V up to the start-up threshold.
When the threshold is exceeded and the L5991
starts operating,VREFOK is pulled high (refer to fig.
27) and the circuit is disabled.
It is then possible to omit the ”bleeder” resistor
(connected between the gate and the source of
the MOS) ordinarily used to prevent undesired
switching-on of the external MOS because of
some leakage current.
Pin 13.
ISEN (Current Sense). This pin is to be
connected to the ”hot” lead of the current sense
resistor Rsense (being the other one grounded), to
get a voltage ramp which is an image of the cur-
rent of the switch (IQ). When this voltage is equal
to:
V
COMP
− 1.4
V13pk = I
Rsense
=
(9)
Qpk
3
the conductionof the switch is terminated.
To increase the noise immunity, a ”Leading Edge
Blanking” of about 100ns is internally realized as
shown in fig. 28. Because of that, the smoothing
RC filter between this pin and Rsense could be re-
moved or, at least, considerablyreduced.
Figure 27. Pull-Down of the output in UVLO.
OUT
10
Pin 14.
DIS (Device Disable). When the voltage
on pin 14 rises above 2.5V the IC is shut down
and it is necessaryto pull VCC (IC supply voltage,
pin 8) below the UVLO threshold to allow the de-
vice to restart.
VREFOK
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
29. It is also possible to realize an overvoltage
protection, as shown in the section ” Application
Ideas”.Ifused, bypass this pin to ground with a fil-
ter capacitor to avoid spurious activation due to
noise spikes. If not, it must be connected to
SGND.
12
SGND
D97IN538
Pin 11.
PGND (Power Ground). The current loop
during the discharge of the gate of the external
MOS is closed through this pin. This loop should
be as short as possible to reduce EMI and run
separately from signal currents return.
Pin 15. DC-LIM (Maximum Duty Cycle Limit). The
upper extreme, Dx, of the duty cycle range de-
pends on the voltage applied to this pin. Approxi-
mately,
Pin 12
. SGND (Signal Ground). This ground refer-
ences the control circuitry of the IC, so all the
ground connections of the external parts related
to control functions must lead to this pin. In laying
out the PCB, care must be taken in preventing
switched high currents from flowing through the
SGND path.
RT
(10)
Dx
RT + 230
if DC-LIM is grounded or left floating. Instead,
Figure 28. Internal LEB.
2V
I
3V
+
0
-
CLK
PWM
13
COMPARATOR
TO PWM
LOGIC
ISEN
+
-
FROM E/A
TO FAULT
LOGIC
+
-
1.2V
OVERCURRENT
COMPARATOR
D97IN503
12/23
L5991 - L5991A
Figure 29. Disable (Latched).
and the output switching frequency will be halved
with respect to the oscillator one because an in-
ternal T flip-flop (see block diagram) is activated.
Fig. 30 shows the operation.
The half duty cycle option speeds up the dis-
charge of the timing capacitor CT (in order to get
duty cycles as close to 50% as possible) so the
oscillator frequency- with the same timing compo-
nents will be slightly higher.
DISABLE
SIGNAL
DIS
14
+
-
D
R
DISABLE
Q
C
Pin 16
. S-BY (Standby Function). The resistor RB,
2.5V
along with RA, sets the operating frequencyof the
oscillator in normal operation (fosc). In fact, as long
as the STANDBY signal is high, the pin is inter-
nally connected to the reference voltage VREF by
a N-channel FET (see fig. 31), so the timing ca-
pacitor CT is charged through RA and RB. When
the STANDBY signal goes low the N-channel FET
is turned off and the pin becomes floating. RB is
UVLO
D97IN502
connecting DC-LIM to VREF (half duty cycle op-
tion), Dx will be set approximately at:
RT
Dx
(11)
2 R + 260
T
Figure 30. Half duty cycle option.
t
d
V15=GND
V5=V13=GND
V2
V10
V2
t
c
+ t
D
X
=
t
c
d
t
c
t
d
V15=VREF
V5=V13=GND
t
c
D
X
=
2 ·t + t
c
d
V10
t
c
D97IN498
Figure 31. Standby function internal schematic and operation.
COMP
6
ISEN
13
+
-
2R
R
DRIVER
OUT
R
STANDBY
HIGH
10V
4
5
FB
-
VREF
+
-
STANDBY
+
2.5
ST-BY
2.5/4
LEVEL SHIFT
STANDBY BLOCK
16
2
LOW
RB
RA
VT1
2.5V
VT2
4V
VCOMP
RCT
CT
D97IN752B
13/23
L5991 - L5991A
now disconnected and CT is charged through RA
only. In this way the oscillator frequency (fSB) will
be lower. Refer to pin 2 description to see how to
calculate the timing components.
Layout hints
Generally speaking a proper circuitboard layout is
vital for correct operation but is not an easy task.
Careful component placing, correct traces routing,
appropriate traces widths and, in case of high
voltages, compliance with isolation distances are
the major issues. The L5991 eases this task by
putting two pins at disposal for separate current
returns of bias (SGND) and switch drive currents
(PGND) The matter is complex and only few im-
portant points will be here reminded.
1) All current returns (signal ground, power
ground, shielding, etc.) should be routed sepa-
rately and should be connected only at a single
ground point.
Typical values for VT1 and VT2 are 2.5 V and 4V
respectively. This 1.5V hysteresis is enough to
prevent undesired frequency change up to a 5.5
to 1 fosc/ fSB ratio.
The value of VT1 is such that in a discontinuous
flyback the standby frequency is activated when
the input power is about 13% of the maximum. If
necessary, it is possible to decrease the power
threshold below 13% by adding a DC offset (Vo)
on the current sense pin (13, ISEN). This will also
allow a frequencychange greater than 5.5 to 1.
The following equations,useful for design, apply:
2) Noise coupling can be reduced by minimizing
the area circumscribed by current loops. This
applies particularly to loops where high pulsed
currentsflow.
3) For high current paths, the traces should be
doubled on the other side of the PCB whenever
possible: this will reduce both the resistance
and the inductanceof the wiring.
2
0.367 − Vo
1
2
PinSB
=
LP
ƒ
(12),
(13),
osc
Rsense
2
0.867 − Vo
Rsense
1
2
PinNO
=
LP
ƒ
SB
4) Magnetic field radiation (and stray inductance)
can be reduced by keeping all traces carrying
switched currentsas short as possible.
2
ƒosc
ƒSB
0.867 − Vo
<
(14),
5) In general, traces carrying signal currents
should run far from traces carrying pulsed cur-
rents or with quickly swinging voltages. From
this viewpoint, particular care should be taken
of the high impedance points (current sense in-
put, feedback input, ...). It could be a good idea
to route signal traces on one PCB side and
power traceson the other side.
0.367 − V
o
where PinSB is the input power below which the
L5991 recognizes a light load and switches the
oscillator frequency from ƒosc to fSB, P
is the
inNO
input power above which the L5991 switches
ƒ
ƒ
osc
back from
to
and Lp the primary induc-
SB
tance of the flyback transformer.
6) Provide adequate filtering of some crucial
points of the circuit, such as voltage references,
IC’s supply pins, etc.
Connect to Vref or leave open this pin when
stand-by functionis not used.
14/23
L5991 - L5991A
either improving performance or solving common
application problems of L5991 based supplies.
APPLICATION IDEAS
Here follows a series of ideas/suggestionsaimed at
Figure 32. Typical application circuit for computer monitors (90W).
9DIN703A
15/23
L5991 - L5991A
Figure 33. Typical application circuit for inkjet printers (40W).
9D7IN168
16/23
L5991 - L5991A
Figure 34. Standby thresholds adjustment.
SGND
10
L5991
12
4
13
R
VREF
ISEN
RA
RSENSE
OPTIONAL
D97IN751A
Figure 35. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies.
VIN
ISOLATION
BOUNDARY
VC
9
10
OUT
L5991
ISEN
13
12
11
PGND
SGND
D97IN761
Figure 36. Low consumption start-up.
VIN
2.2MΩ
33KΩ
STD1NB50-1
VCC
T
VREF
SELF-SUPPLY
WINDING
8
20V
4
L5991
47KΩ
12 11
D97IN762B
Figure 37. Bipolar transistor driver.
VIN
VCC
VC
9
8
10
13
OUT
ISEN
L5991
11
PGND
D97IN763
17/23
L5991 - L5991A
Figure 38. Typical E/A compensationnetworks.
+
From VO
Ri
2.5V
1.3mA
2R
+
-
VFB
Rf
5
6
EA
R
Rd Cf
COMP
12
SGND
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.
+
From VO
RP
2.5V
1.3mA
2R
+
-
Ri
VFB
Rf
5
6
EA
R
CP
Rd
Cf
COMP
12
SGND
D97IN507
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.
Figure 39. Feedback with optocoupler.
VOUT
COMP
6
L5991
5
TL431
VFB
D97IN759
Figure 40. Slope compensation techniques.
ST-BY
VREF
ST-BY
16
4
16
OUT
R
VREF
10
4
RB
RA
RB
RA
RCT
RCT
2
2
CT
CSLOPE
CT
RSLOPE
I
L5991
12
I
L5991
L5991
RSLOPE
RSLOPE
ISEN
ISEN
ISEN
13
13
13
12
12
RSENSE
RSENSE
RSENSE
SGND
SGND
SGND
OPTIONAL
OPTIONAL
OPTIONAL
D97IN760A
18/23
L5991 - L5991A
Figure 41. Protection against overvoltage/feedbackdisconnection (latched)
RSTART
RSTART
VCC
VCC
VZ
8
8
DIS
2.2K
DIS
14 L5991
12
14 L5991
12
11
11
SGND
PGND
SGND
PGND
D98IN905
D97IN754
Figure 42 Protection against overvoltage/feed-
back disconnection (not latched)
Figure 43. Device shutdown on overcurrent
2.5
R2
Ipk max
•
1-
VREF
DIS
RSENSE
R1
RSTART
4
R1
Ipk
I
VCC
14
VREF
4
3
8
L5991
R2
DC
L5991
ISEN
13
11
12
RSENSE
PGND
SGND
12
11
OPTIONAL
D97IN756A
D97IN755A
Figure 44. Constant power in pulse-by-pulse current limitation (flyback discontinuous)
VIN
80 ÷ 400VDC
L
p
RFF
R·L
p
OUT
RFF = 6·106
R
SENSE
10
L5991
ISEN
13
11
12
R
R
SENSE
PGND
SGND
D97IN757
Figure 45. Voltage mode operation.
DC
3
10K
L5991
6
12
13
COMP
SGND
ISEN
D97IN758A
19/23
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