L6227DTR [STMICROELECTRONICS]
DMOS dual full bridge driver with PWM current controller;
| 型号： | L6227DTR |
| 厂家： | 
ST |
| 描述： | DMOS dual full bridge driver with PWM current controller 驱动器 |
| 文件： | 总11页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6227
DUAL DMOS FULL BRIDGE MOTOR DRIVER
PRELIMINARY DATA
■
OPERATING SUPPLY VOLTAGE FROM 8 TO
52V
■
■
2.8A PEAK CURRENT (1.4A DC)
Ω
0.73 TYP. VALUE @ T = 25 °C
j
R
DS (ON)
■ BUILT-IN CONSTANT OFF TIME PWM
PowerDIP24
(20+2+2)
PowerSO36
SO24
(20+2+2)
CURRENT CONTROL
ORDERING NUMBERS:
■
HIGH SIDE OVER CURRENT PROTECTION
2.8A TYP
L6227N L6227PD
L6227D
■
CROSS CONDUCTION PROTECTION
manufactured with Multipower BCD technology
which combines isolated DMOS power transistors
with CMOS and bipolar circuits on the same chip.
The Logic Inputs are CMOS/TTL andµP compatible.
Additional circuitry to realize a constant off time PWM
control has been implemented for each bridge.
Each full bridge is controlled by a separate Enable
and has a sense pin for the current sense resistor in-
sertion. Other features are the protection of the high
side switches against unsafe over current conditions,
the thermal shutdown and the inhibit function that al-
lows to disable all bridges and to reduce the quies-
cent current to very low values (typ. 1.1mA).
■
THERMAL SHUTDOWN
■
OPERATING FREQUENCY UP TO 100KHz
■ INTRINSIC FAST FREE WHEELING DIODES
■
UNDER VOLTAGE LOCKOUT
■
INHIBIT FUNCTION FOR LOW POWER
CONSUMPTION
TYPICAL APPLICATIONS
■ STEPPER MOTOR
■
DUAL OR QUAD DC MOTOR
DESCRIPTION
The L6227 is a dual full bridge driver for motor control
The L6227 is assembled in PowerDIP24(20+2+2),
PowerSO36 and SO24(20+2+2) packages.
BLOCK DIAGRAM
OUT1A
SENSEA
OUT2A
VS A
VS
A
VS
VS
A
A
GND
GND
GND
GND
ENA
Vref A
PWMA
RCA /INH
VBOOT
Logic
&
Drivers
ENB
IN1A
IN2A
IN1B
IN2B
Charge
Pump
VCP
Vref B
RCB
PWMB
VS
B
VS
B
VS
B
OUT1B
SENSEB
OUT2B
VS
B
March 2001
1/11
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6227
FUNCTIONAL BLOCK DIAGRAM
Vboot
VCP
Voltage
Thermal
Regulator
Protection
VSA
Charge
Pump
Vboot
Vboot
Vboot
10V
5V
ENA
IN1A
OUT1A
OUT2A
Over
Current
Detection
IN2A
10V
10V
RCA/INH
SENSE A
Logic
VrefA
BIPOLAR
STEPPER
MOTOR
Masking
Time
One Shot
Sense
Comparator
ENB
IN1B
IN2B
PWM
BRIDGE A
BRIDGE B
VSB
OUT1B
OUT2B
RCB
SENSE B
VrefB
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply Voltage
Input and Enable Voltage Range
Voltage Range at V pins
Test conditions
Value
Unit
V
60
V
V
V
V
S
V ,V
IN EN
-0.3 to +7
-0.3 to +7
-0.3 to +7
V
, V
refB
refA
ref
V
V
Voltage Range at RC /INH and
A
RCA, RCB
RC pins
B
V
DC Sensing Voltage Range
Bootstrap Peak Voltage
-1 to +4
V
V
A
SENSE
V
V + 10
S
BOOT
I
Pulsed Supply Current (for each
t
< 1ms
3.55
S(peak)
PULSE
V
pin), internally limited by the
S
overcurrent protection
I
DC Supply Current (for each V
pin)
1.4
60
A
V
S
S
V
Differential Voltage Between
OD
V
S A
, OUT1 , OUT2 , SENSE and
A A A
V
, OUT1 , OUT2 , SENSE
S B B B B
T
, T
stg OP
Storage and Operating
Temperature Range
-40 to 150
°C
2/11
L6227
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
MIN
MAX
52
Unit
V
V
Supply Voltage
12
S
V
OD
Differential Voltage Between
, OUT1 , OUT2 , SENSE and
52
V
V
S A
A
A
A
V
, OUT1 , OUT2 , SENSE
S B B B B
V
Sensing voltage
SENSE
(pulsed tw<t )
-6
-1
6
1
V
V
rr
(DC)
V
V
Operating Voltage
ref
-0.1
5
V
A
ref
I
DC Output Current
1.4
OUT
T
Operating Junction Temperature
Switching Frequency
-25
+125
100
°C
kHz
j
f
sw
PIN CONNECTION
(Top View)
GND
1
36
GND
NC
NC
NC
2
35
34
33
32
31
30
29
28
27
26
3
NC
VSA
4
VSB
IN1A
IN2A
1
24
VREFA
ENA
OUT2A
NC
5
OUT2B
NC
2
23
22
21
20
19
18
17
16
15
14
6
SENSEA
RCA/INH
3
VCP
VCP
7
VBOOT
ENB
4
OUT2A
VSA
ENA
8
OUT1A
GND
5
VREFA
IN1A
9
VREFB
IN2B
6
GND
10
11
12
GND
7
GND
IN2A
IN1B
OUT1B
RCB
8
VSB
SENSEA
RCA/INH 13
25
24
SENSEB
RCB
9
OUT2B
VBOOT
ENB
SENSEB
IN1B
10
11
12
NC
OUT1A
NC
14
15
16
17
18
23
22
21
20
19
NC
OUT1A
NC
NC
IN1B
13
VREFB
NC
GND
GND
PowerDIP24/SO24
PowerSO36
3/11
L6227
PIN DESCRIPTION
PowerDIP24/
SO24
Name
PowerSO36
Function
V
V
4
20
17
Supply Voltage of the Bridge A.
SA
SB
33
Supply Voltage of the Bridge B. This pin must be connected to V
.
SA
OUT1
OUT2
15
5
5
21
Bridge A outputs.
A
A
OUT1
OUT2
22
32
8
16
Bridge B outputs.
B
B
SENSE
SENSE
GND
12
25
3
10
Sense resistor for the bridge A.
Sense resistor for the bridge B.
A
B
1,18,19,36
6,7,18,19
Common ground terminals. In Powerdip and SO packages, these pins are
also used for heat dissipation toward the PCB.
EN
EN
8
23
14
Enable of the Bridge A. A LOW logic levelapplied to this pin switches off
all the power DMOSs of the related bridge.
The OCSA open drain is internally connected to this pin.
A
29
Enable of the Bridge B. A LOW logic level applied to this pin switches off
all the power DMOSs of the related bridge.
B
The OCSB open drain is internally connected to this pin.
IN1
IN2
10
11
1
2
Logic inputs of the Bridge B. Provided the ENA signal is HIGH, a HIGH
logic levelapplied to any of these pins switches on the related high side
power DMOS, while a logic LOW switches on the related low side power
DMOS .
A
A
IN1
IN2
26
27
11
12
Logic inputs of the Bridge B. Provided the ENB signal is HIGH, a HIGH
logic levelapplied to any of these pins switches on the related high side
power DMOS, while a logic LOW switches on the related low side power
DMOS .
B
B
V
7
22
15
4
Bootstrap Oscillator. Oscillator output for the external charge pump.
Supply voltage to overdrive the upper DMOSs.
CP
V
30
13
24
BOOT
RC /INH
A parallel RC network connected to these pins sets the OFF time of the
low-side power DMOS of the correspondent bridge. The pulse generator is
a monostable triggered by the output of the sense comparator of the
A
RC
9
B
bridge (t
= 0.69 RC). Pulling the RC /INH pin to ground switches all the
OFF
A
BRIDES off and reduces the quiescent current to 1.1mA typ.
V
V
9
24
13
A voltage applied to these pins sets the reference voltage of the sense
comparators, determining the output current in PWM current control.
ref A
ref B
28
4/11
L6227
THERMAL DATA
Symbol
Description
PowerDIP24
SO24
15
PowerSO36
Unit
°C/W
°C/W
R
MaximumThermal Resistance Junction-Pins
Maximum Thermal Resistance Junction-Case
19
-
-
2
-
th-j-pins
R
R
-
th-j-case
(1)
43
51
C/W
°
th-j-amb1
th-j-amb1
th-j-amb1
th-j-amb2
MaximumThermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
MaximumThermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
(2)
(3)
(4)
R
R
R
-
-
-
-
36
16
63
°C/W
°C/W
°C/W
59
78
2
(1) Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm (with a thickness of 35 µm).
2
(2) Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm (with a thickness of 35 µm).
2
(3) Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm (with a thickness of 35 µm), 16 via holes
and a ground layer.
(4) Mounted on a multiplayer PCB without any heatsinking surface on the board..
ELECTRICAL CHARACTERISTICS
(T
amb
= 25 °C, V = 48V, unless otherwise specified)
s
Symbol
Parameter
Supply Voltage
Test Conditions
Min
Typ
Max
52
Unit
V
V
8
S
I
Quiescent Supply Current
All Bridges OFF; -25°C<T <125°C
5.5
10
mA
S
j
T
Thermal Shutdown Temperature
150
C
°
j
Output DMOS Transistors
I
Leakage Current
V
= 52V
S
1
mA
Ω
DSS
R
High-side + Low-side Switch ON
Resistance
T = 25 °C
j
1.47
2.35
1.69
2.7
DS(ON)
T =125 °C
j
Ω
Source Drain Diodes
V
Forward ON Voltage
I
= 1.4A, EN = LOW
SD
1.2
V
SD
t
Reverse Recovery Time
Forward Recovery Time
I = 1.4A
f
300
200
ns
ns
rr
t
fr
Switching Rates
(5)
(5)
t
I
= 1.4 A
LOAD
250
600
105
450
500
78
ns
ns
ns
ns
ns
ns
D(on)EN
Enableto out turn ON delay time
Input to out turn ON delay time
t
D(on)IN
(5)
t
20
20
300
300
ON
D(off)EN
Output rise time
(5)
(5)
t
Enableto out turn OFF delay time
Input to out turn OFF delay time
t
D(off)IN
(5)
t
off
Output fall time
t
Dead time protection
1
1
µs
µs
dt
t
Internal blanking time on SENSE
pins
1.5
1
blank
f
Charge pump frequency
-25°C<T <125°C
0.75
MHz
CP
j
5/11
L6227
ELECTRICAL CHARACTERISTICS
(continued)
(T
amb
= 25 °C, V = 48V, unless otherwise specified)
s
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
UVLO comp
V
Turn ON threshold
Turn OFF threshold
6.6
5.6
7
6
7.4
6.4
V
V
th(ON)
V
th(OFF)
Logic Input
V
Low level logic input voltage
High levellogic input voltage
High levellogic input current
Low level logic input current
-0.3
2
0.8
7
V
V
INL
V
I
INH
V
V
= 5 V
70
-10
A
µ
INH
IN, EN
IN, EN
I
= GND
µA
INL
Over Current Protection
I
Input supply overcurrent protection -25°C<T <125°C
threshold
2
2.8
3.55
0.4
A
V
S OVER
j
V
Open drain low level output voltage I = 4 mA
DIAG
Comparator and Monostable
Source current at RC /INH and
I
V
, V = 2.5 V
RCA/INH RCA
3
5
mA
V
RCA,
RCB
A
RC pins
B
V
Input common mode comparator
voltage range
-0.1
5
ref
V
Comparator threshold voltage on
SENSE pins
V
V
= 0.5 V
= 0.5 V
V
5mV
-
V
5mV
+
ref
th
ref A, B
ref A, B
ref
(6)
t
0.1
0.2
0.3
µs
prop
Turn OFF propagation delay
t
PWM Recirculation time
20 kΩ < R < 100 kΩ
0.1 nF < C < 100 nF
0.67RC 0.69RC 0.71RC
0.2
s
OFF
I
Input bias current at V pins
µA
bias
ref
Inhibit
INH
Voltage threshold at the RC /INH
pin to enable the inhibit function
-25°C<T <125°C
1
1.25
1.25
50
1.5
1.5
V
th
A
j
t
Delay time to enable the inhibit
function
µs
dINHON
t
Delay time to disable the inhibit
function
R = 20kΩ
µs
dINHOFF
C = 1 F
µ
I
Quiescent current in inhibit
condition
V
< 0.4V
1.1
mA
µA
inh
RCA/INH
I
I
Source current at RC /INH pin
V
V
= 5V
< 0.35V
500
100
RCA
RCB
A
RCA/INH
RCA/INH
A
µ
Source current at RC pin
V
V
= 5V, Inhibit inactive
= 5V, Inhibit active
500
µA
µA
B
RCB
RCB
1
(5) Resistive load used. See Fig. 1.
(6) Defined as the time between the voltage at the input of the current sense reaching the V threshold and the lower DMOS switch begin-
ref
ning to turn off. The voltage at SENSE pin is increased instantaneously from V -10 mV to V +10 mV.
ref
ref
6/11
L6227
Figure 1. Switching rates definition
En or IN
50 %
t
t
IOUT
90 %
10 %
tD(OFF) tOFF
tD(ON) t(ON)
CIRCUIT DESCRIPTION
The L6227 is a dual full bridge IC designed to drive DC or Stepper motors and other inductive loads. Each bridge has
4 power DMOS transistors with a typical R of 0.73 Ohm. Any of the 4 half bridges can be controlled indepen-
DS(ON)
dently by means of the 4 TTL/CMOS compatible inputs IN1 , IN2 , IN1 , IN2 , and 2 enable EN , EN .
A
A
B
B
A
B
External connections are provided so that sensing resistor can be added for constant current chopping application.
A non dissipative current sensing on the supply rails of the high side power DMOSs of each bridge, together
with an Internal Reference and an internal open drain, with a pull down capability of 4mA (typical value) will pull
to GND the ENABLE pin of the bridge under fault conditions, turning OFF all the four PowerMOSs. This ensures
a protection against Short Circuit to GND and between two phases of each of the two independent full bridges.
By using an external R-C on the EN pins, the off time before recovering normal operation conditions after a fault
can be easily programmed, by means of the accurate threshold of the logic inputs. Note that protection against
short to the supply rail is typically provided by the external current control circuitry. The trip point of this protec-
tion is internally set at 2.8A (typ value). For each of the two indipendent bridges a monostable and a comparator
can be used to perform a constant t current control.
off
The L6227 also features an inhibit function to put the device in stand-by mode, reducing the current consump-
tion to 1.1mA typ.
These features makes the L6227 a complete bipolar stepper motor driver, or a Dual DC Motor Driver, that out-
performs the component currently available on the market.
7/11
L6227
mm
MIN. TYP. MAX. MIN. TYP. MAX.
4.320 0.170
inch
DIM.
OUTLINE AND
MECHANICAL DATA
A
A1
A2
B
0.380
0.015
3.300
0.130
0.410 0.460 0.510 0.016 0.018 0.020
1.400 1.520 1.650 0.055 0.060 0.065
0.200 0.250 0.300 0.008 0.010 0.012
31.62 31.75 31.88 1.245 1.250 1.255
B1
c
D
E
7.620
8.260 0.300
0.325
e
2.54
0.100
E1
6.350 6.600 6.860 0.250 0.260 0.270
0.300
7.620
e1
L
3.180
3.430 0.125
0.135
Powerdip 24
M
0° min, 15° max.
E1
A2
A
A1
L
B
B1
e
e1
D
24
1
13
12
c
M
SDIP24L
8/11
L6227
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A
A1
A2
B
2.35
0.10
2.65 0.093
0.30 0.004
2.55
0.104
0.012
0.100
0.0200
0.013
0.614
0.299
0.33
0.23
0.51 0.013
0.32 0.009
15.60 0.598
7.60 0.291
C
D
E
15.20
7.40
e
1.27
0,050
H
h
10.0
0.25
10.65 0.394
0.75 0.010
0.419
0.030
k
0° (min.), 8° (max.)
1.27 0.016
SO24
L
0.40
0.050
h x 45°
A1
K
B
D
e
A1
L
C
0.10mm
.004
H
Seating Plane
24
1
13
12
SO24
9/11
L6227
mm
inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
OUTLINE AND
MECHANICAL DATA
A
a1
a2
a3
b
3.60
0.141
0.012
0.130
0.004
0.015
0.012
0.630
0.385
0.570
0.10
0.30 0.004
3.30
0
0.10
0
0.22
0.23
0.38 0.008
0.32 0.009
16.00 0.622
9.80 0.370
14.50 0.547
c
D (1) 15.80
D1
E
9.40
13.90
e
0.65
0.0256
0.435
e3
11.05
E1 (1) 10.90
E2
11.10 0.429
2.90
0.437
0.114
0.244
0.126
0.004
0.626
0.043
0.043
E3
E4
G
H
5.80
2.90
0
6.20 0.228
3.20 0.114
0.10
0
15.50
15.90 0.610
1.10
h
L
0.80
1.10 0.031
10°(max.)
8 °(max.)
N
S
PowerSO36
(1): ”D” and ”E1” do not include mold flash or protrusions
- Mold flash or protrusionsshall not exceed0.15mm(0.006 inch)
- Criticaldimensionsare ”a3”, ”E” and ”G”.
N
N
a2
A
c
a1
e
A
DETAIL B
lead
E
DETAIL A
e3
H
DETAIL A
D
slug
a3
BOTTOM VIEW
36
19
E3
B
E1
E2
D1
DETAIL B
0.35
Gage Plane
- C -
SEATING PLANE
1
1
8
S
L
G
C
M
b
0.12
A B
PSO36MEC
h x 45°
(COPLANARITY)
10/11
L6227
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights ofthird partieswhich may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - All Rights Reserved
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11/11
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