L6227Q_09 [STMICROELECTRONICS]
DMOS dual full bridge driver with PWM current controller; 与PWM电流控制器双DMOS全桥驱动器
| 型号： | L6227Q_09 |
| 厂家： | 
ST |
| 描述： | DMOS dual full bridge driver with PWM current controller |
| 文件： | 总27页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6227Q
DMOS dual full bridge driver
with PWM current controller
Features
■ Operating supply voltage from 8 to 52 V
■ 2.8 A output peak current (1.4 A DC)
■ R
0.73 Ω typ. value @ TJ = 25 °C
DS(on)
■ Operating frequency up to 100 kHz
■ Non dissipative overcurrent protection
VFQFPN32 5 mm x 5 mm
■ Dual independent constant t
PWM current
OFF
Description
controllers
■ Slow decay synchronous rectification
■ Cross conduction protection
■ Thermal shutdown
The L6227Q is a DMOS dual full bridge designed
for motor control applications, realized in
BCDmultipower technology, which combines
isolated DMOS power transistors with CMOS and
bipolar circuits on the same chip. The device also
includes two independent constant off time PWM
current controllers that performs the chopping
regulation. Available in VQFPN32 5 mm x 5 mm
package, the L6227Q features a non-dissipative
overcurrent protection on the high side power
MOSFETs and thermal shutdown.
■ Under voltage lockout
■ Integrated fast free wheeling diodes
Applications
■ Bipolar stepper motor
■ Dual or quad DC motor
Figure 1.
Block diagram
VBOOT
VCP
VBOOT
VSA
VBOOT
VBOOT
CHARGE
PUMP
OVER
CURRENT
DETECTION
OCDA
OUT1A
OUT2A
10V
10V
THERMAL
PROTECTION
ENA
IN1A
IN2A
GATE
LOGIC
SENSEA
PWM
VOLTAGE
REGULATOR
+
-
ONE SHOT
MONOSTABLE
MASKING
TIME
VREFA
RCA
SENSE
COMPARATOR
10V
5V
BRIDGE A
V
SB
OVER
OUT1B
OUT2B
SENSEB
VREFB
RCB
CURRENT
DETECTION
OCDB
GATE
LOGIC
ENB
IN1B
IN2B
BRIDGE B
D99IN1085A
January 2009
Rev 3
1/27
www.st.com
27
Contents
L6227Q
Contents
1
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
1.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
3
4
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output current capability and IC power dissipation . . . . . . . . . . . . . . 21
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
7
8
9
10
2/27
L6227Q
Electrical data
1
Electrical data
1.1
Absolute maximum ratings
Table 1.
Absolute maximum ratings
Parameter
Symbol
Parameter
Value
Unit
VS
Supply voltage
V
=
=
VSB = VS
60
V
SA
SA
Differential voltage between
V
V
VSB = VS = 60 V;
VOD
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
60
V
= VSENSEB = GND
SENSEA
VBOOT
Bootstrap peak voltage
V
=
VSB = VS
VS + 10
V
SA
VIN,VEN
Input and enable voltage range
-0.3 to +7
-0.3 to +7
-0.3 to +7
-1 to +4
V
V
V
V
Voltage range at pins VREFA and
VREFB
VREFA, VREFB
VRCA, VRCB Voltage range at pins RCA and RCB
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and
SENSEB
Pulsed supply current (for each VS
pin), internally limited by the
overcurrent protection
V
=
VSB = VS;
SA
IS(peak)
3.55
A
tPULSE < 1 ms
IS
RMS supply current (for each VS pin)
V
=
VSB = VS
1.4
A
SA
Storage and operating temperature
range
Tstg, TOP
-40 to 150
°C
1.2
Recommended operating conditions
Table 2.
Symbol
Recommended operating conditions
Parameter
Supply voltage
Parameter
Min
Max
Unit
VS
V
=
=
VSB = VS
8
52
V
SA
SA
Differential voltage between
V
V
VSB = VS;
VOD
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
52
V
V
= V
SENSEB
SENSEA
Voltage range at pins VREFA and
VREFB
VREFA, VREFB
-0.1
5
(pulsed tW < trr)
(DC)
-6
-1
6
1
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and
SENSEB
V
V
IOUT
TJ
RMS output current
1.4
+125
100
A
Operating junction temperature
Switching frequency
-25
°C
fsw
kHz
3/27
Electrical data
L6227Q
1.3
Thermal data
Table 3.
Symbol
Thermal data
Parameter
Thermal resistance junction-ambient max (1)
Value
Unit
Rth(JA)
.
42
°C/W
1. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6
cm2 ground layer connected through 18 via holes (9 below the IC).
4/27
L6227Q
Pin connection
2
Pin connection
Figure 2.
Pin connection (top view)
Note:
1
2
The pins 2 to 8 are connected to die PAD
The die PAD must be connected to GND pin
5/27
Pin connection
L6227Q
Table 4.
N°
Pin description
Pin
Type
Function
1, 21
9
GND
GND
Signal ground terminals.
OUT1B
Power output Bridge B output 1.
RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-time of the bridge B.
11
12
RCB
RC pin
Bridge B source pin. This pin must be connected to power ground through a
sensing power resistor.
SENSEB Power supply
13
14
IN1B
IN2B
Logic input Bridge B input 1
Logic input Bridge B input 2
Bridge B current controller reference voltage.
Do not leave this pin open or connect to GND.
15
VREFB
Analog input
Bridge B enable. LOW logic level switches OFF all power MOSFETs of bridge
B. This pin is also connected to the collector of the overcurrent and thermal
protection transistor to implement over current protection.
16
ENB
Logic input (1)
If not used, it has to be connected to +5 V through a resistor.
Supply
voltage
Bootstrap voltage needed for driving the upper power MOSFETs of both
bridge A and Bridge B.
17
19
20
VBOOT
OUT2B
VSB
Power output Bridge B output 2.
Bridge B power supply voltage. It must be connected to the supply voltage
together with pin VSA.
Powersupply
Power supply
Bridge A power supply voltage. It must be connected to the supply voltage
together with pin VSB.
22
VSA
23
24
OUT2A
VCP
Power output Bridge A output 2.
Output
Charge pump oscillator output.
Bridge A enable. LOW logic level switches OFF all power MOSFETs of bridge
A. This pin is also connected to the collector of the overcurrent and thermal
protection transistor to implement over current protection.
25
ENA
Logic input (1)
If not used, it has to be connected to +5 V through a resistor.
Bridge A current controller reference voltage.
Do not leave this pin open or connect to GND.
26
VREFA
Analog input
27
28
IN1A
IN2A
Logic input Bridge A logic input 1.
Logic input Bridge A logic input 2.
Bridge A source pin. This pin must be connected to power ground through a
sensing power resistor.
29
SENSEA Power supply
RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-time of the bridge A.
30
31
RCA
RC pin
OUT1A
Power output Bridge A output 1.
1. Also connected at the output drain of the over current and thermal protection MOSFET. Therefore, it has to be driven
putting in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100 kΩ.
6/27
L6227Q
Electrical characteristics
3
Electrical characteristics
Table 5.
Symbol
Electrical characteristics (T = 25 °C, Vs = 48 V, unless otherwise specified)
A
Parameter
Test condition
Min Typ Max Unit
VSth(ON) Turn-on threshold
VSth(OFF) Turn-off threshold
5.8
5
6.3
5.5
6.8
6
V
V
All Bridges OFF;
TJ = -25 °C to 125 °C (1)
IS
Quiescent supply current
Thermal shutdown temperature
5
10
mA
TJ(OFF)
165
°C
Output DMOS transistors
TJ = 25 °C
TJ =125 ° C (1)
1.47 1.69
2.35 2.7
2
Ω
Ω
High-side + low-side switch ON
resistance
R
DS(on)
IDSS
EN = Low; OUT = VS
EN = Low; OUT = GND
mA
mA
Leakage current
-0.3
Source drain diodes
VSD
trr
Forward ON voltage
ISD = 1.4 A, EN = LOW
If = 1.4 A
1.15 1.3
300
V
Reverse recovery time
Forward recovery time
ns
ns
tfr
200
Logic input
VIL
VIH
Low level logic input voltage
High level logic input voltage
Low level logic input current
High level logic input current
Turn-on input threshold
-0.3
2
0.8
7
V
V
IIL
GND logic input voltage
7 V logic input voltage
-10
µA
µA
V
IIH
10
Vth(ON)
Vth(OFF)
Vth(HYS)
1.8
1.3
2.0
Turn-off input threshold
0.8
V
Input threshold hysteresis
0.25 0.5
V
Switching characteristics
tD(on)EN
Enable to out turn ON delay time (2)
ILOAD =1.4 A, resistive load
500
1.9
40
800
250
ns
µs
ILOAD =1.4 A, resistive load
(dead time included)
tD(on)IN
Input to out turn ON delay time
tRISE
tD(off)EN
tD(off)IN
tFALL
tdt
Output rise time(2)
ILOAD =1.4 A, resistive load
ILOAD =1.4 A, resistive load
ILOAD =1.4 A, resistive load
ILOAD =1.4 A, resistive load
ns
ns
Enable to out turn OFF delay time (2)
Input to out turn OFF delay time
Output fall time (2)
500 800 1000
500 800 1000
ns
40
250
ns
Dead time protection
0.5
1
µs
fCP
Charge pump frequency
-25 °C < TJ < 125 °C
0.6
1
MHz
7/27
Electrical characteristics
L6227Q
Table 5.
Symbol
Electrical characteristics (continued) (T = 25 °C, Vs = 48 V, unless otherwise specified)
A
Parameter
Test condition
Min Typ Max Unit
PWM comparator and monostable
IRCA, RCB
Voffset
tPROP
tBLANK
tON(MIN)
I
Source current at pins RCA and RCB
Offset voltage on sense comparator
Turn OFF propagation delay (3)
Internal blanking time on SENSE pins
Minimum on time
VRCA = VRCB = 2.5 V
VREFA, VREFB = 0.5 V
3.5
5.5
5
mA
mV
ns
500
1
µs
2.5
13
61
3
µs
R
OFF = 20 kΩ; COFF = 1 nF
OFF = 100 kΩ; COFF = 1 nF
µs
tOFF
PWM recirculation time
R
µs
Input bias current at pins VREFA and
VREFB
IBIAS
10
µA
Over current protection
Input supply overcurrent protection
ISOVER
TJ = -25 °C to 125 °C (1)
2.8
A
threshold
ROPDR
Open drain ON resistance
I = 4 mA
40
60
Ω
ns
ns
tOCD(ON) OCD turn-on delay time (4)
tOCD(OFF) OCD turn-off delay time (4)
I = 4 mA; CEN < 100 pF
I = 4 mA; CEN < 100 pF
200
100
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See Figure 3 on page 9
3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
4. See Figure 4 on page 9
8/27
L6227Q
Electrical characteristics
Figure 3.
Switching characteristic definition
EN
Vth(ON)
Vth(OFF)
t
IOUT
90%
10%
t
D01IN1316
tFALL
tRISE
tD(OFF)EN
tD(ON)EN
Figure 4.
Overcurrent detection timing definition
I
OUT
I
SOVER
ON
BRIDGE
OFF
V
EN
90%
10%
D02IN1399
t
t
OCD(OFF)
OCD(ON)
9/27
Circuit description
L6227Q
4
Circuit description
4.1
Power stages and charge pump
The L6227Q integrates two independent power MOS Full Bridges. Each power MOS has an
R
= 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode. Cross
DS(on)
conduction protection is achieved using a dead time (td = 1 µs typical) between the switch
off and switch on of two power MOS in one leg of a bridge.
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped (VBOOT) supply is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown
in Table 6.
Table 6.
Charge pump external components values
Component
Value
CBOOT
CP
220 nF
10 nF
D1
1N4148
1N4148
D2
Figure 5.
Charge pump circuit
VS
D1
D2
CBOOT
CP
D01IN1328
VCP
VBOOT
VS VS
A B
10/27
L6227Q
Circuit description
4.2
Logic inputs
Pins IN1 , IN2 , IN1 and IN2 are TTL/CMOS and microcontroller compatible logic inputs.
A
B
B
B
The internal structure is shown in Figure 6. Typical value for turn-on and turn-off thresholds
are respectively Vthon = 1.8 V and Vthoff = 1.3 V.
Pins EN and EN have identical input structure with the exception that the drains of the
A
B
Overcurrent and thermal protection MOSFETs (one for the bridge A and one for the
bridge B) are also connected to these pins. Due to these connections some care needs to
be taken in driving these pins. The EN and EN inputs may be driven in one of two
A
B
configurations as shown in Figure 7 or Figure 8. If driven by an open drain (collector)
structure, a pull-up resistor R and a capacitor C are connected as shown in Figure 7. If
EN
EN
the driver is a standard push-pull structure the resistor REN and the capacitor CEN are
connected as shown in Figure 8. The resistor REN should be chosen in the range from
2.2 kΩto 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩand 5.6 nF.
More information on selecting the values is found in the overcurrent protection section.
Figure 6.
Logic inputs internal structure
5V
ESD
PROTECTION
D01IN1329
Figure 7.
ENA and ENB pins open collector driving
5V
5V
REN
OPEN
COLLECTOR
OUTPUT
EN
CEN
ESD
PROTECTION
D01IN1330
Figure 8.
ENA and ENB pins push-pull driving
5V
REN
EN
PUSH-PULL
OUTPUT
CEN
ESD
PROTECTION
D01IN1331
11/27
Circuit description
L6227Q
4.3
Truth table
Table 7.
Truth table
Inputs
Outputs
Description (1)
EN
IN1
IN2
OUT1
OUT2
L
X (2)
L
X
L
High Z (3)
GND
High Z
GND
Disable
H
H
H
H
Brake mode (lower path)
Forward
H
L
Vs
GND (Vs)
L
H
H
GND (Vs) (4)
Vs
Vs
Reverse
H
Vs
Brake mode (upper path)
1. Valid only in case of load connected between OUT1 and OUT2
2. X = don't care
3. High Z = high impedance output
4. GND (Vs) = GND during Ton, Vs during Toff
4.4
PWM current control
The L6227Q includes a constant off time PWM current controller for each of the two bridges.
The current control circuit senses the bridge current by sensing the voltage drop across an
external sense resistor connected between the source of the two lower power MOS
transistors and ground, as shown in Figure 9. As the current in the load builds up the voltage
across the sense resistor increases proportionally. When the voltage drop across the sense
resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the
sense comparator triggers the monostable switching the low-side MOS off. The low-side
MOS remain off for the time set by the monostable and the motor current recirculates in the
upper path. When the monostable times out the bridge will again turn on. Since the internal
dead time, used to prevent cross conduction in the bridge, delays the turn on of the power
MOS, the effective off time is the sum of the monostable time plus the dead time.
Figure 9.
PWM current controller simplified schematic
12/27
L6227Q
Circuit description
Figure 10 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the RC pin voltage and the status of the bridge. Immediately
after the low-side power MOS turns on, a high peak current flows through the sensing
resistor due to the reverse recovery of the freewheeling diodes. The L6227Q provides a 1 µs
blanking time tBLANK that inhibits the comparator output so that this current spike cannot
prematurely re-trigger the monostable.
Figure 10. Output current regulation waveforms
I
OUT
V
REF
R
SENSE
t
t
t
OFF
OFF
ON
1µs t
1µs t
BLANK
V
BLANK
SENSE
V
REF
Slow Decay
Slow Decay
0
t
t
V
RC
RCRISE
RCRISE
5V
2.5V
t
t
RCFALL
RCFALL
1µs t
1µs t
DT
DT
ON
SYNCHRONOUS OR QUASI
SYNCHRONOUS RECTIFICATION
OFF
B
C
D
A
B
C
D
D01IN1334
Figure 11 shows the magnitude of the off time t
versus C
and R
values. It can be
OFF
OFF
OFF
approximately calculated from the equations:
t
t
= 0.6 · R
· C
RCFALL
OFF OFF
= t
+ t = 0.6 · R
· C
+ t
OFF DT
OFF
RCFALL
DT
OFF
where R
and C
are the external component values and t is the internally generated
OFF DT
OFF
Dead Time with:
20 kΩ ≤R
0.47 nF ≤C
≤100 kΩ
≤100 nF
OFF
OFF
t
= 1 µs (typical value)
DT
Therefore:
t
t
= 6.6 µs
= 6 ms
OFF(MIN)
OFF(MAX)
13/27
Circuit description
These values allow a sufficient range of t
L6227Q
to implement the drive circuit for most motors.
OFF
The capacitor value chosen for C
also affects the rise time t
of the voltage at the
RCRISE
OFF
pin R
. The rise time t
will only be an issue if the capacitor is not completely
COFF
RCRISE
charged before the next time the monostable is triggered. Therefore, the on time t , which
ON
depends by motors and supply parameters, has to be bigger than t
for allowing a
RCRISE
good current regulation by the PWM stage. Furthermore, the on time t can not be smaller
ON
than the minimum on time t
.
ON(MIN)
t
t
ON >tON(MIN) = 2.5µs
ON >tTCRISE – tDT
⎧
⎨
⎩
t
= 600 · C
OFF
RCRISE
Figure 12 on page 15 shows the lower limit for the on time t for having a good PWM
ON
current regulation capacity. It has to be said that tON is always bigger than t
because
ON(MIN)
the device imposes this condition, but it can be smaller than t
- t . In this last case
RCRISE DT
the device continues to work but the off time t
is not more constant.
OFF
So, small C
value gives more flexibility for the applications (allows smaller on time and,
OFF
therefore, higher switching frequency), but, the smaller is the value for C , the more
OFF
influential will be the noises on the circuit performance.
Figure 11. t
versus C
and R
OFF
OFF OFF
4
.
1 10
= 100kΩ
Roff
3
.
1 10
= 47k
Ω
Roff
= 20k
Ω
Roff
100
10
1
0.1
1
10
100
Coff [nF]
14/27
L6227Q
Circuit description
Figure 12. Area where t can vary maintaining the PWM regulation
ON
100
10
1
1.5µs (typ. value)
0.1
1
10
100
Coff [nF]
4.5
Slow decay mode
Figure 13 shows the operation of the bridge in the slow decay mode. At the start of the off
time, the lower power MOS is switched off and the current recirculates around the upper half
of the bridge. Since the voltage across the coil is low, the current decays slowly. After the
dead time the upper power MOS is operated in the synchronous rectification mode. When
the monostable times out, the lower power MOS is turned on again after some delay set by
the dead time to prevent cross conduction.
Figure 13. Slow decay mode output stage configurations
15/27
Circuit description
L6227Q
4.6
Non-dissipative overcurrent protection
The L6227Q integrates an overcurrent detection circuit (OCD). This circuit provides
protection against a short circuit to ground or between two phases of the bridge. With this
internal over current detection, the external current sense resistor normally used and its
associated power dissipation are eliminated. Figure 14 shows a simplified schematic of the
overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current I . When the
REF
output current in one bridge reaches the detection threshold (typically 2.8 A) the relative
OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is
pulled below the turn off threshold (1.3 V typical) by an internal open drain MOS with a pull
down capability of 4 mA. By using an external R-C on the EN pin, the off time before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs.
Figure 14. Overcurrent protection simplified schematic
OUT1A VSA OUT2A
POWER SENSE
1 cell
HIGH SIDE DMOSs OF
THE BRIDGE A
I1A
I2A
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
TO GATE
LOGIC
+
µC or LOGIC
I1A / n
I2A / n
OCD
COMPARATOR
VDD
(I1A+I2A) / n
IREF
REN
CEN
.
.
EN
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
OVER TEMPERATURE
FROM THE
BRIDGE B
OCD
COMPARATOR
D01IN1337
Figure 15 shows the overcurrent detection operation. The disable time t
before
DISABLE
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by C and R values and its
EN
EN
magnitude is reported in Figure 16. The delay time t
before turning off the bridge when
DELAY
an overcurrent has been detected depends only by C value. Its magnitude is reported in
EN
Figure 17.
C
is also used for providing immunity to pin EN against fast transient noises. Therefore
EN
the value of C should be chosen as big as possible according to the maximum tolerable
EN
delay time and the R value should be chosen according to the desired disable time.
EN
The resistor R should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
EN
values for R and C are respectively 100 kΩ and 5.6 nF that allow obtaining 200 µs
EN
EN
disable time.
16/27
L6227Q
Circuit description
Figure 15. Overcurrent protection waveforms
I
OUT
I
SOVER
V
EN
V
DD
V
th(ON)
V
th(OFF)
V
EN(LOW)
ON
OCD
OFF
ON
BRIDGE
OFF
t
t
DELAY
DISABLE
t
t
t
t
t
OCD(ON)
EN(FALL)
OCD(OFF)
EN(RISE)
D(ON)EN
D02IN1400
t
D(OFF)EN
Figure 16. t
versus C and R (V = 5 V)
EN EN DD
DISABLE
Ω
Ω
R EN = 220 k
R EN = 100 k
3
.
Ω
Ω
R EN = 47 k
R EN = 33 k
1 10
Ω
R EN = 10 k
100
10
1
1
10
100
C E N [nF]
17/27
Circuit description
Figure 17. t
L6227Q
versus C (V = 5 V)
DELAY
EN
DD
10
1
0.1
1
10
100
Cen [nF]
4.7
Thermal protection
In addition to the ovecurrent protection, the L6227Q integrates a thermal protection for
preventing the device destruction in case of junction over temperature. It works sensing the
die temperature by means of a sensible element integrated in the die. The device switch-off
when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ.
value).
18/27
L6227Q
Application information
5
Application information
A typical application using L6227Q is shown in Figure 18. Typical component values for the
application are shown in Table 8. A high quality ceramic capacitor in the range of 100 to
200 nF should be placed between the power pins (VS and VS ) and ground near the
A
B
L6227Q to improve the high frequency filtering on the power supply and reduce high
frequency transients generated by the switching. The capacitors connected from the EN
A
and EN inputs to ground set the shut down time for the bridge A and bridge B respectively
B
when an over current is detected (see overcurrent protection). The two current sensing
inputs (SENSE and SENSE ) should be connected to the sensing resistors with a trace
A
B
length as short as possible in the layout. The sense resistors should be non-inductive
resistors to minimize the dI/dt transients across the resistor. To increase noise immunity,
unused logic pins (except EN and EN ) are best connected to 5 V (high logic level) or GND
A
B
(low logic level) (see pin description). It is recommended to keep power ground and signal
ground separated on PCB.
Table 8.
Component values for typical application
Component
Value
C1
C2
100 µF
100 nF
1 nF
CA
CB
1 nF
CBOOT
CP
220 nF
10 nF
5.6 nF
5.6 nF
68 nF
68 nF
1N4148
1N4148
39 kΩ
39 kΩ
100 kΩ
100 kΩ
0.6 Ω
CENA
CENB
CREFA
CREFB
D1
D2
RA
RB
RENA
RENB
RSENSEA
RSENSEB
0.6 Ω
19/27
Application information
Figure 18. Typical application
L6227Q
Note:
To reduce the IC thermal resistance, therefore improve the dissipation path, the NC pins can
be connected to GND.
20/27
L6227Q
Output current capability and IC power dissipation
6
Output current capability and IC power dissipation
In Figure 19 and Figure 20 are shown the approximate relation between the output current
and the IC power dissipation using PWM current control driving two loads, for two different
driving types:
–
One full bridge ON at a time (Figure 19) in which only one load at a time is
energized.
–
Two full bridges ON at the same time (Figure 20) in which two loads at the same
time are energized.
For a given output current and driving type the power dissipated by the IC can be easily
evaluated, in order to establish which package should be used and how large must be the
on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).
Figure 19. IC power dissipation vs output current with one full bridge ON at a time
ONE FULL BRIDGE ON AT A TIME
10
IA
IOUT
8
IB
6
PD [W]
IOUT
4
2
0
Test Conditions:
Supply Voltage = 24V
No PWM
0 0.25 0.5 0.75 1 1.25 1.5
fSW = 30 kHz (slow decay)
IOUT [A]
Figure 20. IC power dissipation versus output current with two full bridges ON at the
same time
TWO FULL BRIDGES ON AT THE SAME TIME
10
IA
IOUT
8
IB
6
IOUT
PD [W]
4
2
0
Test Conditions:
Supply Voltage =24V
No PWM
fSW = 30kHz (slow decay)
0 0.25 0.5 0.75 1 1.25 1.5
IOUT [A]
21/27
Thermal management
L6227Q
7
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it has to
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness. For instance, using a VFQFPN32L
5x5 package the typical Rth(JA) is about 42 °C/W when mounted on a double-layer FR4
2
2
PCB with a dissipating copper surface of 0.5 cm on the top side plus 6 cm ground layer
connected through 18 via holes (9 below the IC).
22/27
L6227Q
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 9.
VFQFPN32 5x5x1.0 pitch 0.50
Dim.
Databook (mm)
Typ
Min
Max
A
b
0.80
0.18
0.165
4.85
3.00
1.10
4.85
4.20
0.60
0.85
0.25
0.175
5.00
3.10
1.20
5.00
4.30
0.70
0.50
0.40
0.95
0.30
0.185
5.15
3.20
1.30
5.15
4.40
0.80
b1
D
D2
D3
E
E2
E3
e
L
0.30
0.50
0.08
ddd
Note:
1
2
VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no
lead. Very thin profile: 0.80 < A = 1.00 mm.
Details of terminal 1 are optional but must be located on the top surface of the package by
using either a mold or marked features.
23/27
Package mechanical data
Figure 21. Package dimensions
L6227Q
24/27
L6227Q
Order codes
9
Order codes
Table 10. Order code
Order code
Package
Packaging
Tube
L6227Q
VFQFPN32 5 x 5 x 1.0 mm
25/27
Revision history
L6227Q
10
Revision history
Table 11. Document revision history
Date
Revision
Changes
07-Dec-2007
1
First release
Updated: Figure 18 on page 20
Added: Note 1 on page 4
10-Jun-2008
28-Jan-2009
2
3
Updated value in Table 3: Thermal data on page 4
26/27
L6227Q
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