L6392AN [STMICROELECTRONICS]
SWITCHING CONTROLLER, 260kHz SWITCHING FREQ-MAX, PDIP16, ROHS COMPLIANT, DIP-16;
| 型号： | L6392AN |
| 厂家： | 
ST |
| 描述： | SWITCHING CONTROLLER, 260kHz SWITCHING FREQ-MAX, PDIP16, ROHS COMPLIANT, DIP-16 驱动器 |
| 文件： | 总19页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6392
High-voltage high and low side driver
Preliminary Data
Features
■ High voltage rail up to 600 V
■ dV/dt immunity ꢀ0 V/nsec in full temperature
range
■ Driver current capability:
– 270 mA source
DIP-14
SO-14
– 430 mA sink
■ Switching times 7ꢀ/3ꢀ nsec rise/fall with 1 nF
Description
load
■ 3.3 V, ꢀ V TTL/CMOS inputs with hysteresis
■ Integrated bootstrap diode
The L6392 is a high-voltage device, manufactured
with the BCD “OFF-LINE" technology. It has a
monolitich half-bridge gate driver for N-channel
Power MOSFET or IGBT.
■ Operational amplifier for advanced current
sensing
The high side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
of interfacing microcont roller/DSP
■ Adjustable dead-time
■ Interlocking function
■ Compact and simplified layout
■ Bill of material reduction
■ Flexible, easy and fast design
The IC embeds an op amp suitable for advanced
current sensing in applications such as field
oriented motor control.
Application
Table 1.
Device summary
Order codes
Package
Packaging
L6392
L6392D
DIP-14
SO-14
SO-14
Tube
Tube
L6392D013TR
Tape and reel
March 2008
Rev 2
1/19
This is preliminary information on a new product now in development or undergoing evaluation.
Details are subject to change without notice.
www.st.com
19
Contents
L6392
Contents
1
2
3
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
4.2
4.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ꢀ.1
ꢀ.2
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
7
8
Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.1
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10
2/19
L6392
Block diagram
1
Block diagram
Figure 1.
Block diagram
BOOTSTRAP DRIVER
FLOATING STRUCTURE
VCC
BOOT
HVG
4
14
13
from LVG
UV
DETECTION
UV
DETECTION
HVG
DRIVER
S
R
HIN
3
LEVEL
SHIFTER
LOGIC
5V
SHOOT
THROUGH
PREVENTION
OUT
LVG
12
10
LIN
SD
1
VCC
LVG
DRIVER
2
7
5
GND
DT
DEAD
TIME
VCC
OP+
OP-
8
9
OPAMP
OPOUT
+
-
6
3/19
Pin connection
L6392
2
Pin connection
Figure 2.
Pins connection (top view)
1
2
3
4
5
6
7
14
13
LIN
SD
BOOT
HVG
OUT
NC
12
11
10
9
HIN
VCC
LVG
OP-
DT
OPOUT
GND
8
OP+
Table 2.
Pin description
Pin N#
Pin name
Type
Function
1
2
LIN
SD (1)
HIN
I
I
Low side driver logic input (active low)
Shut down logic input (active low)
High side driver logic input (active high)
Lower section supply voltage
Dead time setting
3
I
4
VCC
P
I
ꢀ
DT
6
OPOUT
GND
OP+
O
P
I
Opamp output
7
Ground
8
Opamp non inverting input
Opamp inverting input
9
OP-
I
10
11
12
13
14
LVG (1)
O
Low side driver output
NC
Not connected
OUT
P
O
P
High side (floating) common voltage
High side driver output
HVG (1)
BOOT
Bootstrapped supply voltage
1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This
allows to omitting the "bleeder" resistor connected between the gate and the source of the external
MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/19
L6392
Truth table
3
Truth table
Table 3.
Truth table
Inputs
LIN
Outputs
SD
HIN
LVG
HVG
L
H
H
H
H
X
L
X
L
L
H
L
L
L
L
L
L
L
H
L
H
L
H
H
H
Note:
X: don’t care
ꢀ/19
Electrical data
L6392
4
Electrical data
4.1
Absolute maximum ratings
Table 4.
Absolute maximum rating
Symbol
Parameter
Value
Unit
Vout
VCC
Vop+
Vop-
Vboot
Vhvg
VIvg
Vi
Output voltage
Vboot -21 to Vboot +0.3
- 0.3 to + 21
-0.3 to VCC +0.3
-0.3 to VCC +0.3
VCC - 0.3 to 620
Vout - 0.3 to Vboot + 0.3
-0.3 to VCC + 0.3
-0.3 to 1ꢀ
V
V
Supply voltage
Opamp non-inverting input
Opamp inverting input
Floating supply voltage
High side gate output voltage
Low side gate output voltage
Logic input voltage
V
V
V
V
V
V
dVout/dt Allowed output slew rate
ꢀ0
V/ns
mW
°C
°C
Ptot
TJ
Total power dissipation (TA= 8ꢀ °C)
TBD
Junction temperature
Storage temperature
1ꢀ0
Tstg
-ꢀ0 to 1ꢀ0
Note:
ESD immunity for pins 12, 13 and 14 is guaranteed up to TBD (Human Body Model)
4.2
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Thermal resistance junction to ambient
SO-14
DIP-14
Unit
Rth(JA)
16ꢀ
100
°C/W
4.3
Recommended operating conditions
Table 6.
Symbol Pin
Vout
Recommended operating conditions
Parameter Test condition
Min
Max
Unit
12 Output voltage (1)
14 Floating supply voltage (1)
Switching frequency
ꢀ80
TBD
800
TBD
12ꢀ
V
V
(2)
VBS
TBD
fsw
HVG, LVG load CL = 1nF
kHz
V
VCC
4
Supply voltage
TBD
-40
T
Junction temperature
°C
J
1. If the condition TBDV< Vboot - Vout < TBD V and Vboot < TBD V are guaranteed, Vout can range from TBD V
to ꢀ80 V.
2. VBS = Vboot -Vout
6/19
L6392
Electrical characteristics
5
Electrical characteristics
5.1
AC operation
Table 7.
Symbol
AC operation electrical characteristics (V = 15V; T =+25 °C)
CC J
Pin
Parameter
Test condition
Min
Typ
Max Unit
High/low side driver turn-
on propagation delay
ton
toff
tsd
12ꢀ
ns
Vout = 0 V
1 vs 10
3 vs 13
Vboot = Vcc
High/low side driver turn-
off propagation delay
CL = 1nF
12ꢀ
12ꢀ
ns
ns
Vi = 0 to 3.3 V
See Figure 3 on page 7
2 vs Shut down to high/low
10, 13 side propagation delay
Delay matching, HS and
LS turn-on/off
MT
40
ns
Rdt=0; CL=1 nF; CDT =100 nF
Rdt=37 kΩ;CL=1 nF;CDT=100 nF
Rdt=136 kΩ;CL=1 nF;CDT=100 nF
Rdt=260 kΩ;CL=1 nF;CDT=100 nF
0.1ꢀ
0.ꢀ
1.ꢀ
2.8
µs
µs
µs
µs
dt
ꢀ
Dead time setting range
Matching dead time
Rdt=0 Ω; CL=1 nF; CDT =100 nF
Rdt=37 kΩ;CL=1 nF;CDT=100 nF
Rdt=136 kΩ;CL=1 nF;CDT=100 nF
Rdt=26 0kΩ;CL=1 nF;CDT=100 nF
60
ns
ns
ns
ns
TBD
TBD
TBD
MDT
tr
tf
Rise time
Fall time
CL = 1 nF
CL = 1 nF
7ꢀ
3ꢀ
ns
ns
10, 13
Figure 3.
Timing characteristics
50%
50%
LIN
tr
tr
tr
tf
tf
tf
90%
90%
90%
90%
10%
10%
10%
10%
10%
10%
LVG
ton
toff
50%
50%
HIN
90%
HVG
ton
toff
50%
50%
SD
90%
LVG/HVG
ton
toff
7/19
Electrical characteristics
L6392
5.2
DC operation
Table 8.
Symbol
DC operation electrical characteristics (V = 15 V;T = +25 °C)
CC J
Pin
Parameter
Test condition
Min
Typ
Max Unit
Low supply voltage section
Vcc_hys
Vcc UV hysteresis
700
1400
11.8
mV
V
Vcc UV turn ON
threshold
Vcc_thON
Vcc UV turn OFF
threshold
Vcc_thOFF
10.4
V
VCC = 10 V
SD = ꢀV; LIN = ꢀV;
HIN = GND;
Undervoltage quiescent
supply current
4
Iqccu
110
150
µA
RDT = 0 Ω;
OP + = GND; OP - = ꢀ V
VCC = 1ꢀ V
SD = ꢀ V; LIN = ꢀ V;
HIN = GND;
Iqcc
Quiescent current
680
1060 µA
RDT = 0 Ω;
OP + = GND; OP - = ꢀ V
Bootstrapped supply voltage section
VBS_hys
VBS UV hysteresis
700
1400
11.6
mV
V
VBS UV turn ON
threshold
VBS_thON
V
BS UV turn OFF
VBS_thOFF
10.2
70
V
threshold
VBS = 10 V
14
SD = ꢀ V; LIN and HIN = ꢀ V;
RDT = 0 Ω;
OP + = GND; OP - = ꢀ V
Undervoltage VBS
quiescent current
IQBSU
110
210
µA
µA
VBS = 1ꢀ V
SD = ꢀ V; LIN and HIN = ꢀ V;
RDT = 0 Ω;
IQBS
VBS quiescent current
150
OP + = GND; OP - = ꢀ V
8/19
L6392
Electrical characteristics
Table 8.
Symbol
DC operation electrical characteristics (V = 15 V;T = +25 °C)
CC J
Pin
Parameter
Test condition
Min
Typ
Max Unit
High voltage leakage
current
ILK
Vhvg = Vout = Vboot = 600 V
10
µA
Bootstrap driver on
resistance (1)
Rdson
LVG ON
120
Ω
Driving buffers section
High/low side source
short circuit current
Iso
Vi= Vih (tp < 10 ms)
Vi= Vil (tp < 10 ms)
270
430
mA
mA
10, 13
High/low side sink short
circuit current
Isi
Logic inputs
Vil
Low level logic threshold
voltage
0.83
V
1, 2, 3
High level logic threshold
voltage
Vih
IHINh
IHINl
ILINh
ILINl
ISDh
ISDl
2.21
V
HIN logic “1” input bias
current
HIN = 1ꢀ V
HIN = 0 V
LIN = 0 V
LIN = 1ꢀ V
SD = 1ꢀ V
SD = 0 V
17ꢀ
6
260
1
µA
µA
µA
µA
µA
µA
3
1
2
HIN logic “0” input bias
current
LIN logic “1” input bias
current
40
1
LIN logic “0” input bias
current
SD logic “1” input bias
current
30
100
1
SD logic “0” input bias
current
1. RDSon is tested in the following way:
DSon = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 16 current when
VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2
R
9/19
Electrical characteristics
L6392
Unit
Table 9.
Symbol
OPAMP characteristics (V = 15 V, T = +25 °C)
CC
J
Pin
Parameter
Test condition
Min
Typ
Max
VO = TBD;
0 < Vicm < VCC -TBD
Vio
Iib
Input offset voltage
3
mV
nA
8, 9 Input bias current (1)
1ꢀ
200
Input common mode voltage
range
VCC -
TBD
Vicm
0
Output voltage swing - low
level
VOL
VOH
Isink = 3.ꢀ mA, RL = 2 kΩ
180
14.3
30
360
mV
V
Output voltage swing - high Isource = 3.ꢀ mA,
level
13.ꢀ
16
RL = 2 kΩ
6
Source,
mA
mA
V/µs
Vid = TBD; Vo = TBD
Io
Output short circuit current
Sink
ꢀ0
80
Vid = TBD; Vo = TBD
Vi = TBD; RL = 2 kΩ;
CL = TBD; unity gain
SR
Slew rate
2.ꢀ
3.8
GBWP
Avd
Gain bandwith product
Vo = TBD; RL = 2 kΩ
TBD
9ꢀ
MHz
dB
Large signal voltage gain
8ꢀ
80
SRV
Power supply rejection ratio vs Vcc
8ꢀ
dB
Common mode rejection
ratio
CMRR
100
dB
1. The direction of input current is out of the IC.
10/19
L6392
6
Waveforms definitions
Waveforms definitions
Figure 4.
Dead time - timing waveforms
LIN
HIN
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
LVG
HVG
DT
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
HIN
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
LVG
HVG
DT
DT
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
HIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
LVG
HVG
DT
DT
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
HIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
LVG
HVG
DT
DT
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(*) HIN and LIN can be connected togheter and driven by just one control signal
11/19
Typical application diagram
L6392
7
Typical application diagram
Figure 5.
Application diagram
BOOTSTRAP DRIVER
FLOATING STRUCTURE
VCC
BOOT
HVG
4
14
13
from LVG
UV
DETECTION
UV
DETECTION
Cboot
H.V.
HVG
DRIVER
S
R
HIN
3
LEVEL
SHIFTER
LOGIC
5V
SHOOT
THROUGH
PREVENTION
OUT
LVG
12
10
LIN
SD
1
TO LOAD
VCC
LVG
DRIVER
2
SD
LATCH
7
5
GND
DT
DEAD
TIME
OPAMP
OP+
OP-
8
9
OPOUT
+
-
6
12/19
L6392
Bootstrap driver
8
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 6 a). In the L6392 a patented
integrated structure replaces the external diode. It is realized by a high voltage DMOS,
driven synchronously with the low side driver (LVG), with diode in series, as shown in
Figure 6 b.
An internal charge pump (Figure 6 b) provides the DMOS driving voltage.
8.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Qgate
CEXT = -------------
Vgate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
C
>>> C
EXT
BOOT
e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also
the leakage and quiescent losses.
e.g.: HVG steady state consumption is lower than 200 µA, so if HVG TON is ꢀ ms, CBOOT has
to supply 1 µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1 V.
The internal bootstrap driver gives agreat advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value:
120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Qgate
------------------
Rdson
Vdrop = IchargeRdson → Vdrop
=
Tcharge
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the
bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor.
13/19
Bootstrap driver
For example: using a power MOS with a total gate charge of 30 nC the drop on the
L6392
bootstrap DMOS is about 1 V, if the Tcharge is ꢀ µs. In fact:
30nC
ꢀµs
--------------
⋅ 120Ω ∼ 0.7V
Vdrop
=
V
drop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 6.
Bootstrap driver
DBOOT
VS
BOOT
H.V.
BOOT
H.V.
VS
HVG
LVG
HVG
LVG
CBOOT
CBOOT
VOUT
VOUT
TO LOAD
TO LOAD
D99IN1067
a
b
14/19
L6392
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
1ꢀ/19
Package mechanical data
Figure 7. DIP-14 mechanical data and package dimensions
L6392
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
a1
B
b
0.ꢀ1
0.020
1.39
1.6ꢀ 0.0ꢀꢀ
0.06ꢀ
0.ꢀ
0.020
0.010
b1
D
E
e
0.2ꢀ
20
0.787
8.ꢀ
2.ꢀ4
1ꢀ.24
0.33ꢀ
0.100
0.600
e3
F
7.1
ꢀ.1
0.280
I
0.201
L
3.3
0.130
Z
1.27
2.ꢀ4 0.0ꢀ0
0.100
16/19
L6392
Package mechanical data
SO-14 mechanical data and package dimensions
Figure 8.
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.069
A
A1
A2
B
1.3ꢀ
0.10
1.10
0.33
0.19
8.ꢀꢀ
1.7ꢀ 0.0ꢀ3
0.30 0.004
1.6ꢀ 0.043
0.ꢀ1 0.013
0.2ꢀ 0.007
8.7ꢀ 0.337
0.012
0.06ꢀ
0.020
C
0.01
(1)
0.344
D
E
e
3.80
4.0
0.1ꢀ0
0.1ꢀ7
0.0ꢀ0
1.27
H
ꢀ.8
6.20 0.228
0.ꢀ0 0.01
0.244
h
0.2ꢀ
0.40
0.02
L
1.27 0.016
0° (min.), 8° (max.)
0.10
0.0ꢀ0
k
ddd
0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.1ꢀmm per side.
0016019 D
17/19
Revision history
L6392
10
Revision history
Table 10. Document revision history
Date
Revision
Changes
29-Feb-2008
18-Mar-2008
1
2
Initial release
Cover page updated
18/19
L6392
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