L6714TR_技术文档

L6714

4 phase controller with embedded drivers

for Intel VR10, VR11 and AMD 6Bit CPUs

Features

■ 0.5% output voltage accuracy

■ 7/8 bit programmable output up to 1.60000V -

Intel VR10.x, VR11 DAC

■ 6 bit programmable output up to 1.5500V -

AMD 6Bit DAC

TQFP64 (Exposed Pad)

■ High current integrated gate drivers

■ Full differential current sensing across inductor

or low side MOSFET

Description

■ Embedded VRD thermal monitor

■ Integrated remote sense buffer

■ Dynamic VID management

■ Adjustable reference voltage offset

■ Programmable Soft-Start

L6714 implements a four phase step-down

controller with 90º phase-shift between each

phase with integrated high current drivers in a

compact 10mm x 10mm body package with

exposed pad.

■ Low-Side-Less startup

The device embeds selectable DACs: the output

voltage ranges up to 1.60000V (both Intel VR10.x

and VR11 DAC) or up to 1.5500V (AMD 6Bit

DAC) managing D-VID with 0.5% output voltage

accuracy over line and temperature variations.

Additional programmable offset can be added to

the reference voltage with a single external

resistor.

■ Programmable over voltage protection

■ Preliminary over voltage

■ Constant over current protection

■ Oscillator internally fixed at 150kHz externally

adjustable

■ Output enable

The controller assures fast protection against load

over current and under / over voltage (in this last

case also before UVLO). In case of over-current

the system works in Constant Current mode until

UVP.

■ SS_END / PGOOD signal

■ TQFP64 10mm x 10mm package

with Exposed Pad

Application

Selectable current reading adds flexibility to the

design allowing current sense across inductor or

LS MOSFET.

■ High current VRD for desktop CPUs

■ Workstation and server CPU power supply

■ VRM modules

System Thermal Monitor is also provided allowing

system protection from over-temperature

conditions.

Order codes

Part number

Package

TQFP64

Packaging

L6714

Tube

L6714TR

TQFP64

Tape and reel

November 2006

Rev 3

1/70

www.st.com

70

Contents

L6714

Contents

1

2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

2.2

Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3

Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1

3.2

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4

5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

VID Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1

5.2

5.3

5.4

5.5

Mapping for the Intel VR11 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Voltage Identification (VID) for Intel VR11 mode . . . . . . . . . . . . . . . . . . . 17

Voltage Identifications (VID) for Intel VR10 mode + 6.25mV . . . . . . . . . . 19

Mapping for the AMD 6BIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Voltage identifications (VID) codes for AMD 6BIT mode . . . . . . . . . . . . . 21

6

7

8

Reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Configuring the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.1

DAC selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9

Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10

Current reading and current sharing loop . . . . . . . . . . . . . . . . . . . . . . 32

10.1 Low side current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.2 Inductor current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11

Remote voltage sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2/70

L6714

Contents

12

Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

12.1 Droop function (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

12.2 Offset (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

13

14

15

Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

15.1 Intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

15.2 AMD mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

15.3 Low-Side-Less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

16

Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 47

16.1 Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

16.2 Preliminary over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

16.3 Over voltage and programmable OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

16.4 PGOOD (Only for AMD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

17

18

Maximum Duty-cycle limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

18.1 Low side MOSFET sense over current . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

18.2 Inductor sense over current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

19

20

21

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

21.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

22

Thermal monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3/70

Contents

L6714

23

Tolerance band (TOB) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

23.1 Controller tolerance (TOB controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

23.2 Ext. current sense circuit tolerance

(TOB CurrSense - Inductor Sense) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

23.3 Time constant matching error tolerance (TOB TCMatching) . . . . . . . . . . 63

23.4 Temperature measurement error (VTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 63

24

Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

24.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

24.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 65

25

26

27

Embedding L6714 - Based VR... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4/70

L6714

Block diagram

1

Block diagram

Figure 1. L6714 block diagram

VR_HOT

VR_FAN

SS_END / PGOOD

HS1

HS2

LS2

HS3

LS3

HS4

LS4

LOGIC PWM

ADAPTIVE ANTI

LOGIC PWM

ADAPTIVE ANTI

LOGIC PWM

ADAPTIVE ANTI

LOGIC PWM

ADAPTIVE ANTI

CROSS CONDUCTION

CURRENT SHARING

CORRECTION

CURRENT SHARING

CORRECTION

CURRENT SHARING

CORRECTION

CURRENT SHARING

CORRECTION

OSC / FAULT

TM

PWM1

PWM2

PWM3

PWM4

SS_OSC / REF

CS_SEL

CS1-

PWM1

PWM2

PWM3

PWM4

DIGITAL

SOFT START

CH1 CURRENT

READING

VCC

OCP1

OCP2

OCP3

OCP4

CS1+

VCCDR

OUTEN

DAC/CS_SEL

L6714

CONTROL LOGIC

AND PROTECTIONS

CS_SEL

OCP1

VID0

VID1

CS2-

CH2 CURRENT

READING

CS2+

VID2

OFFSET CS_SEL

OCP2

VID3

TOTAL DELIVERED CURRENT

VID4

CS3-

CH3 CURRENT

READING

VID5

CS3+

+150mV / 1.800V / OVP

64k

VID6

OCP3

OVP

VID7 / D-VID

COMPARATOR

64k

CS4-

ERROR

AMPLIFIER

CH4 CURRENT

READING

VID_SEL

CS4+

1.240V

REMOTE

BUFFER

64k

OCP4

64k

VCC

SGND

OUTEN

OVP

DAC / CS_SEL

5/70

Pin settings

L6714

2

Pin settings

2.1

Connections

Figure 2. Pin connection (Through top view)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

TM

SGND

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OFFSET

CS1-

VCCDR4

LGATE4

PGND4

PGND2

LGATE2

VCCDR2

VCCDR3

LGATE3

PGND3

PGND1

LGATE1

VCCDR1

PHASE1

N.C.

CS1+

CS3-

CS3+

CS2-

CS2+

CS4-

L6714

CS4+

COMP

FB

DROOP

VSEN

SGND

SSOSC / REF

OUTEN

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

6/70

L6714

Pin settings

2.2

Functions

Table 1.

N°

Pin functions

Function

Channel 1 HS driver output.

1

UGATE1

A small series resistors helps in reducing device-dissipated power.

Channel 1 HS driver supply.

Connect through a capacitor (100nF typ.) to PHASE1 and provide necessary

Bootstrap diode.

2

BOOT1

A small resistor in series to the boot diode helps in reducing Boot capacitor

overcharge.

3

4

N.C.

Not internally connected.

Channel 3 HS driver return path.

PHASE3

It must be connected to the HS3 mosfet source and provides return path for the

HS driver of channel 3.

Channel 3 HS driver output.

5

6

UGATE3

BOOT3

A small series resistors helps in reducing device-dissipated power.

Channel 3 HS driver supply.

Connect through a capacitor (100nF typ.) to PHASE3 and provide necessary

Bootstrap diode.

A small resistor in series to the boot diode helps in reducing Boot capacitor

overcharge.

7

8

N.C.

Not internally connected.

Channel 2 HS driver return path.

PHASE2

It must be connected to the HS2 mosfet source and provides return path for the

HS driver of channel 2.

Channel 2 HS driver output.

9

UGATE2

BOOT2

A small series resistors helps in reducing device-dissipated power.

Channel 2 HS driver supply.

Connect through a capacitor (100nF typ.) to PHASE2 and provide necessary

Bootstrap diode.

10

A small resistor in series to the boot diode helps in reducing Boot capacitor

overcharge.

11

12

N.C.

Not internally connected.

Channel 4 HS driver return path.

PHASE4

It must be connected to the HS4 mosfet source and provides return path for the

HS driver of channel 4.

Channel 4 HS driver output.

13

14

UGATE4

BOOT4

A small series resistors helps in reducing device-dissipated power.

Channel 4 HS driver supply.

Connect through a capacitor (100nF typ.) to PHASE4 and provide necessary

Bootstrap diode.

A small resistor in series to the boot diode helps in reducing Boot capacitor

overcharge.

7/70

Pin settings

L6714

Table 1.

N°

Pin functions

Function

Device supply voltage. The operative voltage is 12V 15%. Filter with 1µF (typ)

MLCC vs. SGND.

15

VCC

DAC and Current Sense SELection Pin.

This pin sources a constant 12.5µA current. By connecting a resistor vs. SGND

it is possible to select between Intel and AMD integrated DACs and Current

Sense methods.

DAC/

CS_SEL

16

Filter with 100pF(max) vs. SGND.

DACs and Current Sense methods cannot be changed dynamically.

See “DAC selection” Section and See Table 10 for details.

OUTput ENable Pin.

Forced low, the device stops operations with all MOSFET OFF: all the

protections are disabled except for Section 16.2: Preliminary over voltage on

page 47.

17

OUTEN

Set free, the device starts-up implementing soft-start up to the selected VID

code.

Cycle this pin to recover latch from protections; filter with 1nF (typ) vs. SGND.

Intel Mode. Soft Start OSCillator Pin.

By connecting a resistor R_SSOSCvs. SGND, it allows programming the frequency

F_SSof an internal additional oscillator that drives the reference during Soft-Start.

Setting this frequency allows programming the Soft-Start time T_SSproportionally

to the R_SSOSCconnected with a gain of 20.1612 [µs / kΩ]. The same slope

implemented to reach V_BOOThas to be considered also when the reference

moves from V_BOOTto the programmed VID code. See “Soft start” Section for

details.

SSOSC/

REF

18

AMD Mode. REFerence Output. Filter with 47Ω - 4.7nF vs. SGND.

All the internal references are referred to this pin. Connect to the PCB Signal

Ground.

19

20

SGND

VSEN

Remote Buffer Output, it manages OVP and UVP protections and PGOOD

(when applicable). See “Output voltage monitor and protections” Section and

See Table 10 for details.

A current proportional to the total current read is sourced from this pin according

to the Current Reading Gain.

Short to FB to implement Droop Function or Short to SGND to disable the

function.Connecting to SGND through a resistor and filtering with a capacitor,

the current info can be used for other purposes.

21

DROOP

See “Droop function (Optional)” Section

Error Amplifier Inverting Input. Connect with a resistor R_FBvs. VSEN and with an

R_F- C_Fvs. COMP.

22

23

FB

Error Amplifier Output. Connect with an R_F- C_Fvs. FB.

The device cannot be disabled by pulling down this pin.

COMP

Channel 4 Current Sense Positive Input.

LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source.

24

CS4+

Inductor DCR Sense: connect through an R-C filter to the phase-side of the

channel 4 inductor.

See “Layout guidelines” Section for proper layout of this connection.

8/70

L6714

Pin settings

Table 1.

N°

Pin functions

Function

Channel 4 Current Sense Negative Input.

LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain.

25

26

27

28

29

30

31

32

CS4-

Inductor DCR Sense: connect through a Rg resistor to the output-side of the

channel 4 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 2 Current Sense Positive Input.

LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source.

CS2+

CS2-

CS3+

CS3-

CS1+

CS1-

Inductor DCR Sense: connect through an R-C filter to the phase-side of the

channel 2 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 2 Current Sense Negative Input.

LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain.

Inductor DCR Sense: connect through a Rg resistor to the output-side of the

channel 2 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 3 Current Sense Positive Input.

LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source.

Inductor DCR Sense: connect through an R-C filter to the phase-side of the

channel 3 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 3 Current Sense Negative Input.

LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain.

Inductor DCR Sense: connect through a Rg resistor to the output-side of the

channel 3 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 1 Current Sense Positive Input.

LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Source.

Inductor DCR Sense: connect through an R-C filter to the phase-side of the

channel 1 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Channel 1 Current Sense Negative Input.

LS Mosfet Sense: connect through a resistor Rg to the LS mosfet Drain.

Inductor DCR Sense: connect through a Rg resistor to the output-side of the

channel 1 inductor.

See “Layout guidelines” Section for proper layout of this connection.

Offset Programming Pin.

Internally fixed at 1.240V, connecting a R_OFFSETresistor vs. SGND allows

OFFSET setting a current that is mirrored into FB pin in order to program a positive offset

according to the selected R_FB. Short to SGND to disable the function.

See “Offset (Optional)” Section for details.

9/70

Pin settings

L6714

Table 1.

N°

Pin functions

Function

Over Voltage Programming Pin. Internally pulled up by 12.5µA(typ) to 5V.

Set free to use built-in protection thresholds as reported into Table 10.

33

34

OVP

Connect to SGND through a R_OVPresistor and filter with 100pF (max) to set the

OVP threshold to a fixed voltage according to the R_OVPresistor.

See “Over voltage and programmable OVP” Section Section for details.

Intel Mode.

It allows selecting between VR10 (short to SGND, Table 7) or VR11

VID_SEL (floating,Table 6 ) DACs ,internally pulled up by 12.5µA (typ.).. See “Configuring

the device” Section for details.

AMD Mode. Not Applicable. Needs to be shorted to SGND.

Remote Buffer Non Inverting Input.

35

36

FBR

FBG

Connect to the positive side of the load to perform remote sense.

See “Layout guidelines” Section for proper layout of this connection.

Remote Buffer Inverting Input.

Connect to the negative side of the load to perform remote sense.

See “Layout guidelines” Section for proper layout of this connection.

Oscillator Pin.

It allows programming the switching frequency F_SWof each channel: the

equivalent switching frequency at the load side results in being multiplied by the

phase number N.

OSC/

FAULT

37

Frequency is programmed according to the resistor connected from the pin vs.

SGND or VCC with a gain of 6kHz/µA (see relevant section for details). Leaving

the pin floating programs a switching frequency of 150kHz per phase.

The pin is forced high (5V) to signal an OVP FAULT: to recover from this

condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details.

VID7 - Intel Mode. See VID5 to VID0 Section.

DVID - AMD Mode. DVID Output.

VID7/

DVID

38

39

CMOS output pulled high when the controller is performing a D-VID transition

(with 32 clock cycle delay after the transition has finished). See “Dynamic VID

transitions” Section Section for details.

Intel Mode. See VID5 to VID0 Section.

AMD Mode. Not Applicable. Need to be shorted to SGND.

VID6

Intel Mode. Voltage IDentification Pins (also applies to VID6, VID7).

Internally pulled up by 25µA to 5V, connect to SGND to program a '0' or leave

floating to program a '1'.

They allow programming output voltage as specified in Table 6 and Table 7

according to VID_SEL status. OVP and UVP protection comes as a

consequence of the programmed code (See Table 10).

40 to

45

VID5 to

VID0

AMD Mode. Voltage IDentification Pins.

Internally pulled down by 12.5µA, leave floating to program a '0' while pull up to

more than 1.4V to program a '1'.

They allow programming the output voltage as specified in Table 9 on page 21

(VID7 doesn’t care). OVP and UVP protection comes as a consequence of the

programmed code (See Table 10).

Note. VID6 not used, need to be shorted to SGND.

10/70

L6714

Pin settings

Table 1.

N°

Pin functions

Function

SSEND - Intel Mode. Soft Start END Signal.

Open Drain Output set free after SS has finished and pulled low when triggering

any protection. Pull up to a voltage lower than 5V (typ), if not used it can be left

floating.

SS_END/

PGOOD

46

PGOOD - AMD Mode.

Open Drain Output set free after SS has finished and pulled low when VSEN is

lower than the relative threshold. Pull up to a voltage lower than 5V (typ), if not

used it can be left floating.

Voltage Regulator HOT. Over Temperature Alarm Signal.

Open Drain Output, set free when TM overcomes the Alarm Threshold.

Thermal Monitoring Output enabled if Vcc > UVLO_VCC.

47

48

VR_HOT

VR_FAN

See “Thermal monitor” Section for details and typical connections.

Voltage Regulator FAN. Over Temperature Warning Signal.

Open Drain Output, set free when TM overcomes the Warning Threshold.

Thermal Monitoring Output enabled if Vcc > UVLO_VCC.

See “Thermal monitor” Section for details and typical connections.

Thermal Monitor Input.

It senses the regulator temperature through apposite network and drives

VR_FAN and VR_HOT accordingly.Short TM pin to SGND if not used.

49

50

51

52

TM

See “Thermal monitor” Section for details and typical connections.

All the internal references are referred to this pin. Connect to the PCB Signal

Ground.

SGND

Channel 4 LS Driver Supply.

It must be connected to others VCCDRx pins.

VCCDR4

LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap

vs. PGND4.

Channel 4 LS Driver Output. A small series resistor helps in reducing device-

dissipated power.

LGATE4

53

54

PGND4 Channel 4 LS Driver return path. Connect to Power ground Plane.

PGND2 Channel 2 LS Driver return path. Connect to Power ground Plane.

Channel 2 LS Driver Output. A small series resistor helps in reducing device-

dissipated power.

55

LGATE2

Channel 2 LS Driver Supply.

It must be connected to others VCCDRx pins.

VCCDR2

56

LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap

vs. PGND2.

Channel 3 LS Driver Supply.

It must be connected to others VCCDRx pins.

VCCDR3

57

LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap

vs. PGND3.

Channel 3 LS Driver Output.A small series resistor helps in reducing device-

dissipated power.

58

59

LGATE3

PGND3 Channel 3 LS Driver return path. Connect to Power ground Plane.

11/70

Pin settings

L6714

Table 1.

N°

Pin functions

PGND1 Channel 1 LS Driver return path. Connect to Power ground Plane.

Function

60

61

Channel 1 LS Driver Output.A small series resistor helps in reducing device-

dissipated power.

LGATE1

Channel 1 LS Driver Supply.

It must be connected to others VCCDRx pins.

62

VCCDR1

LS Driver supply can range from 5Vbus up to 12Vbus, filter with 1µF MLCC cap

vs. PGND1.

Channel 1 HS driver return path.

63

64

PHASE1

N.C.

It must be connected to the HS1 mosfet source and provides return path for the

HS driver of channel 1.

Not internally connected.

Thermal pad connects the Silicon substrate and makes good thermal contact

with the PCB to dissipate the power necessary to drive the external mosfets.

THERMAL

PAD

Connect to the PGND plane with several VIAs to improve thermal conductivity.

12/70

L6714

Electrical data

3

Electrical data

3.1

Maximum rating

Table 2.

Symbol

_CC, V_CCDRxto PGNDx

V_BOOTx

Absolute maximum ratings

Parameter

Value

Unit

V

15

V

-

Boot voltage

15

V

V_PHASEx

V_UGATEx

V_PHASEx

-

15

V

V_CC- V_BOOTx

7.5

LGATEx, PHASEx, to PGNDx

VID0 to VID7, VID_SEL

All other Pins to PGNDx

Static condition

-0.3 to V_CC+ 0.3

-0.3 to 5

V

-0.3 to 7

-7.5

26

V

To PGNDx, VCC=14V, BOOTx=7V,

PHASEx=-7.5V

V_PHASEx

Positive peak voltage to PGNDx;

T < 20ns @ 600kHz

3.2

Thermal data

Table 3.

Symbol

Thermal data

Parameter

Value

Unit

Thermal resistance junction to ambient

(Device soldered on 2s2p PC Board)

R_thJA

40

°C/W

T_MAX

T_STG

T_J

Maximum junction temperature

Storage temperature range

150

-40 to 150

0 to 125

2.5

°C

W

Junction temperature range

P_TOT

Maximum power dissipation at T_A= 25°C

13/70

Electrical characteristics

L6714

4

Electrical characteristics

V

= 12V 15%, T_J= 0°C to 70°C, unless otherwise specified

CC

Table 4.

Electrical characteristics

Parameter

Symbol

Test condition

Min.

Typ. Max. Unit

Supply Current

HGATEx and LGATEx = OPEN

VCCDRx = BOOTx = 12V

I_CC

VCC supply current

17

1

mA

LGATEx = OPEN;

VCCDRx = 12V

I_CCDRx

VCCDRx supply current

BOOTx supply current

HGATEx = OPEN; PHASEx to

PGNDx; VCC = BOOTx = 12V

I_BOOTx

0.75

Power-ON

VCC turn-ON

VCC Rising; VCCDRx = 5V

VCC Falling; VCCDRx = 5V

VCCDRx Rising; VCC = 12V

VCCDRx Falling; VCC = 12V

VCC Rising; VCCDRx = 5V

VCC Falling; VCCDRx = 5V

8.9

7.7

4.5

4.3

3.6

3.3

9.3

4.8

V

UVLO_VCC

UVLO_VCCDR

UVLO_OVP

VCC turn-OFF

7.3

3.9

VCCDR turn-ON

VCCDR turn-OFF

Pre-OVP turn-ON

Pre-OVP turn-OFF

3.85

3.05

Oscillator and Inhibit

OSC = OPEN

135

130

150

500

165

170

F_OSC

Main Oscillator Accuracy

kHz

OSC = OPEN; T_J= 0°C to 125°C

T₁

T₂

T₃

SS Delay Time

SS Time T₂

SS Time T₃

Intel mode

1

ms

µs

V

Intel mode; R_SSOSC= 25kΩ

Intel mode

50

Rising thresholds voltage

Hysteresis

0.80

0.85

100

0.90

0.80

Output enable intel mode

mV

V

OUTEN

Input low

Output enable AMD mode

Pull-up current

Input high

1.40

V

12.5

80

40

4

µA

%

V

OSC = OPEN; I_DROOP= 0µA

OSC = OPEN; I_DROOP= 140µA

d_MAX

Maximum duty cycle

∆V_OSC

PWMx ramp amplitude

Voltage at Pin OSC

FAULT

OVP Active

5

V

14/70

L6714

Electrical characteristics

Table 4.

Electrical characteristics

Parameter

Symbol

Test condition

Min.

Typ. Max. Unit

Reference and DAC

Intel mode

VID = 1.000V to VID = 1.600V

FBR = VOUT; FBG = GNDOUT

-0.5

-

0.5

%

k_VID

Output voltage accuracy

AMD mode

VID=1.000V to VID = 1.550V

FBR = VOUT; FBG = GNDOUT

-0.6

-10

0.6

10

REF

Reference accuracy

Boot voltage

AMD mode; respect VID

Intel mode

-

mV

V

V_BOOT

1.081

25

VID Pull-up current

VID Pull-down current

Intel mode; VIDx to SGND

AMD mode; VIDx to 5.4V

µA

I_VID

12.5

Intel mode; Input Low

AMD mode; Input Low

0.3

0.8

VID_IL

VID_IH

V

VID thresholds

Intel mode; Input High

AMD mode; Input High

0.8

1.35

VID_SEL threshold

(Intel mode)

Input low

0.3

VID_SEL

Input high

0.8

Error amplifier and remote buffer

A₀

EA DC gain

EA slew rate

RB DC gain

80

20

1

dB

V/µs

V/V

SR

COMP = 10pF to SGND

Remote buffer common mode

rejection ratio

CMRR

40

dB

Differential current sensing and offset

LS sense

25

0

I_CSx+

Bias current

µA

Inductor sense

I

– I

Rg = 1kΩ; I_INFOx= 25µA

INFOx AVG

-----------------------------------------

Current sense mismatch

Over current threshold

-3

30

-2

-

35

-

3

40

2

%

µA

I

AVG

I_OCTH

I_CSx-(OCP) - I_CSx-(0)

OFFSET = SGND; Rg = 1kΩ

I_DROOP= 0 to 80µA;

Droop current deviation from

nominal value

k_IDROOP

K_IOFFSET

I_OFFSET

V_OFFSET

Offset current accuracy

OFFSET current range

OFFSET pin bias

I_OFFSET= 50µA to 250µA

-8

0

-

8

%

µA

V

250

I_OFFSET= 0 to 250µA

1.240

15/70

Electrical characteristics

L6714

Table 4.

Symbol

Electrical characteristics

Parameter

Test condition

Min.

Typ. Max. Unit

Gate drivers

t_{RISE_UGATEx}HS rise time

BOOTx - PHASEx = 10V;

15

30

ns

C_UGATExto PHASEx = 3.3nF

I_UGATEx

HS source current

HS sink resistance

BOOTx - PHASEx = 10V

BOOTx - PHASEx = 12V

2

A

R_UGATEx

1.5

2.5

55

Ω

VCCDRx = 10V;

t_{RISE_LGATEx}LS rise time

30

ns

C_LGATExto PGNDx = 5.6nF

I_LGATEx

LS source current

VCCDRx = 10V

VCCDRx = 12V

1.8

1.1

A

R_LGATEx

LS sink resistance

0.7

1.5

Ω

Protections

Intel mode; before V_BOOT

Intel mode; above VID

AMD mode

1.300

200

V

mV

V

Over voltage protection

(VSEN Rising)

OVP

100

150

1.700 1.740 1.780

I_OVPcurrent

OVP = SGND

11.5

-50

12.5

0

13.5

50

µA

mV

Program-

mable OVP

Comparator offset voltage

OVP = 1.8V

UVLO_OVP< VCC < UVLO_VCC

1.800

V

VCC > UVLO_VCC

OUTEN = SGND

&

Preliminary over voltage

protection

Pre-OVP

Hysteresis

350

-750

-300

mV

UVP

Under voltage protection

PGOOD threshold

VSEN falling; below VID

AMD mode;

PGOOD

mV

V

VSEN falling; below VID

SSEND / PGOOD

Voltage low

V_SSEND/

I = -4mA

0.4

PGOOD

Thermal Monitor

TM Warning (VR_FAN)

V_TMrising

3.2

3.6

V

V_TM

TM Alarm (VR_HOT)

TM Hysteresis

100

mV

VR_HOT voltage low;

VR_FAN voltage low

0.4

V

V_{VR_HOT}

V_{VR_FAN}

;

I = -4mA

16/70

L6714

VID Tables

5

VID Tables

5.1

Mapping for the Intel VR11 mode

Table 5.

VID7

Voltage Identification (VID) Mapping for Intel VR11 Mode

VID6

VID5

VID4

VID3

VID2

VID1

VID0

800mV

400mV

200mV

100mV

50mV

25mV

12.5mV

6.25mV

5.2

Voltage Identification (VID) for Intel VR11 mode

Table 6.

Voltage Identification (VID) for Intel VR11 mode (See Note).

Output Output Output

Output

HEX Code voltage HEX Code voltage HEX Code voltage HEX Code voltage

(1)

(

1)

(

1)

(1)

0

1

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

OFF

4

5

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

1.07500

8

9

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

C

D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

0.41250

0.40625

0.40000

0.39375

0.38750

0.38125

0.37500

0.36875

0.36250

0.35625

0.35000

0.34375

0.33750

0.33125

0.32500

0.31875

0.31250

0.30625

0.30000

0.29375

0.28750

0.28125

0.27500

OFF

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

17/70

VID Tables

L6714

Table 6.

Voltage Identification (VID) for Intel VR11 mode (See Note).

Output Output Output

Output

HEX Code voltage HEX Code voltage HEX Code voltage HEX Code voltage

(1)

(

1)

(

1)

(1)

1

2

3

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

9

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

0.49375

0.48750

0.48125

0.47500

0.46875

D

E

F

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

0.26875

0.26250

0.25625

0.25000

0.24375

0.23750

0.23125

0.22500

0.21875

0.21250

0.20625

0.20000

0.19375

0.18750

0.18125

0.17500

0.16875

0.16250

0.15625

0.15000

0.14375

0.13750

0.13125

0.12500

0.11875

0.11250

0.10625

0.10000

0.09375

0.08750

0.08125

0.07500

0.06875

9

A

B

18/70

L6714

VID Tables

Output

Table 6.

Voltage Identification (VID) for Intel VR11 mode (See Note).

Output Output Output

HEX Code voltage HEX Code voltage HEX Code voltage HEX Code voltage

(1)

(

1)

(

1)

(1)

3

8

9

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

7

8

9

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

B

8

9

0.46250

0.45625

0.45000

0.44375

0.43750

0.43125

0.42500

0.41875

F

8

9

0.06250

0.05625

0.05000

0.04375

0.03750

0.03125

OFF

A

B

C

D

E

F

A

B

C

D

E

F

A

B

C

D

E

F

A

B

C

D

E

F

OFF

1. According to VR11 specs, the device automatically regulates output voltage 19mV lower to avoid any

external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage

is than what extracted from the table lowered by 19mV built-in offset.

5.3

Voltage Identifications (VID) for Intel VR10 mode + 6.25mV

(VID7 does not care)

Table 7.

Voltage identifications (VID) for Intel VR10 mode + 6.25mV (See Note).

Output

VID VID VID VID VID VID VID

voltage

4

3

2

1

0

5

6

4

3

2

1

0

5

6

(1)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

19/70

VID Tables

L6714

Voltage identifications (VID) for Intel VR10 mode + 6.25mV (See Note).

Table 7.

Output

VID VID VID VID VID VID VID

voltage

4

3

2

1

0

5

6

4

3

2

1

0

5

6

(1)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.10000

1.09375

OFF

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

20/70

L6714

VID Tables

Voltage identifications (VID) for Intel VR10 mode + 6.25mV (See Note).

Table 7.

Output

VID VID VID VID VID VID VID

voltage

4

3

2

1

0

5

6

4

3

2

1

0

5

6

(1)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

1. According to VR10.x specs, the device automatically regulates output voltage 19mV lower to avoid any

external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage

is than what extracted from the table lowered by 19mVbuilt-in offset. VID7 doesn’t care.

5.4

5.5

Mapping for the AMD 6BIT mode

Table 8.

VID4

400mV

Voltage identifications (VID) mapping for AMD 6BIT mode

VID3

VID2

VID1

VID0

200mV

100mV

50mV

25mV

Voltage identifications (VID) codes for AMD 6BIT mode

Table 9.

Voltage identifications (VID) codes for AMD 6BIT mode (See Note).

Output

Voltage

VID VID VID VID VID VID

Voltage

5

4

3

2

1

0

5

4

3

2

1

0

(1)

0

1

0

1

0

1

1.5500

1.5250

1.5000

1.4750

1

0

1

0

1

0

1

0.7625

0.7500

0.7375

0.7250

21/70

VID Tables

L6714

Table 9.

Voltage identifications (VID) codes for AMD 6BIT mode (See Note).

Output

Voltage

VID VID VID VID VID VID

Voltage

5

4

3

2

1

0

5

4

3

2

1

0

(1)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.4500

1.4250

1.4000

1.3750

1.3500

1.3250

1.3000

1.2750

1.2500

1.2250

1.2000

1.1750

1.1500

1.1250

1.1000

1.0750

1.0500

1.0250

1.0000

0.9750

0.9500

0.9250

0.9000

0.8750

0.8500

0.8250

0.8000

0.7750

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

1. VID6 Not Applicable, need to be left unconnected.

22/70

L6714

Reference schematic

6

Reference schematic

Figure 3. Reference schematic - Intel VR10.x, VR11 inductor sense

VIN

LIN

to BOOT1

to BOOT2

to BOOT3

GNDIN

62

56

57

2

CIN

VIN

VCCDR1

VCCDR2

VCCDR3

BOOT1

UGATE1

PHASE1

LGATE1

to BOOT4

1

HS1

63,64

61

L1

C

51

15

VCCDR4

VCC

R

LS1

60

31

30

10

PGND1

CS1-

19,50

33

SGND

OVP

Rg

CS1+

VIN

16

32

BOOT2

DAC / CS_SEL

OFFSET

9

UGATE2

PHASE2

LGATE2

HS2

37

18

OSC/FAULT

7,8

55

L2

C

SSOSC / REF

R

LS2

38

39

40

41

42

43

44

45

VID7 / DVID

VID6

54

27

26

6

PGND2

CS2-

VID5

VID4

VID3

CS2+

VID2

Vcc_core

VIN

BOOT3

VID1

VID0

5

COUT

UGATE3

PHASE3

LGATE3

HS3

LOAD

34

17

VID_SEL

OUTEN

VID_SEL

OUTEN

3,4

58

L3

R

LS3

23

COMP

59

29

28

14

PGND3

CS3-

C

CF

RF

22

21

FB

CS3+

DROOP

VIN

BOOT4

RFB

13

20

UGATE4

PHASE4

LGATE4

HS4

VSEN

11,12

52

L4

47

48

VR_HOT

VR_FAN

R

LS4

+5V

53

25

24

46

NTC

49

PGND4

CS4-

C

TM

CS4+

SS_END

SS_END / PGOOD

FBR FBG

35 36

L6714 REF. SCH. (INDUCTOR - Intel Mode)

23/70

Reference schematic

Figure 4. Reference schematic - Intel VR10.x, VR11 LS MOSFET sense

L6714

V

IN

LIN

to BOOT1

to BOOT2

to BOOT3

GNDIN

62

56

57

2

C

IN

V

IN

VCCDR1

VCCDR2

VCCDR3

BOOT1

UGATE1

PHASE1

LGATE1

to BOOT4

1

HS1

LS1

63,64

61

L1

L2

L3

L4

51

15

VCCDR4

VCC

60

31

30

10

PGND1

CS1-

19,50

33

SGND

OVP

Rg

CS1+

V

IN

170k

15

32

BOOT2

DAC / CS_SEL

OFFSET

9

UGATE2

PHASE2

LGATE2

HS2

LS2

37

18

OSC/FAULT

7,8

55

SSOSC / REF

38

39

40

41

42

43

44

45

VID7 / D-VID

VID6

54

27

26

6

PGND2

CS2-

VID5

Rg

VID4

VID3

CS2+

VID2

Vcc_core

V

IN

BOOT3

VID1

VID0

5

COUT

UGATE3

PHASE3

LGATE3

HS3

LS3

LOAD

34

17

VID_SEL

OUTEN

VID_SEL

OUTEN

3,4

58

23

COMP

59

29

28

14

PGND3

CS3-

C

R

F

Rg

F

22

21

FB

CS3+

DROOP

V

IN

BOOT4

R

FB

13

20

UGATE4

PHASE4

LGATE4

HS4

LS4

VSEN

11,12

52

47

48

VR_HOT

VR_FAN

+5V

53

25

24

46

NTC

49

PGND4

CS4-

TM

Rg

CS4+

PGOOD

SSEND / PGOOD

FBR FBG

35 36

L6714 REF. SCH. (MOSFET - Intel Mode)

24/70

L6714

Reference schematic

Figure 5. Reference schematic - AMD 6BIT inductor sense

V

IN

LIN

to BOOT1

to BOOT2

to BOOT3

GNDIN

62

56

57

2

C

IN

V

IN

VCCDR1

VCCDR2

VCCDR3

BOOT1

UGATE1

PHASE1

LGATE1

to BOOT4

1

HS1

LS1

63,64

61

L1

C

51

15

VCCDR4

VCC

R

60

31

30

10

PGND1

CS1-

19,50

33

SGND

OVP

Rg

CS1+

V

IN

270k

16

32

BOOT2

DAC / CS_SEL

OFFSET

9

UGATE2

PHASE2

LGATE2

HS2

LS2

37

18

OSC/FAULT

7,8

55

L2

C

SSOSC / REF

R

38

39

40

41

42

43

44

45

VID7 / DVID

VID6

54

27

26

6

PGND2

CS2-

VID5

VID4

VID3

CS2+

VID2

Vcc_core

V

IN

BOOT3

VID1

VID0

5

COUT

UGATE3

PHASE3

LGATE3

HS3

LS3

LOAD

34

17

VID_SEL

OUTEN

3,4

58

L3

OUTEN

R

23

COMP

59

29

28

14

PGND3

CS3-

C

R

F

22

21

FB

CS3+

DROOP

V

IN

BOOT4

R

FB

13

20

UGATE4

PHASE4

LGATE4

HS4

LS4

VSEN

11,12

52

L4

47

48

VR_HOT

VR_FAN

R

+5V

53

25

24

46

NTC

49

PGND4

CS4-

C

TM

CS4+

SS_END

SS_END / PGOOD

FBR FBG

35 36

L6714 REF. SCH. (INDUCTOR - AMD 6BIT Mode)

25/70

Reference schematic

Figure 6. Reference schematic - AMD 6BIT LS MOSFET sense

L6714

VIN

LIN

to BOOT1

to BOOT2

to BOOT3

GNDIN

62

56

57

2

C

IN

V

IN

VCCDR1

VCCDR2

VCCDR3

BOOT1

UGATE1

PHASE1

LGATE1

to BOOT4

1

HS1

LS1

63,64

61

L1

L2

L3

L4

51

15

VCCDR4

VCC

60

31

30

10

PGND1

CS1-

19,50

33

SGND

OVP

Rg

CS1+

V

IN

15

32

BOOT2

DAC / CS_SEL

OFFSET

9

UGATE2

PHASE2

LGATE2

HS2

LS2

37

18

OSC/FAULT

7,8

55

SSOSC / REF

38

39

40

41

42

43

44

45

VID7 / D-VID

VID6

54

27

26

6

PGND2

CS2-

VID5

Rg

VID4

VID3

CS2+

VID2

Vcc_core

V

IN

BOOT3

VID1

VID0

5

COUT

UGATE3

PHASE3

LGATE3

HS3

LS3

LOAD

34

17

VID_SEL

OUTEN

3,4

58

OUTEN

23

COMP

59

29

28

14

PGND3

CS3-

C

R

F

Rg

22

21

FB

CS3+

DROOP

V

IN

BOOT4

R

FB

13

20

UGATE4

PHASE4

LGATE4

HS4

LS4

VSEN

11,12

52

47

48

VR_HOT

VR_FAN

+5V

53

25

24

46

NTC

49

PGND4

CS4-

TM

Rg

CS4+

PGOOD

SSEND / PGOOD

FBR FBG

35 36

L6714 REF. SCH. (MOSFET - AMD 6BIT Mode)

26/70

L6714

Device description

7

Device description

L6714 is four-phase PWM controller with embedded high current drivers that provides

complete control logic and protections for a high performance step-down DC-DC voltage

regulator optimized for advanced microprocessor power supply. Multi phase buck is the

simplest and most cost-effective topology employable to satisfy the increasing current

demand of newer microprocessors and modern high current VRM modules. It allows

distributing equally load and power between the phases using smaller, cheaper and most

common external power MOSFET and inductors. Moreover, thanks to the equal phase shift

between each phase, the input and output capacitor count results in being reduced. Phase

interleaving causes in fact input RMS current and output ripple voltage reduction and show

an effective output switching frequency increase: the 150kHz free-running frequency per

phase, externally adjustable through a resistor, results multiplied on the output by the

number of phases.

L6714 permits easy and flexible system design by allowing current reading across either

inductor or low side MOSFET in fully differential mode simply selecting the desired way

through apposite pin. In both cases, also a sense resistor in series to the related element

can be considered to improve reading precision. The current information read corrects the

PWM output in order to equalize the average current carried by each phase limiting the error

at 3% over static and dynamic conditions unless considering the sensing element spread.

The controller includes multiple DACs, selectable through an apposite pin, allowing

compatibility with both Intel VR10,VR11 and AMD 6BIT processors specifications, also

performing D-VID transitions accordingly.

Low-Side-Less start-up allows soft start over pre-biased output avoiding dangerous current

return through the main inductors as well as negative spike at the load side.

L6714 provides programmable Over-Voltage protection to protect the load from dangerous

over stress. It can be externally set to a fixed voltage through an apposite resistor, or it can

be set internally, latching immediately by turning ON the lower driver and driving high the

FAULT pin. Furthermore, preliminary OVP protection also allows the device to protect load

from dangerous OVP when VCC is not above the UVLO threshold.

The Over-Current protection provided, with an OC threshold for each phase, causes the

device to enter in constant current mode until the latched UVP.

L6714 provides system Thermal Monitoring: through an apposite pin the device senses the

temperature of the hottest component in the application driving the Warning and the Alarm

signal as a consequence.

A compact 10x10mm body TQFP64 package with exposed thermal pad allows dissipating

the power to drive the external MOSFET through the system board.

27/70

Configuring the device

L6714

8

Configuring the device

Multiple DACs and different current reading methodologies need to be configured before the

system starts-up by programming the apposite pin DAC/CS_SEL.

The configuration of this pin identifies two main working areas (See Table 10) distinguishing

between compliancy with Intel VR10,VR11 or AMD 6BIT specifications. According to the

main specification considered, further customs can be done: main differences are regarding

the DAC table, soft-start implementation, protection management and Dynamic VID

Transitions. Of course, the Current Reading method can be still selected through DAC /

CS_SEL pin.

See Table 11 and See Table 12 for further details about the device configuration.

8.1

DAC selection

L6714 embeds a selectable DAC (through DAC/CS_SEL, See Table 10) that allows to

regulate the output voltage with a tolerance of 0.5% ( 0.6% for AMD DAC) recovering from

offsets and manufacturing variations. In case of selecting Intel Mode, the device

automatically introduces a -19mV (both VRD10.x and VR11) offset to the regulated voltage

in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a

consequence, the calculated system TOB.

Table 10. DAC / CS_SEL settings (See Note).

DAC / CS_SEL

Resistance vs. SGND

Current sense

method

DAC

OVP

UVP

0 (Short)

Inductor DCR

VID + 150mV

(typ) or

Programmable

Intel

-750mV (typ)

170kΩ

MOSFET R_dsON

270kΩ

Inductor DCR

1.800V (typ) or

Programmable

AMD

OPEN

MOSFET R_dsON

Note:

Filter DAC/CS_SEL pin with 100pF(max) vs. SGND.

Output voltage is programmed through the VID pins: they are inputs of an internal DAC that

is realized by means of a series of resistors providing a partition of the internal voltage

reference. The VID code drives a multiplexer that selects a voltage on a precise point of the

divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the

set-point of the error amplifier, V_REF).

28/70

L6714

Configuring the device

Typical connection

Table 11. Intel mode configuration (See Note).

Function

SGND: Inductor Sense;

It allows selecting the Intel Mode and,

furthermore, between Inductor or LS MOSFET

current reading.

170kΩ to SGND: LS MOSFET

Sense.

DAC / CS_SEL

Static info, no dynamic changes allowed.

Filter with 100pF(max).

Resistor R_SSOSCvs. SGND.

Open: VR11 (Table 6).

It allows programming the soft-start time T_SS

.

SSOSC / REF

See “Soft start” Section for details.

It allows selecting between VR11 DAC or

VR10.x + 6.25mV extended DAC.

VID_SEL

Short to SGND: VR10.x

Static info, no dynamic changes allowed.

(Table 7).

They allow programming the Output Voltage

according to Table 6 and Table 7.

Open: Logic “1” (25µA pull-up)

Short to SGND: “0”

VID7 to VID0

Dynamic transitions managed, See “Dynamic

VID transitions” Section for details.

SSEND /

PGOOD

Soft Start end signal set free after soft-start has Pull-up to anything lower than

finished. It only indicates soft-start has finished. 5V.

Note:

VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes

according to the selected DAC: See Table 4 for details.

Table 12. AMD mode configuration (See Note).

Function

Typical connection

270kΩ to SGND: Inductor

It allows selecting the AMD mode and,

furthermore, between Inductor or LS MOSFET

current reading.

Sense;

DAC / CS_SEL

OPEN: LS MOSFET Sense;

Filter with 100pF(max).

Static info, no dynamic changes allowed.

The reference used for the regulation is

available on this pin.

Filter with 47Ω - 4.7nF vs.

SSOSC / REF

VID_SEL

VID7 / DVID

VID6

SGND.

Not Applicable

Need to be shorted to SGND.

Not Applicable

Pulled high when performing a D-VID transition.

The pin is kept high with a 32 clock cycles delay.

Not Applicable

Needs to be shorted to SGND

They allow programming the Output Voltage

according to Table 9.

Open: “0” (12.5µA pull-down)

Pull-up to V > 1.4V: “1”

VID5 to VID0

Dynamic transitions managed, See “Dynamic

VID transitions” Section for details.

Power Good signal set free after soft-start has

finished whenever the output voltage is within

limits.

SSEND /

PGOOD

Pull-up to anything lower than

5V.

Note:

VID pull-ups / pull-downs, VID voltage thresholds and OUTEN thresholds changes

according to the selected DAC: See Table 4 for details.

29/70

Power dissipation

L6714

9

Power dissipation

L6714 embeds high current MOSFET drivers for both high side and low side MOSFET: it is

then important to consider the power the device is going to dissipate in driving them in order

to avoid overcoming the maximum junction operative temperature. In addition, since the

device has an exposed pad to better dissipate the power, the thermal resistance between

junction and ambient consequent to the layout is also important: thermal pad need to be

soldered to the PCB ground plane through several VIAs in order to facilitate the heat

dissipation.

Two main terms contribute to the device power dissipation: bias power and drivers' power.

The first one (P_DC) depends on the static consumption of the device through the supply pins

and is simply quantifiable as follows (assuming to supply HS and LS drivers with the same

VCC of the device):

P_DC= V_CC⋅ (I_CC+ N ⋅ I_CCDRx+ N ⋅ I_BOOTx

)

where N is the number of phases.

Drivers' power is the power needed by the driver to continuously switch on and off the

external MOSFET; it is a function of the switching frequency and total gate charge of the

selected MOSFET. It can be quantified considering that the total power P_SWdissipated to

switch the MOSFET (easy calculable) is dissipated by three main factors: external gate

resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This

last term is the important one to be determined to calculate the device power dissipation.

The total power dissipated to switch the MOSFET results:

P_SW= N ⋅ F_SW⋅ (Q_GHS⋅ V_BOOT+ Q_GLS⋅ V_CCDRx

)

External gate resistors help the device to dissipate the switching power since the same

power P_SWwill be shared between the internal driver impedance and the external resistor

resulting in a general cooling of the device. When driving multiple MOSFET in parallel, it is

suggested to use one gate resistor for each MOSFET.

30/70

L6714

Power dissipation

Figure 7. L6714 dissipated power (Quiescent + switching).

L6714; Rgate=0; Rmosfet=0

5000

HS=1xSTD38NH02L; LS=1xSTD90NH02L

HS=2xSTD38NH02L; LS=2xSTD90NH02L

4500

HS=1xSTD55NH22L; LS=1xSTD95NH02L

4000

HS=2xSTD55NH22L; LS=2xSTD95NH02L

HS=3xSTD55NH22L; LS=3xSTD95NH02L

3500

3000

2500

2000

1500

1000

500

0

50

100

150

200

250

300

350

400

450

500

550

Switching frequency [kHz] per phase

L6714; Rhs=2.2; Rls=3.3; Rmosfet=1

7000

6000

5000

4000

3000

2000

1000

0

HS=1xSTD38NH02L; LS=1xSTD90NH02L

HS=2xSTD38NH02L; LS=2xSTD90NH02L

HS=1xSTD55NH2LL; LS=1xSTD95NH02L

HS=2xSTD55NH2LL; LS=2xSTD95NH02L

HS=3xSTD55NH2LL; LS=3xSTD95NH02L

50

100

150

200

250

300

350

400

450

500

550

Switching Frequency per phase [kHz]

31/70

Current reading and current sharing loop

L6714

10

Current reading and current sharing loop

L6714 embeds a flexible, fully-differential current sense circuitry that is able to read across

both low side or inductor parasitic resistance or across a sense resistor placed in series to

that element. The fully-differential current reading rejects noise and allows placing sensing

element in different locations without affecting the measurement's accuracy. The kind of

sense element can be simply chosen through the DAC/CS_SEL pin according to See

Table 10.

Current sharing control loop reported in Figure 8: it considers a current I_INFOxproportional to

the current delivered by each phase and the average currentI_AVG= ΣI_INFOx⁄ (N). The error

between the read current I_INFOxand the reference I_AVGis then converted into a voltage that

with a proper gain is used to adjust the duty cycle whose dominant value is set by the

voltage error amplifier in order to equalize the current carried by each phase. Details about

connections are shown in Figure 9.

Figure 8. Current sharing loop.

I_INFO1

PWM1 Out

I_AVG

I_INFO2

AVG

PWM2 Out

From EA

I_INFO3

PWM3 Out

I_INFO4

PWM4 Out

32/70

L6714

Current reading and current sharing loop

10.1

Low side current reading

When reading current across LS, the current flowing trough each phase is read using the

voltage drop across the low side MOSFET R_dsONor across a sense resistor in its series and

it is internally converted into a current. The trans-conductance ratio is issued by the external

resistor Rg placed outside the chip between CSx- and CSx+ pins toward the reading points.

The current sense circuit tracks the current information for a time T_TRACKcentered in the

middle of the LS conduction time and holds the tracked information during the rest of the

period.

L6714 sources a constant 25µA bias current from the CSx+ pin: the current reading circuitry

uses this pin as a reference and the reaction keeps the CSx- pin to this voltage during the

reading time (an internal clamp keeps CSx+ and CSx- at the same voltage sinking from the

CSx- pin the necessary current during the hold time; this is needed to avoid absolute

maximum rating overcome on CSx- pin). The current that flows from the CSx- pin is then

given by (See Figure 9):

R_dsON

-----------------

I_CSx-= 25µA +

⋅ I_PHASEx= 25µA + I_INFOx

Rg

where R_dsONis the ON resistance of the low side MOSFET and Rg is the trans-conductance

resistor used between CSx- and CSx+ pins toward the reading points; I_PHASExis the current

carried by the relative phase and I_INFOxis the current information signal reproduced

internally.

25µA offset allows negative current reading, enabling the device to check for dangerous

returning current between the phases assuring the complete current equalization.

10.2

Inductor current reading

When reading current across the inductor DCR, the current flowing trough each phase is

read using the voltage drop across the output inductor or across a sense resistor in its

series and internally converted into a current. The trans-conductance ratio is issued by the

external resistor Rg placed outside the chip between CSx- pin toward the reading points.

The current sense circuit always tracks the current information, no bias current is sourced

from the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this voltage. To

correctly reproduce the inductor current an R-C filtering network must be introduced in

parallel to the sensing element.

The current that flows from the CSx- pin is then given by the following equation (See

Figure 9):

R_L1 + s ⋅ L ⁄ R_L

Rg 1 + s ⋅ R ⋅ C

------- -------------------------------------

I_CSx-

=

⋅

⋅ I

PHASEx

Where I_PHASExis the current carried by the relative phase.

33/70

Current reading and current sharing loop

Figure 9. Current reading connections.

L6714

I_PHASEx

Lx R_Lx

I_PHASEx

PHASEx

CSx+

LGATEx

CSx-

R

C

Rg

I_CSx-

NO Bias

I_CSx-=I_INFOx

25µA

CSx+

CSx-

Rg

LS Mosfet R_dsONCurrent Sense

Inductor DCR Current Sense

Considering now to match the time constant between the inductor and the R-C filter applied

(Time constant mismatches cause the introduction of poles into the current reading network

causing instability. In addition, it is also important for the load transient response and to let

the system show resistive equivalent output impedance), it results:

R_L

-------

Rg

R_L

-------

Rg

L

R_L

------ = R ⋅ C

⇒

I_CSx-

=

⋅ I_PHASEx= I_INFOx

⇒

I_INFOX

=

⋅ I_PHASEx

Where I_INFOxis the current information reproduced internally.

34/70

L6714

Remote voltage sense

11

Remote voltage sense

The device embeds a Remote Sense Buffer to sense remotely the regulated voltage without

any additional external components. In this way, the output voltage programmed is regulated

between the remote buffer inputs compensating motherboard or connector losses. It senses

the output voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage

sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin

with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded

by a power plane results in common mode coupling for any picked-up noise.

If remote sense is not required, it is enough connecting the resistor R_FBdirectly to the

regulated voltage: VSEN becomes not connected and still senses the output voltage

through the remote buffer. In this case the FBG and FBR pins must be connected anyway to

the regulated voltage (See Figure 10).

Warning: The remote buffer is included in the trimming chain in order

to achieve 0.5% accuracy (0.6% for the AMD DAC) on the

output voltage when the RB is used: eliminating it from the

control loop causes the regulation error to be increased by

the RB offset worsening the device performances.

Figure 10. Remote buffer connections

64k

V_REF

64k

FB

COMP

C_F

VSEN

FBR

FBG

FB

COMP

C_F

VSEN

FBR

FBG

R_F

To Vcore

(Remote Sense)

R_FB

To Vcore

Remote Buffer Used (Up to 0.5% Accuracy)

Remote Buffer NOT Used (Precision Worsened)

35/70

Voltage positioning

L6714

12

Voltage positioning

Output voltage positioning is performed by selecting the reference DAC and by

programming the Droop Function and Offset to the reference (See Figure 11). The currents

sourced from DROOP and FB pins cause the output voltage to vary according to the

external R_FBresistor.

In addition, the embedded Remote Buffer allows to precisely programming the output

voltage offsets and variations by recovering the voltage drops across distribution lines.

The output voltage is then driven by the following relationship:

V_OUT= V_REF– R_FB⋅ (I_DROOP– I_OFFSET

)

where

⎧

⎨

⎩

VID – 19mV VR10 - VR11

VID AMD 6BIT

V_REF

=

DROOP function can be disabled as well as the OFFSET: connecting DROOP pin and FB

pin together implements the load regulation dependence while, if this effect is not desired,

by shorting DROOP pin to SGND it is possible for the device to operate as a classic Voltage

Mode Buck converter. The DROOP pin can also be connected to SGND through a resistor

obtaining a voltage proportional to the delivered current usable for monitoring purposes.

OFFSET can be disabled by shorting the relative pin to SGND.

36/70

L6714

Voltage positioning

12.1

Droop function (Optional)

This method "recovers" part of the drop due to the output capacitor ESR in the load

transient, introducing a dependence of the output voltage on the load current: a static error

proportional to the output current causes the output voltage to vary according to the sensed

current.

As shown in Figure 11, the ESR drop is present in any case, but using the droop function

the total deviation of the output voltage is minimized. Moreover, more and more high-

performance CPUs require precise load-line regulation to perform in the proper way.

DROOP function is not then required only to optimize the output filter, but also beacomes a

requirement of the load.

Connecting DROOP pin and FB pin together, the device forces a current I_DROOP

,

proportional to the read current, into the feedback resistor R_FBimplementing the load

regulation dependence. Since I_DROOPdepends on the current information about the three

phases, the output characteristic vs. load current is then given by:

R_SENSE

---------------------

⋅ I_OUT= V_REF– R_DROOP⋅ I_OUT

V_OUT= V_REF– R_FB⋅ I_DROOP= V_REF– R_FB

⋅

Rg

Where R_SENSEis the chosen sensing element resistance (Inductor DCR or LS R_dsON) and

_OUTis the output current of the system.

I

The whole power supply can be then represented by a "real" voltage generator with an

equivalent output resistance R_DROOPand a voltage value of V_REF. R_FBresistor can be also

designed according to the R_DROOPspecifications as follow:

Rg

R_SENSE

---------------------

⋅

R_FB= R_DROOP

Droop function is optional, in case it is not desired, the DROOP pin can be disconnected

from the FB and an information about the total delivered current becomes available for

debugging, and/or current monitoring. When not used, the pin can be shorted to SGND.

Figure 11. Voltage positioning (left) and droop function (right)

64k

ESR Drop

V_REF

V

MAX

64k

V

NOM

DROOP

FB

COMP

C_F

VSEN

FBR

FBG

V

MIN

R_F

RESPONSE WITHOUT DROOP

RESPONSE WITH DROOP

To Vcore

(Remote Sense)

R_FB

37/70

Voltage positioning

L6714

12.2

Offset (Optional)

The OFFSET pin allows programming a positive offset (V_OS) for the output voltage by

connecting a resistor R_OFFSETvs. SGND; this offset has to be considered in addition to the

one already introduced during the production stage for the Intel VR10,VR11 Mode.

The OFFSET pin is internally fixed at 1.240V (See Table 4) a current is programmed by

connecting the resistor R_OFFSETbetween the pin and SGND: this current is mirrored and

then properly sunk from the FB pin as shown in Figure 12. Output voltage is then

programmed as follow:

V_OUT= V_REF– R_FB⋅ (I_DROOP– I_OFFSET

)

Offset resistor can be designed by considering the following relationship (R_FBis fixed by the

Droop effect):

1.240V

V_OS

------------------

⋅ R_FB

R_OFFSET

=

Offset automatically given by the DAC selection differs from the offset implemented through

the OFFSET pin: the built-in feature is trimmed in production and assures 0.5% error

( 0.6% for the AMD DAC) over load and line variations.

Figure 12. Voltage positioning with offset

64k

V_REF

1.240V

64k

OFFSET

DROOP

FB

COMP

C_F

VSEN

FBR

FBG

R

OFFSET

R_F

To Vcore

(Remote Sense)

R_FB

38/70

L6714

Dynamic VID transitions

13

Dynamic VID transitions

The device is able to manage Dynamic VID Code changes that allow Output Voltage

modification during normal device operation. OVP and UVP signals (and PGOOD in case of

AMD Mode) are masked during every VID transition and they are re-activated after the

transition finishes with a 32 clock cycles delay to prevent from false triggering due to the

transition.

When changing dynamically the regulated voltage (D-VID), the system needs to charge or

discharge the output capacitor accordingly. This means that an extra-current I_D-VIDneeds to

be delivered, especially when increasing the output regulated voltage and it must be

considered when setting the over current threshold. This current can be estimated using the

following relationships:

dV_OUT

-----------------

⋅

I_{D – VID}= C_OUT

dT_VID

where dV_OUTis the selected DAC LSB (6.25mV for VR11 and VR10 Extended DAC or 25mV

for AMD DAC) and T_VIDis the time interval between each LSB transition (externally driven).

Overcoming the OC threshold during the dynamic VID causes the device to enter the

constant current limitation slowing down the output voltage dV/dt also causing the failure in

the D-VID test.

L6714 checks for VID code modifications (See Figure 13) on the rising edge of an internal

additional DVID-clock and waits for a confirmation on the following falling edge. Once the

new code is stable, on the next rising edge, the reference starts stepping up or down in LSB

increments every VID-clock cycle until the new VID code is reached. During the transition,

VID code changes are ignored; the device re-starts monitoring VID after the transition has

finished on the next rising edge available. VID-clock frequency (F_DVID) depends on the

operative mode selected: for Intel Mode it is in the range of 1MHz to assure compatibility

with the specifications while, for AMD Mode, this frequency is lowered to about 250kHz.

When L6714 performs a D-VID transition in AMD Mode, DVID pin is pulled high as long as

the device is performing the transition (also including the additional 32clocks delay)

Warning: If the new VID code is more than 1 LSB different from the

previous, the device will execute the transition stepping the

reference with the DVID-clock frequency F_DVIDuntil the new

code has reached: for this reason it is recommended to

carefully control the VID change rate in order to carefully

control the slope of the output voltage variation especially in

Intel Mode.

39/70

Dynamic VID transitions

L6714

Figure 13. Dynamic VID transitions

VID Clock

VID [0,7]

t

Int. Reference

T_DVID

T

sw

t

V

out

T_VID

x 4 Step VID Transition

4 x 1 Step VID Transition

Vout Slope Controlled by internal

DVID-Clock Oscillator

Vout Slope Controlled by external

driving circuit (T_VID

)

40/70

L6714

Enable and disable

14

Enable and disable

L6714 has three different supplies: VCC pin to supply the internal control logic, VCCDRx to

supply the low side drivers and BOOTx to supply the high side drivers.

If the voltage at pins VCC and VCCDRx are not above the turn on thresholds specified in the

Electrical characteristics, the device is shut down: all drivers keep the MOSFET off to show

high impedance to the load.

Once the device is correctly supplied, proper operation is assured and the device can be

driven by the OUTEN pin to control the power sequencing.

Setting the pin free, the device implements a soft start up to the programmed voltage.

Shorting the pin to SGND, it resets the device (SS_END/PGOOD is shorted to SGND in this

condition) from any latched condition and also disables the device keeping all the MOSFET

turned off to show high impedance to the load.

41/70

Soft start

L6714

15

Soft start

L6714 implements a soft-start to smoothly charge the output filter avoiding high in-rush

currents to be required to the input power supply. The device increases the reference from

zero up to the programmed value in different ways according to the selected Operative

Mode and the output voltage increases accordingly with closed loop regulation.

The device implements Soft-Start only when all the power supplies are above their own turn-

on thresholds and the OUTEN pin is set free.

At the end of the digital Soft-Start, SS_END/PGOOD signal is set free. Protections are

active during this phase; Under Voltage is enabled when the reference voltage reaches 0.6V

while Over Voltage is always enabled with a threshold dependent on the selected Operative

Mode or with the fixed threshold programmed by R_OVP(See “Over voltage and

programmable OVP” Section).

Figure 14. Soft start

Intel Mode

AMD 6BIT Mode

OUTEN

V_OUT

OUTEN

V_OUT

OVP

t

SS_END

PGOOD

T₁T₂T₃T₄

T_SS

t

T_SS

42/70

L6714

Soft start

15.1

Intel mode

Once L6714 receives all the correct supplies and enables, and Intel Mode has been

selected, it initiates the Soft-Start phase with a T₁= 1ms_(min)delay. After that, the reference

ramps up to V_BOOT= 1.081V (1.100V - 19mV) in T₂according to the SSOSC settings and

waits for T₃= 75µsec_(typ)during which the device reads the VID lines. Output voltage will

then ramps up to the programmed value in T₄with the same slope as before (See

Figure 14).

SSOSC defines the frequency of an internal additional Soft-Start-oscillator used to step the

reference from zero up to the programmed value; this oscillator is independent from the

main oscillator whose frequency is programmed through the OSC pin. SSOSC sets then the

Output Voltage dV/dt during Soft-Start according to the resistor R_SSOSCconnected vs.

SGND. In particular, it allows to precisely programming the start-up time up to V_BOOT(T₂)

since it is a fixed voltage independent by the programmed VID. Total Soft-Start time

dependence on the programmed VID results (See Figure 15):

R_SSOSC[kΩ] = T₂[µs] ⋅ 4.9783 ⋅ 10^–2

⎧

⎪

⎨

⎪

⎩

R_SSOSC[kΩ]

5.3816 ⋅ 10^–2

-------------------------------------

⋅ V_SS

if(V_SS>V_BOOT

)

T_SS[µs] = 1075[µs] +

R_SSOSC[kΩ]

-------------------------------------

⋅ [V_BOOT+ (V_BOOT– V_SS)] if(V_SS< V_BOOT

)

5.3816 ⋅ 10^–2

where T_SSis the time spent to reach the programmed voltage V_SSand R_SSOSCthe resistor

connected between SSOSC and SGND in kΩ.

Protections are active during Soft-Start, UVP is enabled after the reference reaches 0.6V

while OVP is always active with a fixed 1.24V threshold before V_BOOTand with the threshold

coming from the VID (or the programmed V_OVP) after V_BOOT(See red-dashed line in

Figure 14).

Note:

If during T₃the programmed VID selects an output voltage lower than V_BOOT, the output

voltage will ramp to the programmed voltage starting from V_BOOT

.

43/70

Soft start

L6714

Figure 15. Soft-start time for Intel mode.

8

7

Time to Vboot

Time to 1.6000V

6

5

4

3

2

1

0

1

10

100

1000

Rssosc [kOhms] vs. SGND

15.2

AMD mode

Once L6714 receives all the correct supplies and enables, and AMD Mode has been

selected, it initiates the Soft-Start by stepping the reference from zero up to the programmed

VID code (See Figure 14); the clock now used to step the reference is the same as the main

oscillator programmed by the OSC pin, SSOSC pin is not applicable in this case. The Soft-

Start time results then (See Figure 16):

dV

--------^O----^U----^T- = 3.125 ⋅ F_SW[kkHz] ⇒T_SS= -------------------------------------------------

dT 3.125 ⋅ F_SW[kHz]

V_SS

where T_SSis the time spent to reach V_SSand F_SWis the main switching frequency

programmed by OSC pin. Protections are active during Soft-Start, UVP is enabled after the

reference reaches 0.6V while OVP is always active with the fixed 1.800V threshold (or the

programmed V_OVP).

44/70

L6714

Soft start

Figure 16. Soft-start time for AMD mode

4

3.5

3

550

500

450

400

350

300

250

200

150

2.5

2

1.5

1

Time to 1.6000V

Time to 1.1000V

Switching Frequency per phase

0.5

0

200

400

600

800

1000

Rosc [kOhms] to SGND

4

3.5

3

550

500

450

400

350

300

250

200

150

2.5

2

1.5

1

Time to 1.6000V

Time to 1.1000V

Switching Frequency per phase

0.5

0

200

400

600

800

1000

Rosc [kOhms] to SGND

45/70

Soft start

L6714

15.3

Low-Side-Less startup

In order to avoid any kind of negative undershoot on the load side during start-up, L6714

performs a special sequence in enabling LS driver to switch: during the soft-start phase, the

LS driver results disabled (LS=OFF) until the HS starts to switch. This avoid the dangerous

negative spike on the output voltage that can happen if starting over a pre-biased output

(See Figure 17).

This particular feature of the device masks the LS turn-on only from the control loop point of

view: protections are still allowed to turn-ON the LS MOSFET in case of over voltage if

needed.

Figure 17. Low-Side-Less start-up comparison

46/70

L6714

Output voltage monitor and protections

16

Output voltage monitor and protections

L6714 monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP

and PGOOD (when applicable) conditions. The device shows different thresholds when

programming different operation mode (Intel or AMD, See Table 10) but the behavior in

response to a protection event is still the same as described below.

Protections are active also during soft-start (See “Soft start” Section) while are masked

during D-VID transitions with an additional 32 clock cycle delay after the transition has

finished to avoid false triggering.

16.1

16.2

Under voltage

If the output voltage monitored by VSEN drops more than -750mV below the programmed

reference for more than one clock period, L6714 turns off all MOSFET and latches the

condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the

selected operative mode.

Preliminary over voltage

To provide a protection while VCC is below the UVLO_VCCthreshold is fundamental to avoid

damage to the CPU in case of failed HS MOSFET. In fact, since the device is supplied from

the 12V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLO_VCC). In

order to give full protection to the load, a preliminary-OVP protection is provided while VCC

is within UVLO_VCCand UVLO_OVP

.

This protection turns-on the low side MOSFET as long as the FBR pin voltage is greater

than 1.800V with a 350mV hysteresis. When set, the protection drives the LS MOSFET with

a gate-to-source voltage depending on the voltage applied to VCCDRx and independently

by the turn-ON threshold across these pins (UVLO_VCCDR). This protection depends also on

the OUTEN pin status as detailed in Figure 18.

A simple way to provide protection to the output in all conditions when the device is OFF

(then avoiding the unprotected red region in Figure 18-Left) consists in supplying the

controller through the 5V_SBbus as shown in Figure 18-Right: 5V_SBis always present before

+12V and, in case of HS short, the LS MOSFET is driven with 5V assuring a reliable

protection of the load. Preliminary OVP is always active before UVLO_VCCfor both Intel and

AMD Modes.

Figure 18. Output voltage protections and typical principle connections

+5V_SB

(OUTEN = 0)

Preliminary OVP

FBR Monitored

(OUTEN = 1)

Programmable OVP

VSEN Monitored

V

cc

+12V

VCC

UVLO

VCC

VCCDR1

VCCDR2

VCCDR3

Preliminary OVP Enabled

FBR Monitored

OVP

No Protection

Provided

47/70

Output voltage monitor and protections

L6714

16.3

Over voltage and programmable OVP

Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), L6714

provides an Over Voltage Protection: when the voltage sensed by VSEN overcomes the

OVP threshold, the controller permanently switches on all the low-side MOSFET and

switches off all the high-side MOSFET in order to protect the load. The OSC/ FAULT pin is

driven high (5V) and power supply or OUTEN pin cycling is required to restart

operations.The OVP Threshold varies according to the operative mode selected (See

Table 10).

The OVP threshold can be also programmed through the OVP pin: leaving the pin floating, it

is internally pulled-up and the OVP threshold is set according to Table 10. Connecting the

OVP pin to SGND through a resistor R_OVP, the OVP threshold becomes the voltage present

at the pin. Since the OVP pin sources a constant I_OVP= 12.5µA current(See Table 10), the

programmed voltage becomes:

OVP_TH

OVP_TH= R_OVP⋅ 12.5µA

⇒

R_OVP= -------------------

12.5µA

Filter OVP pin with 100pF(max) vs. SGND.

16.4

PGOOD (Only for AMD mode)

It is an open-drain signal set free after the soft-start sequence has finished. It is pulled low

when the output voltage drops below -300mV of the programmed voltage.

48/70

L6714

Maximum Duty-cycle limitation

17

Maximum Duty-cycle limitation

The device limits the maximum duty cycle and this value is not fixed but it depends on the

delivered current given by the following relationship:

R_SENSE

⎛

⎝

⎞

---------------------

D_(max)= 0.80 – (I_DROOP× 2.857k) = 0.80 –

× I

× 2.857k

⎠

R_g

OUT

From the previous relationships the maximum duty cycle results:

80%

40%

I_DROOP= 0µA

⎧

⎨

⎩

D_(max)

=

I_DROOP= 140µA

If the desired output characteristic crosses the limited-D_MAXmaximum output voltage, the

output resulting voltage will start to drop after the cross-point. In this case the output voltage

starts to decrease following the resulting characteristic (dotted in Figure 19) until UVP is

detected or anyway until I_DROOP=140µA.

Figure 19. Maximum Duty-Cycle (left) and limited DMAX output voltage (right)

Maximum Duty Cycle

Limited D

Limted-D

Output Voltage

MAX

D

V

OUT

MAX

80 %

0.80 V

IN

40 %

0.40 V

IN

Output Char.

MAX

Desired output Char.

Resulting Output Char.

UVP Threshold

I

OUT

DROOP

I

= 140µA

= N x I

OCPx

I

(I

= N x I

OCP OCPx

DROOP

(I

)

= 140µA)

OCP

DROOP

49/70

Over current protection

L6714

18

Over current protection

Depending on the current reading method selected, the device limits the peak or the bottom

of the inductor current entering in constant current until setting UVP as below explained.

The Over Current threshold has to be programmed, by designing the Rg resistors, to a safe

value, in order to be sure that the device doesn't enter OCP during normal operation of the

device. This value must take into consideration also the extra current needed during the

Dynamic VID Transition I_D-VIDand, since the device reads across MOSFET R_dsONor

inductor DCR, the process spread and temperature variations of these sensing elements.

Moreover, since also the internal threshold spreads, the Rg design has to consider the

minimum value I_OCTH(min)of the threshold as follow:

I

⋅ R_SENSE(max)

I_OCTH(min)

Rg = --^O----^C----^P----^x--⁽--^m----^a---^x---⁾-------------------------------------------

where I_OCPxis the current measured by the current reading circuitry when the device enters

Quasi-Constant-Current. I_OCPxmust be calculated starting from the corresponding output

current value I_OUT(OCP)as follow (I_D-VIDmust also be considered when D-VID are

implemented) considering that the device performs Track & Hold only for the LS sense

mode:

⎧

⎪

⎨

⎪

⎩

I_OUT(OCP)∆I_PPI_{D – VID}

-------------------------- – ----------- + -----------------

LowSideMosfetSense

InductorDCRSense

N

2

N

I_OCPx

=

I

∆I_PPI_{D – VID}

OUT(OCP)

-------------------------- + ----------- + -----------------

N

2

N

where I_OUT(OCP)is still the output current value at which the device enters Quasi-Constant-

Current, I_PPis the inductor current ripple in each phase I_D-VIDis the additional current

required by D-VID (when applicable) and N the number of phases. In particular, since the

device limits the peak or the valley of the inductor current (according to DAC/CS_SEL

status), the ripple entity, when not negligible, impacts on the real OC threshold value and

must be considered.

50/70

L6714

Over current protection

18.1

Low side MOSFET sense over current

The device detects an Over Current condition for each phase when the current information

_INFOxovercomes the fixed threshold of I_OCTH(35µA Typ,). When this happens, the device

I

keeps the relative LS MOSFET on, also skipping clock cycles, until the threshold is crossed

back and I_INFOxresults being lower than the I_OCTHthreshold. After exiting the OC condition,

the LS MOSFET is turned off and the HS is turned on with a duty cycle driven by the PWM

comparator.

Keeping the LS on, skipping clock cycles, causes the on-time subsequent to the exit from

the OC condition, driven by the control loop, to increase. Considering now that the device

has a maximum on-time dependence with the delivered current given by the following

relationship:

0.80 ⋅ T

0.40 ⋅ T

I_DROOP= 0µA

⎧

⎨

⎩

SW

T_ON(max)

=

I_DROOP= 140µA

I_OUT= ΣI

Where I_OUTis the output current (

_PHASEx) and T_SWis the switching period

(T_SW=1/F_SW). This linear dependence has a value at zero load of 0.80·T_SWand at maximum

current of 0.40·T_SWtypical.

When the current information I_INFOxovercomes the fixed threshold of I_OCTH(35µA Typ), the

device enters in Quasi-Constant-Current operation: the low-side MOSFET stays ON until

the current read becomes lower than I_OCPx(I_INFOx< I_OCTH) skipping clock cycles. The high

side MOSFET can be then turned ON with a T_ONimposed by the control loop after the LS

turn-off and the device works in the usual way until another OCP event is detected.

This means that the average current delivered can slightly increase in Quasi-Constant-

Current operation since the current ripple increases. In fact, the ON time increases due to

the OFF time rise because of the current has to reach the I_OCPxbottom. The worst-case

condition is when the ON time reaches its maximum value.

When this happens, the device works in Constant Current and the output voltage decrease

as the load increase. Crossing the UVP threshold causes the device to latch (Figure 20

shows this working condition).

It can be observed that the peak current (I_PEAK) is greater than I_OCPxbut it can be

determined as follow:

V

_IN– V_OUT(min)

V

_IN– V_OUT(min)

-----------------------------------------

⋅ 0.40 ⋅ T_SW

-----------------------------------------

I_PEAK= I_OCPx

+

⋅ T_ON(max)= I_OCPx

+

L

Where V

is the UVP threshold, (inductor saturation must be considered). When that

outMIN

threshold is crossed, all MOSFET are turned OFF and the device stops working. Cycle the

power supply or the OUTEN pin to restart operation.

The maximum average current during the Constant-Current behavior results:

I

_PEAK– I_OCPx

⎛

⎝

⎞

⎠

I_{MAX, tot}= N ⋅ I_MAX= N ⋅

I_OCPx+ ------------------------------------

2

51/70

Over current protection

L6714

in this particular situation, the switching frequency for each phase results reduced. The ON

time is the maximum allowed T_ON(max)while the OFF time depends on the application:

I

_PEAK– I_OCPx

1

------------------------------------

T_OFF= L ⋅

f = --------------------------------------------

_ON(max)+ T_OFF

V_OUT

T

Figure 20. Constant current

Constant Current (Exploded)

I_PEAK

V_OUT

0.40 V_IN

I_MAX

Droop Effect

I_OCPx

Limted-T_ONChar.

T_ON(max)

LS ON Skipping

Clock Cycles

T_ON(max)

Resulting Out. Char.

UVP Threshold

uCernt

uQiaC-otns.

I_OUT

I_MAX,tot

I_OCP= 4 x I_OCPx

(I_DROOP= 140µA)

T_SW

The trans-conductance resistor Rg can be designed considering that the device limits the

bottom of the inductor current ripple and also considering the additional current delivered

during the quasi-constant-current behavior as previously described in the worst case

conditions.

Moreover, when designing D-VID compatible systems, the additional current due to the

output filter charge during dynamic VID transitions must be considered.

I

⋅ R_SENSE(max)

I_OCTH(min)

Rg = --^O----^C----^P----^x--⁽--^m----^a---^x---⁾-------------------------------------------

where

I_OUT(OCP)∆I_PPI_{D – VID}

I_OCPx= -------------------------- – ----------- + -----------------

N

2

N

52/70

L6714

Over current protection

18.2

Inductor sense over current

The device detects an over current when the II_NFOxovercome the fixed threshold I_OCTH

.

Since the device always senses the current across the inductor, the I_OCTHcrossing will

happen during the HS conduction time: as a consequence of OCP detection, the device will

turn OFF the HS MOSFET and turns ON the LSMOSFET of that phase until I_INFOxre-cross

the threshold or until the next clock cycle. This implies that the device limits the peak of the

inductor current.

In any case, the inductor current won't overcome the I_OCPxvalue and this will represent the

maximum peak value to consider in the OC design.

The device works in Constant-Current, and the output voltage decreases as the load

increase, until the output voltage reaches the UVP threshold. When this threshold is

crossed, all MOSFETs are turned off and the device stops working. Cycle the power supply

or the OUTEN pin to restart operation.

The transconductance resistor Rg can be designed considering that the device limits the

inductor current ripple peak. Moreover, when designing D-VID systems, the additional

current due to the output filter charge during dynamic VID transitions must be considered.

I

⋅ R_SENSE(max)

I_OCTH(min)

Rg = --^O----^C----^P----^x--⁽--^m----^a---^x---⁾-------------------------------------------

where

I_OUT(OCP)∆I_PPI_{D – VID}

I_OCPx= -------------------------- + ----------- + -----------------

N

2

N

53/70

Oscillator

L6714

19

Oscillator

L6714 embeds four phase oscillator with optimized phase-shift (90º phase-shift) in order to

reduce the input rms current and optimize the output filter definition.

The internal oscillator generates the triangular waveform for the PWM charging and

discharging with a constant current an internal capacitor. The switching frequency for each

channel, F_SW, is internally fixed at 150kHz so that the resulting switching frequency at the

load side results in being multiplied by N (number of phases).

The current delivered to the oscillator is typically 25µA (corresponding to the free running

frequency F_SW= 150kHz) and it may be varied using an external resistor (R_OSC) connected

between the OSC pin and SGND or VCC (or a fixed voltage greater than 1.24V). Since the

OSC pin is fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced)

from (into) the pin considering the internal gain of 6KHz/µA.

In particular connecting R_OSCto SGND the frequency is increased (current is sunk from the

pin), while connecting R_OSCto VCC = 12V the frequency is reduced (current is forced into

the pin), according the following relationships:

R

vs. SGND

OSC

1.240V

R_OSC(kΩ)

kHz

µA

7.422 ⋅ 10³

·

---------------------------

----------

-------------------------------

F_SW= 150(kHz) +

⋅ 6

= 150(kHz) +

⇒R_OSC(kΩ) = -----------

R_OSC(kΩ)

F_SW

7.422 ⋅ 10³

Hz

µA

7.422 ⋅ 10³

·

--------

-------------------------------

= 150(kHz) +

⇒R_OSC(kΩ) = -----------------------------------------------------------[kΩ]

F_SW(kHz) – 150(kHz)

R_OSC(kΩ)

R

vs. +12V

OSC

6.456 ⋅ 10⁴

= 150(kHz)–------------------------------- ⇒R_OSC(kΩ) = -----

12V – 1.240V

R_OSC(kΩ)

kHz

µA

-----------------------------------

----------

⋅ 6

F_SW= 150(kHz) –

R_OSC(kΩ)

15

6.456 ⋅ 10⁴

kHz

µA

----------

6

= 150(kHz)–------------------------------- ⇒R_OSC(kΩ) = -----------------------------------------------------------[kΩ]

R_OSC(kΩ)

150(kHz) – F_SW(kHz)

When using the Low-Side MOSFETs current sense, the maximum programmable switching

frequency per phase must be limited to 500kHz to avoid current reading errors causing, as a

consequence, current sharing errors.

Anyway, device power dissipation must be checked prior to design high switching frequency

systems.

54/70

L6714

Oscillator

Figure 21. R_OSCvs. switching frequency

7000

6000

5000

4000

3000

2000

1000

0

25

50

75

100

125

150

Fsw [kHz] Selected

550

500

450

400

350

300

250

200

150

100

50

0

150

250

350

450

550

650

750

850

950

1050

Fsw [kHz] Programmed

55/70

Driver section

L6714

20

Driver section

The integrated high-current drivers allow using different types of power MOS (also multiple

MOS to reduce the equivalent R_dsON), maintaining fast switching transition.

The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for

return. The drivers for the low-side MOSFETs use VCCDRx pin for supply and PGNDx pin

for return. A minimum voltage at VCCDRx pin is required to start operations of the device.

VCCDRx pins must be connected together.

The controller embodies a sophisticated anti-shoot-through system to minimize low side

body diode conduction time maintaining good efficiency saving the use of Schottky diodes:

when the high-side MOSFET turns off, the voltage on its source begins to fall; when the

voltage reaches 2V, the low-side MOSFET gate drive is suddenly applied. When the low-

side MOSFET turns off, the voltage at LGATEx pin is sensed. When it drops below 1V, the

high-side MOSFET gate drive is suddenly applied.

If the current flowing in the inductor is negative, the source of high-side MOSFET will never

drop. To allow the turning on of the low-side MOSFET even in this case, a watchdog

controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side

MOSFET is switched on so allowing the negative current of the inductor to recirculate. This

mechanism allows the system to regulate even if the current is negative.

The BOOTx and VCCDRx pins are separated from IC's power supply (VCC pin) as well as

signal ground (SGND pin) and power ground (PGNDx pin) in order to maximize the

switching noise immunity. The separated supply for the different drivers gives high flexibility

in MOSFET choice, allowing the use of logic-level MOSFET. Several combination of supply

can be chosen to optimize performance and efficiency of the application.

Power conversion input is also flexible; 5V, 12V bus or any bus that allows the conversion

(See maximum duty cycle limitations) can be chosen freely.

56/70

L6714

System control loop compensation

21

System control loop compensation

The control loop is composed by the Current Sharing control loop (See Figure 8) and the

Average Current Mode control loop. Each loop gives, with a proper gain, the correction to

the PWM in order to minimize the error in its regulation: the Current Sharing control loop

equalize the currents in the inductors while the Average Current Mode control loop fixes the

output voltage equal to the reference programmed by VID. Figure 22 shows the block

diagram of the system control loop.

The system Control Loop is reported in Figure 23. The current information I_DROOPsourced

by the DROOP pin flows into R_FBimplementing the dependence of the output voltage from

the read current.

Figure 22. Main control loop

L4

PWM4

1 / 5

L3

PWM3

1 / 5

L2

PWM2

PWM1

C

R

OUT

1 / 5

L1

ERROR AMPLIFIER

V

REF

4 / 5

I

DROOP

I

INFO1

INFO2

INFO3

INFO4

CURRENT SHARING

DUTY CYCLE

COMP

FB

DROOP

CORRECTION

Z (s)

Z

(s)

FB

F

The system can be modeled with an equivalent single phase converter which only difference

is the equivalent inductor L/N (where each phase has an L inductor).The Control Loop gain

results (obtained opening the loop after the COMP pin):

PWM ⋅ Z_F(s) ⋅ (R_DROOP+ Z_P(s))

G_LOOP(s) = –------------------------------------------------------------------------------------------------------------------------

Z_F(s)

A(s)

1

⎛

⎞

[Z_P(s) + Z_L(s)] ⋅ -------------- + 1 + ----------- ⋅ R_FB

⎝

⎠

A(s)

57/70

System control loop compensation

L6714

Where:

●

R_SENSEis the MOSFET R_dsONor the Inductor DCR depending on the sensing element

selected;

R_SENSE

---------------------

⋅ R_FBis the equivalent output resistance determined by the droop

R_DROOP

function;

=

Rg

Z_P(s) is the impedance resulting by the parallel of the output capacitor (and its ESR)

and the applied load R_O;

●

Z_F(s) is the compensation network impedance;

Z_L(s) is the parallel of the N inductor impedance;

A(s) is the error amplifier gain;

V_IN

-- ------------------

4

PWM =

⋅

is the PWM transfer function where ∆V_OSCis the oscillator ramp

5

∆V_OSC

amplitude and has a typical value of 4V.

Removing the dependence from the Error Amplifier gain, so assuming this gain high

enough, and with further simplifications, the control loop gain results:

V

Z

(s)

R

+ R

1 + s ⋅

C

⋅

(R

//R + ESR)

DROOP O

4

5

IN

F

O

DROOP

O

-- --------------------- --------------- ------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------

G

(s) = –

⋅

LOOP

∆V

R

2

OSC

FB

L

R

+ -------

----

-------

s

⋅

C

⋅

--------------------- + C

N ⋅

⋅

ESR + C

⋅

O

+ 1

N ^{+ s ⋅}

N

O

N

R

O

The system Control Loop gain (See Figure 23) is designed in order to obtain a high DC gain

to minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the

desired crossover frequency ω . Neglecting the effect of Z_F(s), the transfer function has one

T

zero and two poles; both the poles are fixed once the output filter is designed (LC filter

resonance ω ) and the zero (ω_ESR) is fixed by ESR and the Droop resistance.

LC

Figure 23. Equivalent control loop block diagram (left) and bode diagram (right).

d V

L / N

V

OUT

PWM

dB

ESR

R

O

C

O

REMOTE BUFFER

64k

G

(s)

LOOP

VID

64k

FBG

FBR

V

K

OUT

Z (s)

F

R [dB]

F

64k

DROOP

FB

COMP

R

F

C

F

VSEN

Z (s)

F

ω

=

ω

LC

F

ω

T

ESR

R

FB

Z

FB

(s)

To obtain the desired shape an R_F- C_Fseries network is considered for the Z_F(s)

implementation. A zero at ω = 1/R_FC_Fis then introduced together with an integrator. This

F

integrator minimizes the static error while placing the zero ω in correspondence with the L-

F

C resonance assures a simple -20dB/dec shape of the gain.

In fact, considering the usual value for the output filter, the LC resonance results to be at

frequency lower than the above reported zero.

58/70

L6714

System control loop compensation

Compensation network can be simply designed placing ω =ω_LCand imposing the cross-over

F

frequency ω as desired obtaining (always considering that ω might be not higher than

T

1/10th of the switching frequency F_SW):

R_FB⋅ ∆V_OSC

5

4

L

------------------------------------ --

----------------------------------------------------------

R_F

=

⋅

⋅ ω ⋅

T

V_IN

N ⋅ (R_DROOP+ ESR)

L

---

C_O

⋅

N

C_F= -----------------------

R_F

21.1

Compensation network guidelines

The Compensation Network design assures to having system response according to the

cross-over frequency selected and to the output filter considered: it is anyway possible to

further fine-tune the compensation network modifying the bandwidth in order to get the best

response of the system as follow (See Figure 24):

●

Increase R_Fto increase the system bandwidth accordingly;

Decrease R_Fto decrease the system bandwidth accordingly;

Increase C_Fto move ω to low frequencies increasing as a consequence the system

F

phase margin.

Having the fastest compensation network gives not the confidence to satisfy the

requirements of the load: the inductor still limits the maximum dI/dt that the system can

afford. In fact, when a load transient is applied, the best that the controller can do is to

“saturate” the duty cycle to its maximum (d_MAX) or minimum (0) value. The output voltage

dV/dt is then limited by the inductor charge / discharge time and by the output capacitance.

In particular, the most limiting transition corresponds to the load removal since the inductor

results being discharged only by V_OUT(while it is charged by d_MAXV_IN-V_OUTduring a load

appliance).

Referring to Figure 24-left, further tuning the Compensation network cannot give any

improvements unless the output filter changes: only modifying the main inductors ot the

output capacitance improves the system response.

Figure 24. R_F-C_Fimpact on bandwidth.

dB

C_F

G_LOOP(s)

K

R_F[dB]

Z_F(s)

R_F

ω_LC

=

ω_F

ω_ESR

ω

ω_T

59/70

Thermal monitor

L6714

22

Thermal monitor

L6714 continuously senses the system temperature through TM pin: depending on the

voltage sensed by this pin, the device sets free the VR_FAN pin as a warning and, after

further temperature increase, also the VR_HOT pin as an alarm condition.

These signals can be used to give a boost to the system fan (VR_FAN) and improve the VR

cooling, or to initiate the CPU low power state (VR_HOT) in order to reduce the current

demand from the processor so reducing also the VR temperature. In a different manner,

VR_FAN can be used to initiate the CPU low power state so reducing the processor current

requirements and VR_HOT to reset the system in case of further dangerous temperature

increase.

Thermal sensors is external to the PWM control IC since the controller is normally not

located near the heat generating components: it is basically composed by a NTC resistor

and a proper biasing resistor R_TM. NTC must be connected as close as possible at the

system hot-spot in order to be sure to control the hottest point of the VR.

Typical connection is reported in Figure 25 that also shows how the trip point can be easily

programmed by modifying the divider values in order to cross the VR_FAN and VR_HOT

thresholds at the desired temperatures.

Both VR_HOT and VR_FAN are active high and open drain outputs. Thermal Monitoring

Output are enabled if Vcc > UVLO

.

VCC

Figure 25. System thermal monitor typical connections.

+5V

Sense Element

(Place remotely, near Hot Spot)

TM

R_TM

TM Voltage - NTC=3300/4250K

4.00

3.80

3.60

3.40

3.20

3.00

2.80

Rtm = 330

2.60

2.40

2.20

2.00

Rtm = 390

Rtm = 470

80

85

90

95

100

105

110

115

120

Temperature [degC]

60/70

L6714

Tolerance band (TOB) definition

23

Tolerance band (TOB) definition

Output voltage load-line varies considering component process variation, system

temperature extremes, and age degradation limits. Moreover, individual tolerance of the

components also varies among designs: it is then possible to define a Manufacturing

Tolerance Band (TOB_Manuf) that defines the possible output voltage spread across the

nominal load line characteristic.

TOB_Manufcan be sliced into different three main categories: Controller Tolerance, External

Current Sense Circuit Tolerance and Time Constant Matching Error Tolerance. All these

parameters can be composed thanks to the RSS analysis so that the manufacturing

variation on TOB results to be:

TOB_Manuf

=

TOB²_Controller+ TOB²_CurrSense+ TOB_T²_CMatching

Output voltage ripple (V_P= V_PP/2) and temperature measurement error (V_TC) must be

added to the Manufacturing TOB in order to get the system Tolerance Band as follow:

TOB = TOB_Manuf+ V_P+ V_TC

All the component spreads and variations are usually considered at 3σ. Here follows an

explanation on how to calculate these parameters for a reference L6714 application.

23.1

Controller tolerance (TOB controller)

It can be further sliced as follow:

●

Reference tolerance. L6714 is trimmed during the production stage to ensure the

output voltage to be within k_VID= 0.5% ( 0.6% for AMD DAC) over temperature and

line variations. In addition, the device automatically adds a -19mV offset (Only for Intel

Mode) avoiding the use of any external component. This offset is already included

during the trimming process in order to avoid the use of any external circuit to generate

this offsets and, moreover, avoiding the introduction of any further error to be

considered in the TOB calculation.

●

Current Reading Circuit. The device reads the current flowing across the MOSFET

RdsON or the inductor DCR by using its dedicated differential inputs. The current

sourced by the VRD is then reproduced and sourced from the DROOP pin scaled down

by a proper designed gain as follow:

R_SENSE

---------------------

⋅ I_OUT

I_DROOP

=

Rg

This current multiplied by the R_FBresistor connected from FB pin vs. the load allows

programming the droop function according to the selected R_L/Rg gain and R_FBresistor.

Deviations in the current sourced due to errors in the current reading, impacts on the output

voltage depending on the size of R_FBresistor. The device is trimmed during the production

stage in order to guarantee a maximum deviation of k_IFB= 1µA from the nominal value.

Controller tolerance results then to be:

2

TOB_Controller

=

[(VID – 19mV) ⋅ k_VID]²+ (k_IDROOP⋅ R_FB

)

61/70

Tolerance band (TOB) definition

L6714

23.2

Ext. current sense circuit tolerance

(TOB CurrSense - Inductor Sense)

It can be further sliced as follow:

●

Inductor DCR Tolerance (k_DCR). Variations in the inductor DCR impacts on the output

voltage since the device reads a current that is different from the real current flowing

into the sense element. As a results, the controller will source a I_DROOPcurrent different

from the nominal. The results will be an AVP different from the nominal in the same

percentage as the DCR is different from the nominal. Since all the sense elements

results to be in parallel, the error related to the inductor DCR has to be divided by the

number of phases (N).

●

Trans-conductance resistors tolerance (k_Rg). Variations in the Rg resistors impacts in

the current reading circuit gain and so impacts on the output voltage. The results will be

an AVP different from the nominal in the same percentage as the Rg is different from

the nominal. Since all the sense elements results to be in parallel, and so the three

current reading circuits, the error related to the Rg resistors has to be divided by the

number of phases (N).

●

NTC Initial Accuracy (k_{NTC_0}). Variations in the NTC nominal value at room

temperature used for the thermal compensation impacts on the AVP in the same

percentage as before. In addition, the benefit of the division by the number of phases N

cannot be applied in this case.

●

NTC Temperature Accuracy (k_NTC). NTC variations from room to hot also impacts on

the output voltage positioning. The impact is bigger as big is the temperature variation

from room to hot (∆T).

All these parameters impacts the AVP, so they must be weighted on the maximum

voltage swing from zero load up to the maximum electrical current (V_AVP). Total error

from external current sense circuit results:

k_D²_CRk²_Rg

2

α ⋅ ∆T ⋅ k_NTC

TOB_CurrSense

=

V²_AVP

⋅

------------- + -------- + k_N²_TC0

+

⎛

⎝

⎞

⎠

--------------------------------------

DCR

N

62/70

L6714

Tolerance band (TOB) definition

23.3

Time constant matching error tolerance (TOB TCMatching)

●

Inductance and capacitance Tolerance (k_L, k_C). Variations in the inductance value and

in the value of the capacitor used for the Time Constant Matching causes over/under

shoots after a load transient appliance. This impacts the output voltage and then the

TOB. Since all the sense elements results to be in parallel, the error related to the time

constant mismatch has to be divided by the number of phases (N).

●

Capacitance Temperature Variations (k_Ct). The capacitor used for time constant

matching also vary with temperature (∆T_C) impacting on the output voltage transients

ad before. Since all the sense elements results to be in parallel, the error related to the

time constant mismatch has to be divided by the number of phases (N).

All these parameters impact the Dynamic AVP, so they must be weighted on the

maximum dynamic voltage swing (I_dyn). Total error due to time constant mismatch

results:

k²_L+ k²_C+ (k_Ct⋅ ∆TC)

TOB_TCMatching

=

V²_AVPDyn

⋅

---------------------------------------------------------

N

23.4

Temperature measurement error (V_TC)

Error in the measured temperature (for thermal compensation) impacts on the output

regulated voltage since the correction form the compensation circuit is not what required to

keep the output voltage flat.

The measurement error (ε_Temp) must be multiplied by the copper temp coefficient (α) and

compared with the sensing resistance (R_SENSE): this percentage affects the AVP voltage as

follow:

α ⋅ ε_Temp

R_SENSE

--------------------------

⋅ V_AVP

V_TC

=

63/70

Layout guidelines

L6714

24

Layout guidelines

Since the device manages control functions and high-current drivers, layout is one of the

most important things to consider when designing such high current applications. A good

layout solution can generate a benefit in lowering power dissipation on the power paths,

reducing radiation and a proper connection between signal and power ground can optimize

the performance of the control loops.

Two kind of critical components and connections have to be considered when layouting a

VRM based on L6714: power components and connections and small signal components

connections.

24.1

Power components and connections

These are the components and connections where switching and high continuous current

flows from the input to the load. The first priority when placing components has to be

reserved to this power section, minimizing the length of each connection and loop as much

as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections

must be a part of a power plane and anyway realized by wide and thick copper traces: loop

must be anyway minimized. The critical components, i.e. the power transistors, must be

close one to the other. The use of multi-layer printed circuit board is recommended.

Figure 26 shows the details of the power connections involved and the current loops. The

input capacitance (C_IN), or at least a portion of the total capacitance needed, has to be

placed close to the power section in order to eliminate the stray inductance generated by the

copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be

connected near the HS drain.

Use proper VIAs number when power traces have to move between different planes on the

PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the

same high-current trace on more than one PCB layer will reduce the parasitic resistance

associated to that connection.

Connect output bulk capacitor as near as possible to the load, minimizing parasitic

inductance and resistance associated to the copper trace also adding extra decoupling

capacitors along the way to the load when this results in being far from the bulk capacitor

bank.

Gate traces must be sized according to the driver RMS current delivered to the power

MOSFET. The device robustness allows managing applications with the power section far

from the controller without losing performances. External gate resistors help the device to

dissipate power resulting in a general cooling of the device. When driving multiple

MOSFETs in parallel, it is suggested to use one resistor for each MOSFET.

64/70

L6714

Layout guidelines

24.2

Small signal components and connections

These are small signal components and connections to critical nodes of the application as

well as bypass capacitors for the device supply (See Figure 26). Locate the bypass

capacitor (VCC, VCCDRx and Bootstrap capacitor) close to the device and refer sensible

components such as frequency set-up resistor R_OSC, offset resistor R_OFFSETand OVP

resistor R_OVPto SGND. Star grounding is suggested: connect SGND to PGND plane in a

single point to avoid that drops due to the high current delivered causes errors in the device

behavior.

VSEN pin filtered vs. SGND helps in reducing noise injection into device and OUTEN pin

filtered vs. SGND helps in reducing false trip due to coupled noise: take care in routing

driving net for this pin in order to minimize coupled noise.

Warning: Boot Capacitor Extra Charge. Systems that do not use

Schottky diodes might show big negative spikes on the

phase pin. This spike can be limited as well as the positive

spike but has an additional consequence: it causes the

bootstrap capacitor to be over-charged. This extra-charge

can cause, in the worst case condition of maximum input

voltage and during particular transients, that boot-to-phase

voltage overcomes the abs. max. ratings also causing device

failures. It is then suggested in this cases to limit this extra-

charge by adding a small resistor in series to the boot diode

(one resistor can be enough for all the three diodes if placed

upstream the diode anode, See Figure 26) and by using

standard and low-capacitive diodes.

Figure 26. Power connections and related connections layout (same for all phases).

To limit C_BOOTExtra-Charge

V_IN

BOOTx

UGATEx

PHASEx

C_IN

L

PHASEx

VCC

L

LGATEx

PGNDx

LOAD

SGND

+Vcc

Remote Buffer Connection must be routed as parallel nets from the FBG/FBR pins to the

load in order to avoid the pick-up of any common mode noise. Connecting these pins in

points far from the load will cause a non-optimum load regulation, increasing output

tolerance.

Locate current reading components close to the device. The PCB traces connecting the

reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up

of any common mode noise. It's also important to avoid any offset in the measurement and,

to get a better precision, to connect the traces as close as possible to the sensing elements.

Symmetrical layout is also suggested. Small filtering capacitor can be added, near the

controller, between V_OUTand SGND, on the CSx- line when reading across inductor to allow

higher layout flexibility.

65/70

Embedding L6714 - Based VR

L6714

25

Embedding L6714 - Based VR

When embedding the VRD into the application, additional care must be taken since the

whole VRD is a switching DC/DC regulator and the most common system in which it has to

work is a digital system such as MB or similar. In fact, latest MB has become faster and

powerful: high speed data bus are more and more common and switching-induced noise

produced by the VRD can affect data integrity if not following additional layout guidelines.

Few easy points must be considered mainly when routing traces in which high switching

currents flow (high switching currents cause voltage spikes across the stray inductance of

the trace causing noise that can affect the near traces):

Keep safe guarding distance between high current switching VRD traces and data buses,

especially if high-speed data bus to minimize noise coupling.

Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that

must walk near the VRD.

Possible causes of noise can be located in the PHASE connections, MOSFET gate drive

and Input voltage path (from input bulk capacitors and HS drain). Also PGND connections

must be considered if not insisting on a power ground plane. These connections must be

carefully kept far away from noise-sensitive data bus.

Since the generated noise is mainly due to the switching activity of the VRM, noise

emissions depend on how fast the current switches. To reduce noise emission levels, it is

also possible, in addition to the previous guidelines, to reduce the current slope by properly

tuning the HS gate resistor and the PHASE snuber network.

66/70

L6714

Package mechanical data

26

Package mechanical data

®

In order to meet environmental requirements, ST offers these devices in ECOPACK

packages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

67/70

Package mechanical data

L6714

Table 13. TQFP64 mechanical data

mm.

inch

Typ

Dim.

Min

Typ

Max

Min

Max

A

A1

A2

b

1.20

0.15

1.05

0.27

0.20

12.20

10.20

6.10

0.0472

0.006

0.05

0.95

0.17

0.09

11.80

9.80

3.50

0.002

0.0374

0.0066

0.0035

0.464

1.00

0.22

0.0393

0.0086

0.0413

0.0086

0.0078

0.480

c

D

12.00

10.00

0.472

0.394

D1

D2

D3

E

0.386

0.401

0.1378

0.2402

7.50

12.00

10.00

0.295

0.472

0.394

11.80

9.80

3.50

12.20

10.20

6.10

0.464

0.386

0.480

0.401

E1

E2

E3

e

0.1378

0.2402

7.50

0.50

0.60

1.00

3.5°

0.295

0.0197

0.0236

0.0393

3.5°

L

0.45

0°

0.75

0.0177

0°

0.0295

L1

k

7 °

7°

ccc

0.080

0.0031

Figure 27. Package dimensions

68/70

L6714

Revision history

27

Revision history

Table 14. Revision history

Date

Revision

Changes

16-Mar-2006

1

Initial release.

Updated K_IDROOP, K_IOFFSETvalues in Table 4: Electrical

characteristics on page 14.

02-Aug-2006

07-Nov-2006

2

3

Updated D2 and E2 exposed tab measures in Table 13:

TQFP64 mechanical data.

69/70

Revision history

L6714

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All ST products are sold pursuant to ST’s terms and conditions of sale.

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型号：	L6714TR
厂家：	ST
描述：	4 phase controller with embedded drivers for Intel VR10, VR11 and AMD 6Bit CPUs 与英特尔VR10 ， VR11和AMD 6位嵌入式处理器驱动4相控制器稳压器开关式稳压器或控制器电源电路开关式控制器驱动
文件：	总70页 (文件大小：679K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L6714TR [STMICROELECTRONICS]

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