L6911ETR [STMICROELECTRONICS]
5 BIT PROGRAMMABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION; 采用同步整流5位可编程降压控制器
| 型号： | L6911ETR |
| 厂家： | 
ST |
| 描述： | 5 BIT PROGRAMMABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION |
| 文件： | 总20页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6911E
5 BIT PROGRAMMABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
■
OPERATING SUPPLY IC VOLTAGE FROM 5V
TO 12V BUSES
■ UP TO 1.3A GATE CURRENT CAPABILITY
■ TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT COMPLIANT WITH VRM 8.5 :
1.050V TO 1.825V WITH 0.025V BINARY
STEPS
SO-20
■
VOLTAGE MODE PWM CONTROL
■ EXCELLENT OUTPUT ACCURACY: ±1%
OVER LINE AND TEMPERATURE
VARIATIONS
ORDERING NUMBERS: L6911E
L6911ETR (Tape and Reel)
■ VERY FAST LOAD TRANSIENT RESPONSE:
FROM 0% TO 100% DUTY CYCLE
■ POWER GOOD OUTPUT VOLTAGE
DESCRIPTION
The device is a power supply controller specifically
designed to provide a high performance DC/DC con-
version for high current microprocessors. A precise 5
bit digital to analog converter (DAC) allows to adjust
the output voltage from 1.050 to 1.825 with 25mV bi-
nary steps.
■
OVERVOLTAGE PROTECTION AND
MONITOR
■ OVERCURRENT PROTECTION REALIZED
USING THE UPPER MOSFET’S RdsON
■
200KHz INTERNAL OSCILLATOR
The high precision internal reference assures the se-
lected output voltage to be within ±1%. The high peak
current gate drive affords to have fast switching to the
external power mos providing low switching losses.
■ OSCILLATOR EXTERNALLY ADJUSTABLE
FROM 50KHz TO 1MHz
SOFT START AND INHIBIT FUNCTIONS
■
The device assures a fast protection against load
overcurrent and load over-voltage. An external SCR
is triggered to crowbar the input supply in case of
hard overvoltage. An internal crowbar is also provid-
ed turning on the low side mosfet as long as the over-
voltage is detected. In case of over-current detection,
the soft start capacitor is discharged an the system
works in HICCUP mode.
APPLICATIONS
■
POWER SUPPLY FOR ADVANCED
MICROPROCESSOR CORE
DISTRIBUTED POWER SUPPLY
■
BLOCK DIAGRAM
Vcc 5V to12V
Vin 5V to12V
VCC
OCSET
PGOOD
SS
BOOT
MONITOR and
PROTECTION
UGATE
OVP
RT
Vo
1.050V to 1.825V
PHASE
LGATE
PGND
GND
OSC
VD0
VD1
VD2
VD3
VD4
-
D/A
+
PWM
+
VSEN
VFB
-
E/A
D98IN957
COMP
November 2001
1/20
L6911E
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Vcc
-V
Vcc to GND, PGND
Boot Voltage
15
V
15
V
BOOT PHASE
V
-V
15
V
HGATE PHASE
OCSET, PHASE, LGATE
ROSC, SS, FB, PGOOD, VSEN
COMP, OVP
-0.3 to Vcc+0.3
V
7
V
6.5
V
PIN CONNECTION
VSEN
OCSET
SS/INH
VID0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RT
OVP
VCC
LGATE
PGND
BOOT
UGATE
PHASE
PGOOD
GND
VID1
VID2
VID3
VID4
COMP
FB
D98IN958
THERMAL DATA
Symbol
Parameter
Value
110
Unit
°C / W
°C
Rth j-amb
Tmax
Thermal Resistance Junction to Ambient
Maximum junction temperature
Storage temperature range
150
Tstorage
-40 to 150
0 to 125
°C
T
J
Junction temperature range
°C
2/20
L6911E
PIN FUNCTION
N
1
2
Name
Description
VSEN Connected to the output voltage is able to manage over-voltage conditions and the PGOOD signal.
OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit protection.
The internal 200µA current generator sinks a current from the drain through the external resistor.
The Over-Current threshold is due to the following equation:
IOCSET ROCSET
IP = ------------------------------------------------
RDSon
3
SS/INH The soft start time is programmed connecting an external capacitor from this pin and GND. The
µ
internal current generator forces through the capacitor 10 A.
This pin can be used to disable the device forcing a voltage lower than 0.4V
4 - 8 VID0 - 4 Voltage Identification Code pins. These input are internally pulled-up and TTL compatible. They are
used to program the output voltage as specified in Table 1 and to set the overvoltage and power
good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
9
COMP This pin is connected to the error amplifier output and is used to compensate the voltage control
feedback loop.
10
FB
This pin is connected to the error amplifier inverting input and is used to compensate the voltage
control feedback loop.
11
12
GND
All the internal references are referred to this pin. Connect it to the PCB signal ground.
PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above
specified threshlds.
If not used may be left floating.
13
PHASE This pin is connected to the source of the upper mosfet and provides the return path for the high side
driver. This pin monitors the drop across the upper mosfet for the current limit.
14
15
UGATE High side gate driver output.
BOOT Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet.
Connect through a capacitor to the PHASE pin and through a diode to Vcc (catode vs boot).
16
PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in order to
reduce the noise injection into the device
17
18
LGATE This pin is the lower mosfet gate driver output
VCC
Device supply voltage. The operative supply voltage range is from 4.5 to 12V.
DO NOT CONNECT V TO 12V IF V IS 5V.
IN
CC
19
20
OVP
Over voltage protection. If the output voltage reach the 15% above the programmed voltage this pin
is driven high and can be used to drive an external SCR that crowbar the supply voltage.
If not used, it may be left floating.
RT
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the external
frequency is increased according to the equation:
5 106
f S = 200kHz + --------------------
RT(kΩ )
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to the
equation:
4 107
f S
200kHz
– --------------------
=
R
k
T( Ω)
If the pin is not connected, the switching frequency is 200KHz.
µ
The voltage at this pin is fixed at 1.23V. Forcing a 50 A current into this pin, the built in oscillator
stops to switch.
3/20
L6911E
ELECTRICAL CHARACTERISTIC
(Vcc=12V; T=25°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
Vcc SUPPLY CURRENT
Icc
Vcc Supply current
UGATE and LGATE open
5
mA
POWER-ON
Turn-On Vcc threshold
Turn-Off Vcc threshold
Rising V threshold
V
= 4.5V
= 4.5V
4.6
V
V
OCSET
V
3.6
OCSET
1.26
10
V
OCSET
Iss
OSCILLATOR
Free running frequency
Soft Start Current
µA
RT = OPEN
180
-15
200
1.9
220
15
KHz
%
Total Variation
6 KΩ< R to GND <200 KΩ
T
Ramp amplitude
RT = OPEN
Vp-p
∆Vosc
REFERENCE AND DAC
DACOUT Voltage
Accuracy
-1
1
%
V
VID0, VID1,VID2, VID3,
VID25mV see Table1;Tamb=0 to
70°C
VID Pull-Up voltage
ERROR AMPLIFIER
3.1
DC Gain
88
15
10
dB
GBWP Gain-Bandwidth Product
MHz
SR
GATE DRIVERS
High Side Source
Slew-Rate
COMP=10pF
µ
V/ S
1
1.3
A
I
V
V
- V
=12V,
PHASE
UGATE
BOOT
Current
- V
= 6V
UGATE
PHASE
R
High Side Sink
Resistance
V
-V =12V,
BOOT PHASE
2
4
3
Ω
A
UGATE
I
= 300mA
UGATE
Low Side Source
Current
0.9
1.1
1.5
120
I
Vcc=12V, V
= 6V
LGATE
LGATE
Low Side Sink
Resistance
Ω
R
Vcc=12V, I
= 300mA
LGATE
LGATE
Output Driver Dead Time
PHASE connected to GND
nS
PROTECTIONS
Over Voltage Trip (V
DACOUT)
/
V
V
Rising
SEN
117
200
120
230
%
SEN
I
OCSET Current Source
OVP Sourcing Current
= 4.5V
OCSET
170
60
µ
A
OCSET
I
V
> OVP Trip, V =0V
OVP
mA
OVP
SEN
POWER GOOD
Upper Threshold
(V /DACOUT)
V
V
Rising
Falling
108
88
110
90
2
112
92
%
%
%
V
SEN
SEN
SEN
Lower Threshold
(V /DACOUT)
SEN
Hysteresis
(V /DACOUT)
Upper and Lower threshold
= -5mA
SEN
V
PGOOD Voltage Low
I
0.5
PGOOD
PGOOD
4/20
L6911E
Table 1. VID Setting
VID4
Output
Voltage (V)
VID4
(25mV)
Output
VID3 VID2
(25mV)
VID1
VID0
VID3
VID2 VID1
VID0
Voltage (V)
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Device Description
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections
for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed
to drive N Channel Mosfets in a synchronous-rectified buck topology. The device works properly with Vcc rang-
ing from 5V to 12V and regulates the output voltage starting from a 1.26V power stage supply voltage (Vin). The
output voltage of the converter can be precisely regulated, programming the VID pins, from 1.050V to 1.825V
with 25mV binary steps, with a maximum tolerance of ±1% over temperature and line voltage variations. The
device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator
that is adjustable from 50kHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 10V/
ms slew rate which permits high converter bandwidth for fast transient performance. The resulting PWM duty
cycle ranges from 0% to 100%. The device protects against over-current conditions entering in HICCUP mode.
The device monitors the current by using the r
rent sensing resistor.
of the upper MOSFET which eliminates the need for a cur-
DS(ON)
The device is available in SO20 package.
Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is tipically 50µA (Fsw=200KHz) and may be varied using an external resistor (R ) connected between
T
RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied
proportionally to the current sinked (forced) from (into) the pin.
In particular connecting it to GND the frequency is increased (current is sinked from the pin), according to the
following relationship:
6
4.94 10
f
= 200kHz + -------------------------
S
R (kΩ)
T
Connecting RT to VCC=12V or to VCC=5V the frequency is reduced (current is forced into the pin), according
to the following relationships:
5/20
L6911E
7
4.306 10
=
+ -----------------------------
f
200kHz
V
CC
= 12V
S
R (kΩ)
T
7
15 10
=
+ --------------------
f
200kHz
V
CC
= 5V
S
R (kΩ)
T
Switching frequency variations vs. R are reported in Fig.1.
T
Note that forcing a 50µA current into this pin, the device stops switching because no current is delivered to the
oscillator.
Figure 1.
10000
1000
100
RT to GND
10
RT to VCC=12V
RT to VCC=5V
10
10 0
1000
Frequency [kH z]
Digital to Analog Converter
The built-in digital to analog converter allows the adjustment of the output voltage from 1.050V to 1.825V with
25mV binary steps as shown in the previous table 1. The internal reference is trimmed to ensure the precision
of 1%.
The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These
are TTL compatible inputs of an internal DAC that is realised by means of a series of resistors rpoviding a par-
tition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise
point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the
set-point of the error amplifier). Internal pull-ups are provided (realized with a 5µA current generator); in this
way, to program a logic ”1” it is enough to leave the pin floating, while to program a logic ”0” it is enough to short
the pin to GND.
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over-
voltage protection (OVP) thresholds.
Soft Start and Inhibit
At start-up a ramp is generated charging the external capacitor C by means of a 10µA constant current, as
SS
shown in figure 2.
When the voltage across the soft start capacitor (V ) reaches 0.5V the lower power MOS is turned on to dis-
SS
charge the output capacitor. As V reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upper
SS
6/20
L6911E
MOS begins to switch and the output voltage starts to increase.
The VSS growing voltage initially clamps the output of the error amplifier, and consequently VOUT linearly in-
creases, as shown in figure 2. In this phase the system works in open loop. When VSS is equal to VCOMP the
clamp on the output of the error amplifier is released. In any case another clamp on the non-inverting input of
the error amplifier remains active, allowing to VOUT to grow with a lower slope (i.e. the slope of the VSS voltage,
see figure 2). In this second phase the system works in closed loop with a growing reference. As the output
voltage reaches the desired value VPROG, also the clamp on the error amplifier input is removed, and the soft
start finishes. Vss increases until a maximum value of about 4V.
The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins
are not above their own Turn-On thresholds; in this way the device starts switching only if both the power sup-
plies are present. During normal operation, if any under-voltage is detected on one of the two supplies, the SS
pin is internally shorted to GND and so the SS capacitor is rapidly discharged.
The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external MOSFETS are kept
off.
Figure 2. Soft Start
Vcc Turn-on threshold
Vcc
Vin
Vin Turn-on threshold
1V
Vss
LGATE
Vout
to G ND
0.5V
Timing Diagram
Aquisition: CH1 = PHASE; CH2 = V
;
OUT
CH3 = PGOOD; CH4 = V
SS
Driver Section
The driver capability on the high and low side drivers allows to use different types of power MOS (also multiple
MOS to reduce the R ), maintaining fast switching transition.
DSON
The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use many kinds of mos-
fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is
avoided if the PHASE pin is over about 500mV. The upper mos is in any case turned-on after 200nS from the
low side turn-off.
The peak current is shown for both the upper (fig. 3) and the lowr (fig. 4) driver at 5V and 12V. a 4nF capacitive
load has been used in these measurements.
For the lower driver, the source peak current is 1.1A @ Vcc=12V and 500mA @ Vcc=5V, and the sink peak
current is 1.3A @ Vcc=12V and 500mA @ Vcc=5V.
Similary, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase=12V and 600mA @ Vboot-
Vphase =5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase =5V.
7/20
L6911E
Figure 3. High Side driver peak current.
Vboot-Vphase=12V (left) Vboot-Vphase=5V (right) CH1 = High Side Gate CH4 = Inductor Current
Figure 4. Low Side driver peak current.
Vcc=12V (left) Vcc=5V (right)CH1 = Low Side Gate CH4 = Inductor Current
Monitor and Protection
The output voltage is monitored by means of pin 1 (VSEN). If it is not within ±10% (typ.) of the programmed
value, the powergood output is forced low.
The device provides overvoltage protection, when the output voltage reaches a value 17% (typ.) greater than
the nominal one. If the output voltage exceed this threshold, the OVP pin is forced high (5V) and the lower driver
is turned on as long as the over-voltage is detected. The OVP pin is capable to deliver up to 60mA (min)in order
to trigger an external SCR connected to burn the input fuse. The low-side mosfet turn-on implement this function
when the SCR is not used and helps in keeping the ouput low.
To perform the overcurrent protection the device compares the drop across the high side MOS, due to its
RDSON, with the voltage across the external resistor (R ) connected between the OCSET pin and drain of
OCS
the upper MOS. Thus the overcurrent threshold (I ) can be calculated with the following relationship:
P
IOCS ROCS
IP = --------------------------------
RDSON
where the typical value of I
is 200µA.
OCS
To calculate the R
value it must be considered the maximum R
(also the variation with temperature)
OCS
DSON
and the minimum value of I . To avoid undesirable trigger of overcurrent protection this relationship must be
OCS
satisfied:
8/20
L6911E
∆l
I ≥ I
+ ---- = I
2
P
OUTMAX
OUTMAX
PEAK
where ∆I is the inductance ripple current and I
is the maximum output current.
µ
In case of output short circuit the soft start capacitor is discharged with constant current (10 A typ.) and when
the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is al-
ways active and if such kind of event occours, the device turns off both mosfets, and the SS capacitor is di-
charged again after reaching the upper threshold of about 4V. The system is now working in HICCUP mode, as
shown in figure 5a. After removing the cause of the over-current, the device restart working normally without
power supplies turn off and on.
Figure 5.
9
L=1.5µH, Vin=12V
8
L=2µH,
Vin=12V
7
6
µ
L=3 H,
5
4
3
2
1
0
Vin=12V
L=1.5µH,
Vin=5V
L=2µH,
Vin=5V
L=3µH, Vin=5V
0.5
1.5
2.5
3.5
Output Voltage [V]
a: Hiccup Mode
b: Inductor Ripple Current vs. Vout
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current ∆I between 20% and 30% of the maximum output current. The inductance value can be cal-
L
culated with this relationship:
VIN
V
V OUT
OUT
–
----------------------------- --------------
L =
fs ∆IL
is the switching frequency, V is the input voltage and V is the output voltage. Figure 5b shows
OUT
VIN
Where f
SW
IN
the ripple current vs. the output voltage for different values of the inductor, with vin=5V and Vin=12V.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. If the compensation network is well designed, the device is able to open or
close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to
change its current from initial to final value. Since the inductor has not finished its charging time, the output cur-
rent is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
The response time to a load transient is different for the application or the removal of the load: if during the ap-
plication of the load the inductor is charged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-
∆
imate response time for I load transient in case of enough fast compensation network response:
9/20
L6911E
∆
∆
I
L
I
L
V
= ------------------------------
= ---------------
t
t
removal
application
–
V
V
IN
OUT
OUT
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the max-
imum input voltage available.
Output Capacitor
Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the
range of tenth A/µsec, the output capacitor is a basic component for the fast response of the power supply. In
fact for first few microseconds they supply the current to the load. The controller recognizes immediately the
load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value.
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
∆
V
∆
= I
· ESR
OUT
OUT
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
2
∆I
L
OUT
∆
= --------------------------------------------------------------------------------------------
V
OUT
(
–
V
)
OUT
2 C
V
D
OUT
INMIN
MAX
Where D
is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop
MAX
during load transient and the lower is the output voltage static ripple.
Input Capacitor
The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must
have a low ESR to minimize the losses. The rms value of this ripple is:
I
= I
D (1 – D)
OUT
rms
Where D is the duty cycle. The equation reaches its maximum value with D=0.5. The losses in worst case are:
2
P = ESR I
rms
Compensation network design
The control loop is a voltage mode (figure 7) that uses a droop function to satisfy the requirements for a VRM
module, reducing the size and the cost of the output capacitor.
This method ”recovers” part of the drop due to the output capacitor ESR in the load transient, introducing a de-
pendence of the output voltage on the load current: at light load the output voltage will be higher than the nom-
inal level, while at high load the output voltage will be lower than the nominal value.
10/20
L6911E
Figure 6. Output transient response without (a) and with (b) the droop function
ESR DROP
ESR DROP
VMAX
VDROOP
VNOM
VMIN
(a)
(b)
As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) propor-
tional to the output current. Since a sense resistor is not present, the output DC current is measured by using
Ω
the intrinsic resistance of the inductance (a few m ). So the low-pass filtered inductor voltage (that is the induc-
tor current) is added to the feedback signal, implementing the droop function in a simple way. Referring to the
schematic in figure 7, the static characteristic of the closed loop system is:
R
R8 // R9
L
+
R3 R8 // R9
------------------------------------- – ---------------------------------- -
I
OUT
=
+
V
V
V
OUT
PROG
PROG
R8
R2
Where V
is the output voltage of the digital to analog converter (i.e. the set point) and R is the inductance
L
PROG
+
resistance. The second term of the equation allows a positive offset at zero load (∆V ); the third term introduces
the droop effect (∆V ). Note that the droop effect is equal the ESR drop if:
DROOP
R
R8 // R9
L
---------------------------------- - = ESR
R8
Figure 7. Compensation network
V I
N
V C O M
P
V P H A S E
L 2
R
L
V O U T
P W M
E
S R
R 8
C 1 8
Z F
C 6 - 1 5
C 2 0
R 4
R 9
R 3
C 25
V
P
R O
G
Z I
R 2
Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired
droop effect as follow:
■
Ω
Choose a value for R2 in the range of hundreds of K to obtain realistic values for the other
components.
11/20
L6911E
■
From the above equations, it results:
R8 =
+
R
I
MAX
∆V R2
V
L
----------------------- ---------------------------
;
∆V
DROOP
PROG
∆V
1
DROOP
--------------------------- ------------------------------------ -
=
R9 R8
;
R
I
∆V
L
MAX
DROOP
+ ---------------------------
1
R
I
MAX
L
Where I
is the maximum output current.
MAX
■ The component R3 must be chosen in order to obtain R3<<R8//R9 to permit these and successive
simplifications.
Therefore, with the droop function the output voltage decreases as the load current increases, so the DC output
impedance is equal to a resistance R . It is easy to verify that the output voltage deviation under load tran-
OUT
sient is minimum when the output impedance is constant with frequency.
To choose the other components of the compensation network, the transfer function of the voltage loop is con-
sidered. To simplify the analysis is supposed that R3 << Rd, where Rd = (R8//R9).
Figure 8. Compensation network definition
|A v|
2
f
L C
f
C E
f
E C
f
C C
f
f
f
|R |
R
0
f
D
f
2
f
1
f
3
|G loo p|
0
G
fc
Compensati onNetworkS ingularity
f
= 1/ 2π R 4 C20
ConverterS ingularity
f
f
= 1 / 2π
LC
doublepole
ESRzero
1
LC
f
f
= 1/ 2π (R3 + R 4) C 20
= 1/ 2π ESR
C
2
CE
OUT
ESR Cceramic
=
=
π
R
C
C
1/ 2
3
25
25
f
=
π
Introduced by
1/ 2
3
EC
f
π
Rd
1 / 2
d
f
= 1/ 2π Rceramic Cceramic
CeramicCap acitor
CC
The transfer function may be evaluated neglecting the connection of R8 to PHASE because, as will see later,
this connection is important only at low frequencies. So R4 is considered connected to VOUT. Under this as-
sumption, the voltage loop has the following transfer function:
12/20
L6911E
Z (s )
Zf(s)
--------------
Zi(s)
Vin
C
=
=
= ---------------- -------------------------------------
Gloop(s)
Av(s) R(s)
Av(s)
Where Av(s)
∆V
Z (s) + Z (s)
osc
C
L
Where Z (s) and Z (s) are the output capacitor and inductor impedance respectively.
C
L
The expression of Z (s) may be simplified as follow:
I
2 R3
1
s
1
s
-------
+
(τ + τ ) +
s
τ
τ
1 d
Rd 1
s
-- C20
R4 +
R3
-- C25
Rd
1
d
R
d
Z (s ) = ---------------------------------- + ----------------------------------------------------- - = -------------------------------------------------------------------------------------------------- -=
I
(1 + s τ ) (1 + s τ )
1
1
+ --
s
2
d
Rd + -- C25
+
R4
C20 R3
s
R3
1 + s------- τ
(1 + s τ )
1
d
R
d
-------------------------------------------------------------------- -
=
Rd
(
+
τ ) (
+
τ )
1
s
1
s
2
d
τ
τ
= (R4+R3)×C20 and = Rd×C25.
2
τ
Where:
= R4×C20,
1
d
The regulator transfer function became now:
(
+
τ ) (
+
τ )
1
s
1
s
2
d
------------------------------------------------------------------------------------------------------
R(s) ≈
R3
+ -------
+
(1 s τ )
1
s C18 R
1
s
τ
d
d
R
d
Figure 8 shows a method to select the regulator components (please note that the frequencies f and f cor-
EC
CC
responds to the singularities introduced by additional ceramic capacitors in parallel to the output main electro-
lytic capacitor).
■
τ
To obtain a flat frequency response of the output impedance, the droop time constant has to be equal
d
to the inductor time constant (see the note at the end of the section):
L
L
τ
=
= ------ = τ
= -----------------------
(R R )
R
C25
C25
d
d
L
R
L
L
d
■
To obtain a constant -20dB/dec Gloop(s) shape the singularity f and f are placed in proximity of f
CE
1
2
and f respectively. This implies that:
LC
f
f
f
LC
LC
2
--- = --------
R4 =
-------- –
R3
1
1
f
f
f
CE
1
CE
f1= f
C20 = -- π R4 f
CE
CE
2
■ To obtain a Gloop bandwidth of f , results:
C
f C
f LC
C20 C25
VIN C20 // C25
VIN
C18 = ----------------- ---------------------------- -------
∆Vosc C20 + C25 fC
G0 fLC = 1 fC
G0 = A0 R0 = ----------------- ----------------------------- = -------
∆Vosc
C18
f LC
Note.
To understand the reason of the previous assumption, the scheme in figure 9 must be considered.
In this scheme, the inductor current has been substituted by the load current, because in the frequencies range
of interest for the Droop function these current are substantially the same and it was supposed that the droop
network don’t represent a charge for the inductor.
13/20
L6911E
Figure 9. Voltage regulation with droop function block scheme
Vcom p
Vout
Av(s)
R(s)
1
+
s
τ
τ
L
d
Iout
R
OUT
1 + s
It results:
+
+
sτ
1
sτ
G
1
V
L
LOOP
L
o
------------------ -----------------------------
------------------
= ---------------- =
=
R
Z
R
OUT
d
OUT
+ τ
+
+ τ
1 s
d
I
1
s
1
G
LOAD
d
LOOP
Because in the interested range |Gloop|>>1.
To obtain a flat shape, the relationship considered will naturally follow.
VRM Demo Board Description
Figure 10 shows the schematic circuit of the VRM evaluation board. The design has been developed for a VRM
8.5 Flexible Motherboard applicaton delivering up to 28.5A.
An additional circuit sense a Vtt bus (1.2V typ.) and generate a 2.5mS (typ.) delayed Vtt_PWRGD signal when
this rail is over 1.1V. The assertion of the Vtt_PWRGD signal enables the device together with the ENOUT input.
Figure 10. Schematic Circuit
L1
F1
+5 VIN
D1
C10
R7
C1-3
C11
+12Vcc
15
19
R14
VCC
GND
VID0
VID1
VID2
VID3
VID4
OSC
SS
OCSET
18
11
4
2
C12
UGATE
14
13
VID0
Q1,Q2
L2
PHASE
LGATE
VID1
VOUTCORE
Vss
5
VID2
U1
L6911E17
6
VID3
Q3,Q4,Q5
D2
C4-9
R15
R6
7
PGND
PGOOD
VSEN
16
VID25mV
8
R1
12
20
3
PWRGD
1
9
10
C13
R8
C18
Q7
R3
R4
R9
C20
C17
C19
R5
C14
Vdd
RESET
5
R2
6
8
2
NOT RESET
NOT RESIN
GND
UZ
TLC7701
D3
Vtt_PGOOD
4
CT
3
Vtt_sense
SENSE
R13
7
1
C15
C16
CONTRO L
L6911ECONNECTOR EVALUATIONKIT REV. 1 .1
OUTEN
R10
R12
Q6
R11
14/20
L6911E
Efficiency
The measured efficiency versus load current at different output voltages is shown in figure 11. In the application
two Mosfets STS12NF30L (30V, 8.5mΩ typ with V =12V) connected in parallel are used for the High Side,
GS
while three of them are used for the Low Side.
Figure 11. Efficiency vs. load current
90
80
70
Vout = 1.825V
60
Vout = 1.225V
50
40
Vout = 1.500V
0
5
10
15
20
25
OutputCurrent [A]
Inductor design
µ
Since the maximum output current is 28.5A, to have a 20% ripple (5A) the inductor chosen is 1.5 H.
Output Capacitor
In the demo six OSCON capacitors, model 6SP680M, are used, with a maximum ESR equal to 12mΩ each.
Ω
Therefore the resultant ESR is of 2m . For load transient of 28.5A in the worst case the voltage drop is of:
∆
Vout = 28.5 * 0.002 = 57mV
The voltage drop due to the capacitor discharge during load transient, considering that the maximum duty cicle
is equal to 100% results in 46.5mV with 1.85V of programmed output.
Input Capacitor
For I =28.5A and with D=0.5(worst case for input current ripple), Irms is equal to 17.8A. Three OSCON elec-
OUT
trolityc capacitors 6SP680M, with a maximum ESR equal to 12mΩ, are chosen to substain the ripple. So the
losses in worst case are:
2
rms
=
=
(1.25(670)m
ESR I
Over-Current Protection
Substituting the demo board parameters in the relationship reported in the relative section, (I
=170µA;
OCSMIN
Ω
Ω
=1k .
OCS
I =33A; R
P
=3m ) it results that R
DSONMAX
15/20
L6911E
Connector Pin Orientation
Pin #
1
Row A
5Vin
Pin #
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
Row B
5Vin
2
5Vin
5Vin
3
5Vin
5Vin
4
5Vin
5Vin
5
12Vin
12Vin
12Vin
No Contact
VID1
6
12Vin
7
Reserved
VID0
8
9
VID2
VID3
10
11
12
13
14
15
16
17
VID4 (25mV)
OUTEN
PWRGD
Ishare
V
V
TT
TT_PWRGD
Vss
Vss
Vss
Vcc
Vcc
CORE
CORE
Vcc
CORE
Vss
Vss
Vcc
Vcc
CORE
CORE
Mechanical Key
18
19
20
21
22
23
24
25
Vss
Vcc
33
32
31
30
29
28
27
26
Vss
Vcc
CORE
CORE
CORE
CORE
CORE
Vss
Vss
Vcc
Vcc
CORE
Vss
Vss
Vcc
Vcc
CORE
Vss
Vss
Vcc
Vcc
CORE
16/20
L6911E
PCB AND COMPONENTS LAYOUT
Figure 12. PCB and Components Layouts
Component Side Silkscreen
Component Side
Internal Ground Plane
Solder Side Silkscreen
Figure 13. PCB and Components Layouts
Internal Layer
Figure 14. PCB and Components Layouts
Solder Side
17/20
L6911E
PART LIST
Resistors
R1
R2
R3
R4
R5
R6
R7
R8
R9
Not Mounted
470K
1K
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
1%
82
Not Mounted
20K
680
13K
100K
6.8K
R10
R11
R12
R13
R14
R15
1%
1%
10K
1K
10K
Ω
8.2
1K
Capacitors
C1-C3
C4-C9
µ
OSCON 6SP680M
Radial 10x10.5
680 F- 6.3V
µ
OSCON 4SP820M
OSCON 6SP680M
Radial 10x10.5
Radial 10x10.5
820 F – 4V or
µ
680 F – 6.3V
C10
C11,C13-C16
C12
1nF
100nF
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
SMD 0805
1µF
C17
47nF
C18
3.3nF
C19
Not Mounted
100nF
C20
Magnetics
L1
L2
1.5µH
1.8µH
T44-52 Core, 7T - 18AWG
T50-52B Core, 8T – 16AWG
Transistors
Q1-Q5
STS12NF30L or
FDS6670
STMicroelectronics
Fairchild
SO8
SO8
Q6
Q7
Signal NPN BJT
Signal MOSFET
SOT23
SOT23
Diodes
D1
D2
D3
1N4148
SOT23
SMB
STPS3L25U
STMicroelectronics
Ics
U1
U2
L6911E
STMicroelectronics
Texas Instruments
SO20
SO8
TLC7701QD
Fuse
F1
251015A-15A
Littlefuse
AXIAL
18/20
L6911E
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A
A1
B
C
D
E
e
2.35
0.1
2.65 0.093
0.3 0.004
0.104
0.012
0.020
0.013
0.512
0.299
0.33
0.23
12.6
7.4
0.51 0.013
0.32 0.009
13
0.496
0.291
7.6
1.27
0.050
H
h
10
0.25
0.4
10.65 0.394
0.75 0.010
0.419
0.030
0.050
L
1.27 0.016
SO20
K
0°(min.)8°(max.)
L
h x 45°
A
A1
K
B
C
e
H
D
20
11
E
1
10
SO20MEC
19/20
L6911E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights ofthird partieswhich may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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20/20
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