L9823013TR_技术文档

L9823

Octal low-side driver for bulb, resistive and inductive loads with

serial input control, output protection and diagnostic

Datasheet - production data

 Output status data available on the SPI using

8-bit I/O protocol up to 3.0 MHz

 Low standby current with reset = low (typ.

35 µA @ VDD)

 Open load detection (outputs off)

 Single V logic supply

DD

'!0'03ꢀꢀꢁꢂꢃ

 High EMS immunity and low EME (controlled

SO24

output slopes)

 Full functionality of the remaining device at

negative voltage drop on outputs (-1.5 V or

-3.0 A)

 Output mode programmable for sustained

Features

current limit or shutdown

 Outputs current capability up to 0.5 A

 Cascadable SPI control for outputs

 Reset function with reset signal or

Description

L9823 is a octal low-side driver circuit, dedicated

for automotive applications.

undervoltage at V

DD

 Programmable intrinsic output voltage

Output voltage clamping is provided for flyback

current recirculation, when inductive loads are

driven.

clamping at typ. 50 V for inductive switching

 Overcurrent shutdown with latch-off for every

write cycle (SFPD = low)

Chip select and cascadable serial 8-bit Interface

for outputs control and diagnostic data transfer.

 Independent thermal shutdown of outputs

(SOA Protection)

Table 1. Device summary

Order code

Package

Packing

L9823

SO24

Tube

E-L9823

September 2013

DocID7791 Rev 7

1/19

This is information on a product in full production.

www.st.com

Contents

L9823

Contents

1

Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

1.2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

2.4

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power outputs characteristics for flyback current, outputs short circuit

protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1

3.2

3.3

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output stages control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4

5

6

Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/19

DocID7791 Rev 7

L9823

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Outputs Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Diagnostic for outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

DocID7791 Rev 7

3/19

3

List of figures

L9823

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Output control register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Timing of the serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Pulse diagram to read the outputs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Structure of the outputs status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typical application circuit diagram for the L9823 circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SO24 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4/19

DocID7791 Rev 7

L9823

Block diagram and pins description

1

Block diagram and pins description

1.1

Block diagram

Figure 1. Block diagram

ꢀꢆ

$$

3&0$

ꢀꢅ

/54ꢁ

ꢂꢄ

ꢉ

/,ꢁ

ꢋ

6

ꢌ

$'

)

/,

#3"

ꢀꢁ

'ATE

#ONTROL

1ꢁ

1ꢀ

1ꢂ

1ꢃ

1ꢄ

1ꢅ

1ꢆ

1ꢇ

ꢋ

)

ꢁ

ꢉ

3#"

/VER

4EMPERATURE

$ETECT

ꢉ

ꢋ

/4ꢁ

ꢌ

#(ꢁ

3#,+

ꢃ

$IAGꢁ

$IAGꢀ

$IAGꢂ

$IAGꢃ

$IAGꢄ

$IAGꢅ

$IAGꢆ

$IAGꢇ

/54ꢀ

ꢂꢃ

/54ꢂ

ꢀꢄ

/54ꢃ

ꢀꢃ

/54ꢄ

ꢀꢂ

/54ꢅ

ꢀꢀ

/54ꢆ

ꢂ

/54ꢇ

ꢀ

1ꢀ

#(ꢀ

#(ꢂ

#(ꢃ

#(ꢄ

#(ꢅ

#(ꢇ

$IAGꢀ

1ꢂ

$IAGꢂ

3)

ꢄ

1ꢃ

$IAGꢃ

1ꢄ

$IAGꢄ

3/

ꢈ

1ꢅ

$IAGꢅ

1ꢆ

$IAGꢆ

2ESET

ꢂꢂ

1ꢇ

$IAGꢇ

5NDERVOLTAGE

2%3%4

ꢅ ꢉꢊ

ꢀꢇ ꢉ ꢂꢁ

'.$

'!0'03ꢀꢀꢁꢄꢀ

1.2

Pins description

Figure 2. Pins connection (top view)

/54ꢇ

/54ꢆ

3#,+

3)

ꢀ

ꢂꢄ

ꢂꢃ

ꢂꢂ

ꢂꢀ

ꢂꢁ

ꢀꢈ

ꢀꢊ

ꢀꢇ

ꢀꢆ

ꢀꢅ

ꢀꢄ

ꢀꢃ

/54ꢁ

/54ꢀ

2%3%4

.ꢍ#ꢍ

ꢂ

ꢃ

ꢄ

'.$

3/

ꢅ

'.$

ꢆ

'.$

ꢇ

'.$

ꢊ

'.$

ꢈ

6$$

#3"

/54ꢅ

/54ꢄ

ꢀꢁ

ꢀꢀ

ꢀꢂ

3&0$

/54ꢂ

/54ꢃ

'!0'03ꢀꢀꢁꢄꢅ

DocID7791 Rev 7

5/19

18

Block diagram and pins description

L9823

Table 2. Pins description

Description

N#

1

2

OUT7 Output 7

OUT6 Output 6

The system clock pin (SCLK) clocks the internal shift registers of the L9823. The serial input

pin (SI) accepts data into the input shift register on the falling edge of the SCLK signal while

the serial output pin (SO) shifts data information out of the shift register on the rising edge of

the SCLK signal. False clocking of the shift register must be avoided to guarantee validity of

SCLK data. It is essential that the SCLK pin be in a logic low state whenever chip select bar pin

(CSB) makes any transition. For this reason, it is recommended though not necessary, that

the SCLK pin be kept in a low logic state as long as the device is not accessed (CSB in logic

high state). When CSB is in a logic high state, any signal at the SCLK and SI pin is ignored

and SO is tri-stated (high-impedance).

3

This pin is for the input of serial instruction data. SI information is read in on the falling edge of

SCLK. A logic high state present on this pin when the SCLK signal rises will program a

specific output OFF, and in turn, turns OFF the specific output on the rising edge of the CSB

signal. Conversely, a logic low state present on the SI pin will program the output ON, and in

turn, turns ON the specific output on the rising edge of the CSB signal. To program the eight

4

SI

outputs of the L9823 ON or OFF, an eight bit serial stream of data is required to be entered

into the SI pin starting with Output 7, followed by Output 6, Output 5, etc., to Output 0. For

each rise of the SCLK signal, with CSB held in a logic low state, a databyte instruction (ON or

OFF) is loaded into the shift register per the databyte SI state. The shift register is full after

eight bits of information have been entered. To preserve data integrity, care should be taken to

not transition SI as SCLK transitions from a low-to-high logic state.

5

6

7

8

GND

The serial output (SO) pin is the tri-stateable output from the shift register. The SO pin

remains in a high impedance state until the CSB pin goes to a logic low state. The SO data

reports the drain status, either high or low. The SO pin changes state on the rising edge of

SCLK and reads out on the falling edge of SCLK. When an output is OFF and not faulted, the

corresponding SO databyte is a high state. When SO an output is ON, and there is no fault,

the corresponding databyte on the SO pin will be a low logic state. The SI / SO shifting of data

follows a first-in-first-out protocol with both input and output words transferring the Most

Significant Bit (MSB) first. The SO pin is not affected by the status of the Reset pin.

9

SO

The system MCU selects the L9823 to be communicated with through the use of the CSB pin.

Whenever the pin is in a logic low state, data can be transferred from the MCU to the L9823

and vise versa. Clocked-in data from the MCU is transferred from the L9823 shift register and

latched into the power outputs on the rising edge of the CSB signal. On the falling edge of the

CSB signal, drain status information is transferred from the power outputs and loaded into the

device's shift register. The CSB pin also controls the output driver of the serial output pin.

Whenever the CSB pin goes to a logic low state, the SO pin output driver is enabled allowing

information to be transferred from the L9823 to the MCU. To avoid any spurious data, it is

essential that the high-to-low transition of the CSB signal occur only when SCLK is in a logic

low state.

10

CSB

11

12

13

OUT5 Output 5

OUT4 Output 4

OUT3 Output 3

6/19

DocID7791 Rev 7

L9823

Block diagram and pins description

Table 2. Pins description (continued)

Description

N#

14

OUT2 Output 2

The Short Fault Protect Disable (SFPD) pin is used to disable the overcurrent latch-OFF. This

feature allows control of incandescent loads where in-rush currents exceed the device's

analog current limits. Essentially the SFPD pin determines whether the L9823 output(s) will

instantly shutdown upon sensing an output short or remain ON in a current limiting mode of

SFPD operation until the output short is removed or thermal shutdown is reached. If the SFPD pin is

tied to V_DDthe L9823 output(s) will remain ON in a current limited mode of operation upon

encountering a load short to supply. If the SFPD pin is grounded, a short circuit will

immediately shutdown only the output affected. Other outputs not having a fault condition will

operate normally.

15

16

17

18

19

20

21

VDD

GND

N.C.

VDD

GND

Not Connected

The Reset pin is active low and used to clear the SPI shift register and in doing so sets all

output switches OFF. With the device in a system with an MCU; upon initial system power up,

the MCU holds the Reset pin of the device in a logic low state ensuring all outputs to be OFF

until the VDD pin voltages are adequate for predictable operation. After the L9823 is Reset,

22

RESET the MCU is ready to assert system control with all output switches initially OFF. The Reset pin

is active low and has an internal pull-down incorporated to ensure operational predictability

should the external pull-down of the MCU open circuit. The internal pull-up is to afford safe

and easy interfacing to the MCU. The Reset pin of the L9823 should be pulled to a logic low

state for a duration of at least 160ns to ensure reliable Reset.

23

24

OUT1 Output 1

OUT0 Output 0

DocID7791 Rev 7

7/19

18

Electrical specifications

L9823

2

Electrical specifications

2.1

Absolute maximum ratings

For voltages and currents applied externally to the device. Exceeding limits may cause

damage to the device.

Table 3. Absolute maximum ratings

Symbol

Parameter

Value

Unit

V_DD

Supply voltage

-0.3 to 7

V

Inputs and data lines (CSB, SCLK, SI, Reset, SFPD, SO)

V_IN

V_SDO

I_IN

Voltage (CSB, SCLK, SI, Reset, SFPD)

Voltage (SO)

-0.3 to 7

-0.3 to V_DD+0.3

-20 to 20 ⁽¹⁾

V

Protection diodes current ⁽¹⁾T  1ms

mA

Outputs (OUT0 to OUT7)

V_{OUT Cont}Continuous output voltage

V_{OUT Cont}Continuous output current

I_{OUT PEAK}Output current

-1.5 to 45

-3 to I_{OUT LIM}

-10 ⁽²⁾to 2

50

V

A

E_OUTclampOutput clamp energy ⁽³⁾

mJ

A

I_{OUT LIM}Output current (self limit)

2

1. All inputs are protected against ESD according to MIL 883C; tested with HBM C = 100 pF, R = 1500  at

2kV. It corresponds to a dissipated energy E  0.2mJ (data available upon request).

2. Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3.

3. Max. output clamp energy at T_j= 150°C, using single non-repetitive pulse of 500 mA

2.2

Thermal data

Table 4. Thermal data

Symbol

Parameter

Value

Unit

Thermal shutdown

T_LIM

Thermal shutdown threshold

155 (Min.), 180 (Typ.)

°C

Thermal resistance (junction-to-lead)

R_thjL-oneSingle output (junction lead)

R_thjL-allAll outputs (junction lead)

25 (Max.)

20 (Max.)

-55 to 150

°C/W

°C

T_stg

Storage temperature

8/19

DocID7791 Rev 7

L9823

Electrical specifications

2.3

Electrical characteristics

4.5 V  V  5.5 V; -40 °C  T  150 °C; unless otherwise specified.

DD

J

Table 5. Electrical characteristics

Test condition

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply voltage

Reset = LOW and / or

V_DDRES>V_DD> 0.5V

I_DDSTBStandby current

I_DDleakleakage current

-

35

<1

70

10

µA

V_DD< 0.5V

I

_{OUT0 to 7}= 500 mA

SPI - SCLK = 3 MHz

CSB = Low

I_DDOPMOperating mode

-

6

mA

SO no load

I_DDduring reverse output

current

I_{DD rev}

I_{out rev}= -2.5 A

-

10

mA

V

Reset of all registers and disable

of all outputs

V_{DD RES}Undervoltage reset

2.5

3.95

Inputs (CSB, SCLK, SI, Reset, SFPD)

V_INL

V_INH

Low level

High level

-

-0.3

-

0.2·V_DD

V

V_DD+0.

0.7·V_DD

3

V_hyst

I_IN

Hysteresis voltage

Input current

-

0.5

-10

1.2

-

0.5

·

V

DD

V_IN= V_DD

10

µA

Pull-up resistance (CSB, SI)

R_IN

C_IN

-

50

-

250

10

k

Pull-down resistance (SFPD,

Reset, SCLK)

Input capacitance

pF

Serial data outputs

V_SOHHigh output level

I_SO= -4 mA

V_DD-0.4

-

V

V_SOL

I_SOL

C_SO

Low output level

I_SO= 3.2 mA

-

-10

-

0.4

10

20

Tristate leakage current

Output capacitance

CSB = high; 0 V  V_SO V_DD

f_SO= 300 kHz, 0 V  V_SO V_DD

Outputs OUT 0 to 7

µA

pF

OUTx = OFF; V_OUTx= 16V;

V



V

and / or Reset = Low

I_{OUTL0 - 7}Leakage current

-10

10

60

µA

DD

DD RES

Tj  85°C

<1A

2mA  I_{OUT clamp} I_{OUT LIM}

I_{OUT test}= 20mA with correlation

V_OUT

Output clamp voltage

45

-

V

clamp

I_OUT= 500mA;T_j= +150°C

T_j= +25°C

1

1.5

R_DSonOn resistance OUT 0 ... 7



0.8

1.25

DocID7791 Rev 7

9/19

18

Electrical specifications

L9823

Table 5. Electrical characteristics (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

C_OUTOutput capacitance

Outputs short circuit protection

V_OUT= 16 V; f = 1 MHz

-

300

pF

I_SCB

Overcurrent shutoff threshold SFPD = Low, V_OUT V_DG

0.5

1.6

2.5

A

I_{OUT LIM}Short circuit current limitation

-

SFPD = Low, V_OUT V_DG

CSB = 50% to

t_{dly SCB}Short circuit shutdown delay

70

150

250

µs

I_OUT 1/2 I_{OUT LIM}

Diagnostics

V_DG

Diagnostic threshold voltage

-

0.5

·V

0.55

·V_DD0.6

·V

V

DD

V_out= V_DG

Open load detection sink

current

I_{OUT OL}

30

70

60

100

250

µA

Output programmed OFF

SFPD = Low, V_OUT V_DG

CSB = 50% to valid data at SO

t_{dly SFPD}Diagnostic detection filter time

150

µs

Outputs timing

CSB = 50% to R_L= 50 

V_OUT= 0.9 V_bat, V_bat= 16 V

t_don

Turn-on delay

Turn-off delay

-

20

µs

CSB = 50% to R_L= 50 

t_doff

-

µs

V_OUT= 0.1

90% to 30% of V_bat

R_L= 50 ; V_bat= 16 V

30% to 90% of V_bat

·V_bat, V_bat= 16 V

;

dV_on/dtTurn-on voltage slew-rate

dV_off/dtTurn-off voltage slew-rate

0.7

2.1

3.5

5.5

V/µs

;

R_L= 50 ; V_bat= 16 V

30% to 80% of V_{OUT clamp}

dV_off

Turn-off voltage clamp slew-

rate

R_L= 500 

clamp/dt

Serial diagnostic link (Load capacitor at SO = 200 pF)

f_sclk

t_clh

t_cll

Clock frequency

50% duty cycle

3

-

MHz

ns

Minimum time SCLK = HIGH

Minimum time SCLK = LOW

-

160

ns

Propagation delay

t_pcld

t_csdv

t_sclch

t_hclcl

t_scld

4.9 V  V_DD 5.1 V

-

100

ns

SCLK to data at SO valid

CSB = LOW to data at SO

active

-

100

Setup time SCLK to CSB change

H/L

SCLK low before CSB low

100

20

-

SCLK change L/H after CSB = Setup time CSB to SCLK change

Low

L/H

SCLK change H/L after SI data

valid

SI input setup time

10/19

DocID7791 Rev 7

L9823

Electrical specifications

Table 5. Electrical characteristics (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

SI data hold after SCLK change

H/L

t_hcld

SI input hold time

-

20

ns

t_sclcl

SCLK low before CSB high

SCLK high after CSB high

-

150

15,

-

ns

t_hclch

t_pchdzCSB L/H to output data float

100

Minimum Reset time Reset =

t_Reset

Low

-

160

ns

Table 6. Outputs Control

Description

Value

SI-bit

0

1

Output

on

off

Figure 3. Output control register structure

-3"

1ꢇ

,3"

1ꢆ 1ꢅ 1ꢄ 1ꢃ 1ꢂ 1ꢀ 1ꢁ

#ONTROLꢉBIT OUTPUT ꢁ

#ONTROLꢉBIT OUTPUT ꢀ

#ONTROLꢉBIT OUTPUT ꢂ

#ONTROLꢉBIT OUTPUT ꢃ

#ONTROLꢉBIT OUTPUT ꢄ

#ONTROLꢉBIT OUTPUT ꢅ

#ONTROLꢉBIT OUTPUT ꢆ

#ONTROLꢉBIT OUTPUT ꢇ

'!0'03ꢀꢀꢁꢄꢆ

DocID7791 Rev 7

11/19

18

Electrical specifications

L9823

2.4

Power outputs characteristics for flyback current, outputs

short circuit protection and diagnostics

For output currents flowing into the circuit the output voltages are limited. The typical value

of this voltage is 50V. This function allows that the flyback current of a inductive load

recirculates into the circuit; the flyback energy is absorbed in the chip.

Output short circuit protection SFPD = Low (dedicated for loads without inrush current):

when the output current exceeds the short circuit threshold, the corresponding output

overload latch is set after a delay time t

and the output is switched off. The delay timer

dly SCB

is started after each rise of CSB and valid datas are transferred to the output control

register. If the short takes place after the delay time has elapsed the shutdown is immediate

(within 15 µs).

Output short circuit protection SFPD = High (dedicated for loads with inrush current, as

lamps): when the load current would exceed the short circuit limit value, the corresponding

output goes in a current regulation mode. The output current is determined by the output

characteristics and the output voltage depends on the load resistance. In this mode high

power is dissipated in the output transistor and its temperature increases rapidly. When the

power transistor temperature exceeds the thermal shutdown threshold, the overload latch is

set and the corresponding output switched off.

For the load diagnostic in output off condition each output features a diagnostic current sink,

of typ 60 µA.

12/19

DocID7791 Rev 7

L9823

Functional description

3

Functional description

3.1

General

The L9823 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to

the device using the Serial Peripheral Interface = SPI protocol. The power outputs features

voltage clamping function for flyback current recirculation and are protected against short

circuit to Vbat.

The diagnostics recognizes two outputs fault conditions: 1) overcurrent and thermal

overload in switch-ON condition and 2) open load or short to GND in switch-OFF condition

for all outputs. The outputs status can be read out via the serial interface.

The chip internal Reset is a OR function of the external Reset signal and internally

generated undervoltage Reset signal.

3.2

Output stages control

Each output is controlled with its latch and with a common Reset line, which enables all

outputs.

The control data are transmitted via the SI input, the timing of the serial interface is shown in

Figure 4.

The device is selected with low CSB signal and the input data are transferred into the 8 bit

shift register at every falling SCLK edge. The rising edge of the CSB latches the new data

from the shift register to the drivers.

Figure 4. Timing of the serial interface

#3"

TSCLCH

TCSDV

THCLCL

TCLH

TCLL

TSCLCL

THCLCH

3#,+

3/

TPCLD

TPCHDZ

$ꢁ

NOT DEFINED

$ꢇ

THCLD

TSCLD

$ꢇ

$ꢆ

$ꢁ

3)

'!0'03ꢀꢀꢁꢄꢇ

The SPI register data are transferred to the output latch at rising CSB edge. The digital filter

between CSB and the output latch ensures that the data are transferred only after 8 SCLK

cycles or multiple of 8 SCLK cycles since the last CSB falling edge. The CSB changes only

at low SCLK.

DocID7791 Rev 7

13/19

18

Functional description

L9823

3.3

Diagnostics

The output voltage at all outputs is compared with the diagnostic threshold, typ 0,55  V

=

DD

V

.

DG

Table 7. Diagnostic for outputs

Output

Output voltage

Status bit

Output mode

off

on

> DG-threshold

< DG-threshold

> DG-threshold

high

low

correct operation

fault condition 2)

correct operation

fault condition 1)

low

high

Fault condition 1

Output short circuit to Vbat:



For SFPD = Low the output was switched on and the voltage at the output exceeded

the diagnostics threshold due to overcurrent, the output overload latch was set and the

output has been switched off. The diagnostic bit is high.



For SFPD = high the output was switched on and the voltage at the output exceeds the

diagnostics threshold. The output operates in current regulation mode or has been

switched off due to thermal shutdown. The status bit is high.

Fault condition 2

Open load or output short circuit to GND:



The output is switched off and the voltage at the output drops below the diagnostics

threshold, because the load current is lower than the output diagnostic current source,

the load is interrupted. The diagnostic bit is low.



At the falling edge of CSB the output status data are transferred to the shift register.

When SCB is low, data bits contained in the shift register are transferred to SO output

at every rising SCLK edge.

Figure 5. Pulse diagram to read the outputs status register

#3"

3#,+

3)

-3"

ꢆ

ꢅ

ꢄ

ꢃ

ꢂ

ꢀ

,3"

3/

-3"

ꢆ

ꢅ

ꢄ

ꢃ

ꢂ

ꢀ

,3"

'!0'03ꢀꢀꢁꢄꢁ

14/19

DocID7791 Rev 7

L9823

Functional description

Figure 6. Structure of the outputs status register

06%

/6%

'LDJꢇ 'LDJꢆ 'LDJꢅ 'LDJꢄ 'LDJꢃ 'LDJꢂ 'LDJꢁ 'LDJꢀ

'LDJQRVWLFꢈELWꢉRXWSXWꢉꢀ

'LDJQRVWLFꢈELWꢉRXWSXWꢉꢁ

'LDJQRVWLFꢈELWꢉRXWSXWꢉꢂ

'LDJQRVWLFꢈELWꢉRXWSXWꢉꢃ

'LDJQRVWLFꢈELWꢉRXWSXWꢉꢄ

'LDJQRVWLFꢈELWꢉRXWSXWꢉꢅ

'LDJQRVWLFꢈELWꢉRXWSXWꢉꢆ

'LDJQRVWLFꢈELWꢉRXWSXWꢉꢇ

'!0'03ꢀꢀꢁꢄꢈ

DocID7791 Rev 7

15/19

18

Applications information

L9823

4

Applications information

The typical application diagram for parallel Input SPI control is shown in Figure 7.

Figure 7. Typical application circuit diagram for the L9823 circuit.

6

"!4

6/,4 !'%

2%'5,!4/2

$$

6

ꢀꢆ

$$

3&0$

/54ꢁ

ꢂꢄ

ꢉ

ꢀꢅ

/,ꢁ

ꢋ

6

ꢌ

$'

)

/,

#3"

ꢀꢁ

'ATE

#ONTROL

1ꢁ

ꢁ

1ꢁ

1ꢀ

1ꢂ

1ꢃ

1ꢄ

1ꢅ

1ꢆ

1ꢇ

ꢋ

)

ꢉ

3#"

/VER

ꢉ

4E MPERATURE

$ETECT

/4ꢁ

ꢋ

ꢌ

#(ꢁ

3#,+

$IAGꢁ

$IAGꢀ

$IAGꢂ

$IAGꢃ

$IAGꢄ

$IAGꢅ

$IAGꢆ

$IAGꢇ

/54ꢀ

ꢂꢃ

/54ꢂ

ꢀꢄ

/54ꢃ

ꢀꢃ

/54ꢄ

ꢀꢂ

/54ꢅ

ꢀꢀ

ꢃ

1ꢀ

#(ꢀ

#(ꢂ

$IAGꢀ

1ꢂ

$IAGꢂ

3)

ꢄ

1ꢃ

$IAGꢃ

#(ꢃ

1ꢄ

$IAGꢄ

#(ꢄ

3/

ꢈ

1ꢅ

$IAGꢅ

#(ꢅ

/54ꢆ

ꢂ

/54ꢇ

1ꢆ

$IAGꢆ

2ESET

#(ꢇ

2ESET

ꢂꢂ

1ꢇ

$IAGꢇ

#(ꢇ

5NDERVOLTAGE

2%3%4

ꢀ

0

2ꢎ , LOADS

,ꢈꢊꢂꢃ

ꢅ ꢉꢊ

ꢀꢇ ꢉ ꢂꢁ

'.$

,ꢈꢊꢂꢃ

'!0'03ꢀꢀꢁꢄꢂ

For higher current driving capability more outputs of the same kind can be paralleled. In this

case the maximum flyback energy should not exceed the limit value for single output.

The immunity of the circuit with respect to the transients at the output is verified during the

characterization for Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test

Pulses are coupled to the outputs with 200pF series capacitor. The correct function of the

circuit with the Test Pulses coupled to the outputs is verified during the characterization for

the typical application with R = 16 to 200, L= 0 to 600mH loads. All outputs withstand test

pulses without damage.

16/19

DocID7791 Rev 7

L9823

Package information

5

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Figure 8. SO24 mechanical data and package dimensions

MM

INCH

$)-ꢈ

/54,).% !.$

-%#(!.)#!, $!4!

-).ꢈ 490ꢈ -!8ꢈ -).ꢈ

490ꢈ -!8ꢈ

ꢁꢍꢀꢁꢄ

!

!ꢀ

"

ꢂꢍꢃꢅ

ꢁꢍꢀꢁ

ꢁꢍꢃꢃ

ꢁꢍꢂꢃ

ꢀꢅꢍꢂꢁ

ꢂꢍꢆꢅ ꢁꢍꢁꢈꢃ

ꢁꢍꢃꢁ ꢁꢍꢁꢁꢄ

ꢁꢍꢅꢀ ꢁꢍꢁꢀꢃ

ꢁꢍꢃꢂ ꢁꢍꢁꢁꢈ

ꢀꢅꢍꢆꢁ ꢁꢍꢅꢈꢊ

ꢁꢍꢁꢀꢂ

ꢁꢍꢂꢁꢁ

7EIGHTꢉ ꢁꢍꢆꢁGR

#

ꢁꢍꢁꢀꢃ

ꢏꢀꢐ

$

ꢁꢍꢆꢀꢄ

%

E

ꢇꢍꢄꢁ

ꢇꢍꢆꢁ ꢁꢍꢂꢈꢀ

ꢁꢍꢂꢈꢈ

ꢁꢍꢁꢅꢁ

ꢀꢍꢂꢇ

(

ꢀꢁꢍꢁ

ꢁꢍꢂꢅ

ꢁꢍꢄꢁ

ꢀꢁꢍꢆꢅ ꢁꢍꢃꢈꢄ

ꢁꢍꢇꢅ ꢁꢍꢁꢀꢁ

ꢀꢍꢂꢇ ꢁꢍꢁꢀꢆ

ꢀꢉꢊPLQꢋꢌꢍꢉꢎꢉꢊPD[ꢋꢌ

ꢁꢍꢀꢁ

ꢁꢍꢄꢀꢈ

H

ꢁꢍꢁꢃꢁ

,

ꢁꢍꢁꢅꢁ

K

DDD

ꢁꢍꢁꢁꢄ

3/ꢂꢄ

ꢏꢀꢐ h$v DIMENSION DOES NOT INCLUDE MOLD FLASHꢎ PROTUSIONS OR GATE

BURRSꢍ -OLD FLASHꢎ PROTUSIONS OR GATE BURRS SHALL NOT EXCEED

ꢁꢍꢀꢅMM PER SIDEꢍ

ꢁꢁꢇꢁꢇꢆꢈ #

'!0'03ꢀꢀꢁꢄꢄ

DocID7791 Rev 7

17/19

18

Revision history

L9823

6

Revision history

Table 8. Document revision history

Changes

Date

Revision

16-Apr-2003

4

Initial release.

Document reformatted.

13-Apr-2011

5

Added new order code in Table 1: Device summary on page 1.

Updated:

17-Jun-2013

19-Sep-2013

6

7

Figure 3: Output control register structure on page 11 and Figure 6:

Structure of the outputs status register on page 15.

Updated Disclaimer.

18/19

DocID7791 Rev 7

L9823

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE

SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)

AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS

OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT

PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS

EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY

DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE

DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

DocID7791 Rev 7

19/19

19


型号：	L9823013TR
厂家：	ST
描述：	Octal Low-Side Driver for bulb, resistive and inductive loads with serial input control, output protection and diagnostic 驱动光电二极管接口集成电路驱动器
文件：	总19页 (文件大小：361K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L9823013TR [STMICROELECTRONICS]

相关型号：

L9824

L9824D

L9825

L9825-21

L9825-32

L9825TR

L9825_03

L9826

L9826-21

L9826-22

L9826-32

L9826TR