M24M01-A125 [STMICROELECTRONICS]
Automotive 1-Mbit serial IC bus EEPROM with 1 MHz clock;
| 型号： | M24M01-A125 |
| 厂家： | 
ST |
| 描述： | Automotive 1-Mbit serial IC bus EEPROM with 1 MHz clock 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总37页 (文件大小：628K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24M01-A125
Automotive 1-Mbit serial I²C bus EEPROM with 1 MHz clock
Datasheet - production data
Features
2
• Compatible with all I C bus modes
– 1 MHz
– 400 kHz
– 100 kHz
• Memory array
– 1 Mbit (128 Kbytes) of EEPROM
TSSOP8 (DW)
169 mil width
– Page size: 256 bytes
– Additional Write lockable page
(Identification page)
• Extended temperature and voltage ranges
– -40 °C to 125 °C; 2.5 V to 5.5 V
• Schmitt trigger inputs for noise filtering.
• Short Write cycle time
– Byte Write within 4 ms
– Page Write within 4 ms
SO8 (MN)
150 mil width
• Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 600 k Write cycles at 125 °C
• Data retention
– 50 years at 125 °C
– 100 years at 25 °C
• ESD Protection (Human Body Model)
– 4000 V
• Packages
– RoHS compliant and halogen-free
®
(ECOPACK 2)
February 2014
DocID023765 Rev 4
1/37
This is information on a product in full production.
www.st.com
Contents
M24M01-A125
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E2, E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
3.4
3.5
3.6
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
4.2
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Contents
5
Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1
5.1.2
5.1.3
Operating supply voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CC
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
8
9
10
11
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3
List of tables
M24M01-A125
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Address significant bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device identification code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33
SO8N – 8 lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 34
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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M24M01-A125
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2
Figure 10. Maximum R
value versus bus parasitic capacitance (C ) for an I C
bus
bus
bus at maximum frequency f = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
C
2
Figure 11. Maximum R
value versus bus parasitic capacitance C ) for an I C
bus
bus
bus at maximum frequency f = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
C
Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34
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5
Description
M24M01-A125
1
Description
The M24M01-A125 is a 1-Mbit serial EEPROM Automotive grade device operating up to
125 °C. The M24M01-A125 is compliant with the very high level of reliability defined by the
Automotive standard AEC-Q100 grade 1.
2
The device is accessed by a simple serial I C compatible interface running up to 1 MHz.
The memory array is based on advanced true EEPROM technology (Electrically Erasable
PROgrammable Memory). The M24M01-A125 is a byte-alterable memory (128 K × 8 bits)
organized as 512 pages of 256 bytes in which the data integrity is significantly improved
with an embedded Error Correction Code logic.
The M24M01-A125 offers an additional Identification Page (256 bytes) in which the ST
device identification can be read. This page can also be used to store sensitive application
parameters which can be later permanently locked in read-only mode.
Figure 1. Logic diagram
7#
%ꢇ
%ꢅ
(IGH VOLTAGE
GENERATOR
#ONTROL LOGIC
3#,
3$!
)ꢆ/ SHIFT REGISTER
$ATA
REGISTER
!DDRESS REGISTER
AND COUNTER
ꢅ PAGE
)DENTIFICATION PAGE
8 DECODER
-3ꢀꢁꢂꢃꢄ6ꢅ
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M24M01-A125
Description
Table 1. Signal names
Function
Signal name
Direction
E2, E1
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
Input
I/O
Input
Input
-
SDA
SCL
WC
VCC
VSS
-
Figure 2. 8-pin package connections
-ꢇꢈ-ꢁꢅ
$5
%ꢅ
%ꢇ
ꢅ
ꢇ
ꢀ
ꢈ
ꢉ
ꢃ
ꢊ
ꢄ
6
##
7#
3#,
3$!
6
33
-3ꢅꢂꢃꢃꢀ6ꢅ
1. DU: Don't Use (if connected, must be connected to VSS)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
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36
Signal description
M24M01-A125
2
Signal description
2.1
Serial Clock (SCL)
The signal applied on this input is used to strobe the data available on SDA(in) and to output
the data on SDA(out).
2.2
2.3
Serial Data (SDA)
SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open
drain output that may be wire-OR’ed with other open drain or open collector signals on the
bus. A pull up resistor must be connected between SDA and V (Figure 10 indicates how
CC
to calculate the value of the pull-up resistor).
Chip Enable (E2, E1)
(E2,E1) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2) of the 7-bit device select code (see Table 2). These inputs must be
tied to V or V , as shown in Figure 3. When not connected (left floating), these inputs
CC
SS
are read as low (0).
Figure 3. Device select code
6
6
##
##
-ꢇꢈXXX
-ꢇꢈXXX
%
%
I
I
6
6
33
33
!Iꢅꢇꢉꢁꢊ
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
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M24M01-A125
Signal description
2.5
2.6
VSS (ground)
V
is the reference for the V supply voltage.
CC
SS
Supply voltage (VCC)
V
is the supply voltage pin.
CC
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36
Device operation
M24M01-A125
3
Device operation
2
The device supports the I C protocol (see Figure 4).
2
The I C bus is controlled by the bus master and the device is always a slave in all
communications.
The device (bus master or a slave) that sends data on to the bus is defined as a transmitter;
the device (bus master or a slave) is defined as a receiver when reading the data.
2
Figure 4. I C bus protocol
3#,
3$!
3$!
)NPUT
3$!
#HANGE
34!24
#ONDITION
34/0
#ONDITION
ꢅ
ꢇ
ꢀ
ꢃ
ꢉ
ꢂ
3#,
3$!
!#+
-3"
34!24
#ONDITION
ꢅ
ꢇ
ꢀ
ꢃ
ꢉ
ꢂ
3#,
3$!
-3"
!#+
34/0
#ONDITION
!)ꢁꢁꢃꢂꢇ"
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M24M01-A125
Device operation
3.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
3.3
3.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
th
of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
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36
Device operation
M24M01-A125
3.5
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, as
shown in Table 2.
The device select code consists of a 4-bit device type identifier and a 2-bit Chip Enable
address (E2, E1). A device select code handling any value other than 1010b (to select the
memory) or 1011b (to select the Identification page) is not acknowledged by the memory
device.
2
Up to four memory devices can be connected on a single I C bus. Each one is given a
unique 2-bit code on the Chip Enable (E2, E1) inputs. When the device select code is
received, the memory device only responds if the Chip Enable Address is the same as the
value decoded on the E2, E1 inputs.
th
The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
Table 2. Device select code
Chip Enable
address(2)
Address
bit
Device type identifier(1)
RW
b7
1
b6
0
b5
1
b4
0
b3
E2
b2
b1
b0
When accessing
the memory
E1
A16
RW
When accessing
the Identification
page
1
0
1
1
E2
E1
X(3)
RW
1. The most significant bit, b7, is sent first.
2. E2 and E1 bits are compared with the value read on input pins E2,E1.
3. X = don’t care.
If a match occurs on the device select code, the corresponding memory device gives an
th
acknowledgment on Serial Data (SDA) during the 9 bit time. If the memory device does not
match the device select code, it deselects itself from the bus, and goes into Standby mode.
Once the memory device has acknowledged the device select code (Table 2), the memory
device waits for the master to send two address bytes (most significant address byte sent
first, followed by the least significant address byte (Table 3). The memory device responds
to each address byte with an acknowledge bit.
Note:
A: significant address bit.
X: bit is Don’t Care.
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Device operation
Table 3. Address significant bits
Memory(1) (2)
Identification page
(Device type identifier = 1011b)
(Device type identifier =
1010b)
Random
Address
Read
Read
Write
Lock
Read
lock
status
Write
Identification Identification Identification
page
page
page
Device
Select
bit 1
b16
A16
A16
X
X
X
X
b15
b14
b13
b12
b11
b10
b9
A15
A14
A13
A12
A11
A10
A9
A15
A14
A13
A12
A11
A10
A9
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b8
A8
A8
X
X
b7
A7
A7
A7
A6
A5
A4
A3
A2
A1
A0
A7
A6
A5
A4
A3
A2
A1
A0
b6
A6
A6
b5
A5
A5
b4
A4
A4
b3
A3
A3
b2
A2
A2
b1
A1
A1
b0
A0
A0
1. A: significant address bit.
2. X: bit is Don’t Care.
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36
Device operation
M24M01-A125
3.6
Identification page
The M24M01-A125 offers an Identification Page (256 bytes) in addition to the 1 Mb memory.
The Identification page contains two fields:
•
Device identification code: the first three bytes are programmed by STMicroelectronics
with the Device identification code, as shown in Table 4.
•
Application parameters: the bytes after the Device identification code are available for
application specific data.
Note:
If the end application does not need to read the Device identification code, this field can be
overwritten and used to store application-specific data. Once the application-specific data
are written in the Identification page, the whole Identification page should be permanently
locked in Read-only mode.
The instructions Read, Write and Lock Identification Page are detailed in Section 4:
Instructions.
Table 4. Device identification code
Address in
Content
Value
Identification page
00h
01h
02h
ST manufacturer code
I2C family code
20h
E0h
Memory density code
11h (1024 Kbit)
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M24M01-A125
Instructions
4
Instructions
4.1
Write operations
For a Write operation, the bus master sends a Start condition followed by a device select
code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5, and
waits for the master to send two address bytes (most significant address byte sent first,
followed by the least significant address byte (Table 3). The device responds to each
address byte with an acknowledge bit, and then waits for the data byte.
The 128 Kbytes (1 Mb) are addressed with 17 address bits, the 16 lower address bits being
defined by the two address bytes and the most significant address bit (A16) being included
in the Device Select code (see Table 2).
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
th
the “10 bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle t is then triggered. A Stop condition at any other time slot does not trigger the internal
W
Write cycle.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
After the successful completion of an internal Write cycle (t ), the device internal address
W
counter is automatically incremented to point to the next byte after the last modified byte.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 6.
DocID023765 Rev 4
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36
Instructions
M24M01-A125
4.1.1
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified (see Figure 6). If, instead, the
addressed location is not Write-protected, the device replies with Ack. The bus master
terminates the transfer by generating a Stop condition, as shown in Figure 5.
Figure 5. Write mode sequences with WC = 0 (data write enabled)
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16/37
DocID023765 Rev 4
M24M01-A125
Instructions
4.1.2
Page Write
(a)
The Page Write mode allows up to N bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A16/A8, are the same. If more bytes are sent than will fit up to the end
of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the
page are overwritten.
(a)
The bus master sends from 1 to N bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte received by the device is
not acknowledged, as shown in Figure 6. After each byte is transferred, the internal byte
address counter is incremented. The transfer is terminated by the bus master generating a
Stop condition.
Figure 6. Write mode sequences with WC = 1 (data write inhibited)
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a. N is the number of bytes in a page.
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Instructions
M24M01-A125
4.1.3
Write Identification Page
The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
•
Device type identifier = 1011b
•
Most significant address bits A16/A8 are don't care, except for address bit A10 which
must be “0”. Least significant address bits A7/A0 define the byte location inside the
Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
4.1.4
4.1.5
Lock Identification Page
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
•
•
•
Device type identifier = 1011b
Address bit A10 must be ‘1’; all other address bits are don't care
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 7, is:
•
•
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
•
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
18/37
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M24M01-A125
Instructions
Figure 7. Write cycle polling flowchart using ACK
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DocID023765 Rev 4
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Instructions
M24M01-A125
4.2
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
Figure 8. Read mode sequences
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4.2.1
Random Address Read
The Random Address Read is a sequence composed of a truncated Write sequence (to
define a new address pointer value, see Table 3) followed by a current Read.
The Random Address Read sequence is therefore the sum of [Start + Device Select code
with RW=0 + two address bytes] (without Stop condition, as shown in Figure 8)] and [Start
condition + Device Select code with RW=1]. The memory device acknowledges the
sequence and then outputs the contents of the addressed byte. To terminate the data
transfer, the bus master does not acknowledge the last data byte and then issues a Stop
condition.
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M24M01-A125
Instructions
4.2.2
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte pointed by the internal address counter. The counter is then incremented.
The bus master terminates the transfer with a Stop condition, as shown in Figure 8, without
acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory
or the Identification page. When accessing the Identification page, the address counter
value is loaded with the Identification page byte location, when accessing the memory, it is
safer to always use the Random Address Read instruction (this instruction loads the
address counter with the byte location to read in the memory) instead of the Current
Address Read instruction.
4.2.3
Sequential Read
A sequential Read can be used after a Current Address Read or a Random Address Read.
After a Read instruction, the device can continue to output the next byte(s) in sequence if
the bus master sends additional clock pulses and if the bus master does acknowledge each
transmitted data byte. To terminate the stream of bytes, the bus master must not
acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8.
The sequential read is controlled with the device internal address counter which is
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
4.2.4
4.2.5
Read Identification Page
The Identification Page can be read by issuing a Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The most significant address bits A16/A8
are don't care and the least significant address bits A7/A0 define the byte location inside the
Identification page. The number of bytes to read in the ID page must not exceed the page
boundary.
Read the lock status
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit after the data byte if the Identification page is
unlocked, otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
•
Start: the truncated command is not executed because the Start condition resets the
device internal logic,
•
Stop: the device is then set back into Standby mode by the Stop condition.
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Instructions
M24M01-A125
4.2.6
Acknowledge in Read mode
For all Read instructions, the device waits, after each byte sent out, for an acknowledgment
during the 9th bit time. If the bus master does not send the Acknowledge (the master drives
SDA high during the 9th bit time), the device terminates the data transfer and enters its
Standby mode.
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M24M01-A125
Application design recommendations
5
Application design recommendations
5.1
Supply voltage
5.1.1
Operating supply voltage (V
)
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Table 7).
CC
CC
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal Write cycle (t ). In order to
W
secure a stable DC supply voltage, it is recommended to decouple the V line with a
CC
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V /V package
CC SS
pins.
5.1.2
Power-up conditions
When the power supply is turned on, the V voltage has to rise continuously from 0 V up to
CC
the minimum V operating voltage defined in Table 7.
CC
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until V reaches the internal
CC
threshold voltage (this threshold is defined in the DC characteristic Table 10 as V
).
RES
When V passes over the POR threshold, the device is reset and in the following state:
CC
•
•
in the Standby power mode
deselected
As soon as the V voltage has reached a stable value within the [V (min), V (max)]
CC
CC
CC
range (defined in Table 7), the device is ready for operation.
5.1.3
Power-down
During power-down (continuous decrease in the V supply voltage below the minimum
CC
V
operating voltage defined in Table 7), the device must be in Standby power mode (that
CC
is after a STOP condition or after the completion of the Write cycle t if an internal Write
W
cycle is in progress).
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Application design recommendations
M24M01-A125
5.2
Cycling with Error Correction Code (ECC)
The Error Correction Code (ECC) is an internal logic function which is transparent for the
2
I C communication protocol.
(b)
The ECC logic is implemented on each group of four EEPROM bytes . Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
(b)
other bytes located in the same group . As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Table 6.
Example 1: maximum cycling limit reached with 1 million cycles per byte
Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group
cycling budget is 4 million cycles.
Example 2: maximum cycling limit reached with unequal byte cycling
Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times,
byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million
cycles.
b. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
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M24M01-A125
Delivery state
6
Delivery state
The device is delivered as follows:
•
•
The memory array is set to all 1s (each byte = FFh).
Identification page: the first three bytes define the Device identification code (value
defined in Table 4). The content of the following bytes is Don’t Care.
7
Maximum rating
Stressing the device outside the ratings listed in Table 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 5. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
V
TSTG
TLEAD
VIO
Lead temperature during soldering
Input or output range
see note (1)
–0.50
6.5
5
IOL
DC output current (SDA = 0)
-
–0.50
-
mA
V
VCC
Supply voltage
6.5
4000
VESD
Electrostatic pulse (Human Body model)(2)
V
1. Compliant with JEDEC Standard J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions of Hazardous Substances
(RoHS directive 2011/65/EUof July 2011).
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std
JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
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DC and AC parameters
M24M01-A125
8
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 6. Cycling performance by groups of four bytes
Symbol
Parameter
Test condition
Min.
Max.
Unit
TA ≤ 25 °C, 2.5 V < VCC < 5.5 V
Write cycle endurance(1) TA = 85 °C, 2.5 V < VCC < 5.5 V
-
-
-
4,000,000
1,200,000
600,000
Write
Ncycle
cycle(2)
TA = 125 °C, 2.5 V < VCC < 5.5 V
1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where
N is an integer, or for the status register byte (refer also to Section 5.2: Cycling with Error Correction Code (ECC)). The
Write cycle endurance is defined by characterization and qualification.
2. A Write cycle is executed when either a Page Write, a Byte Write, a Write Identification Page or a Lock Identification Page
instruction is decoded. When using those Write instructions, refer also to Section 5.2: Cycling with Error Correction Code
(ECC).
Table 7. Operating conditions (voltage range W)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
2.5
5.5
V
–40
125
°C
Table 8. AC measurement conditions
Symbol
Parameter
Min.
Max.
Unit
Cbus
Load capacitance
100
pF
ns
V
-
-
-
SCL input rise/fall time, SDA input fall time
Input levels
-
50
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
Input and output timing reference levels
V
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DC and AC parameters
Figure 9. AC measurement I/O waveform
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)NPUT AND OUTPUT
4IMING REFERENCE LEVELS
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Table 9. Input parameters
Symbol
Parameter(1)
Test condition
Min. Max. Unit
CIN
CIN
ZL
Input capacitance (SDA)
-
-
-
8
6
-
pF
pF
kΩ
kΩ
Input capacitance (other pins)
-
VIN < 0.3 VCC
VIN > 0.7 VCC
30
500
Input impedance (E2, E1, WC)(2)
ZH
-
1. Characterized only, not tested in production.
2. E2, E1 input impedance when the memory is selected (after a Start condition).
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DC and AC parameters
M24M01-A125
Table 10. DC characteristics
Test conditions (in addition to
Symbol
Parameter
Min.
Max.
Unit
those in Table 7 and Table 8)
Input leakage current
(SCL, SDA, E2, E1)
VIN = VSS or VCC,
device in Standby mode
ILI
-
-
± 2
± 2
µA
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
fC = 400 kHz, VCC = 5.5 V
fC = 400 kHz, VCC = 2.5 V
fC = 1 MHz, VCC = 5.5 V
fC = 1 MHz, VCC = 2.5 V
During tW
-
-
-
-
-
2
2
2
2
2
mA
mA
mA
mA
mA
ICC
Supply current (Read)
Supply current (Write)
ICC0
Device not selected(1), t° = 85 °C
VIN = VSS or VCC , VCC = 2.5 V
-
-
-
-
2
3
µA
µA
µA
µA
Device not selected(1), t° = 85 °C,
VIN = VSS or VCC, VCC = 5.5 V
ICC1
Standby supply current
Device not selected(1), t° = 125 °C,
VIN = VSS or VCC, VCC = 2.5 V
15
20
Device not selected(1), t° = 125 °C,
VIN = VSS or VCC, VCC = 5.5 V
VIL
VIH
Input low voltage (SCL, SDA, WC)
Input high voltage (SCL, SDA)
Input high voltage (WC, E2, E1)
-
-
-
–0.45
0.3 VCC
6.5
V
V
V
0.7 VCC
0.7 VCC VCC +0.6
I
OL = 2.1 mA, VCC = 2.5 V or
VOL
Output low voltage
-
0.4
1.5
V
V
IOL = 3 mA, VCC = 5.5 V
(2)
VRES
Internal reset threshold voltage
-
0.5
1. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the
internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
2. Characterized only, not 100% tested.
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DC and AC parameters
Table 11. 400 kHz AC characteristics
Parameter(1)
Symbol
Alt.
Min.
Max.
Unit
fC
fSCL
tHIGH
tLOW
tF
Clock frequency
-
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tCLCH
Clock pulse width high
Clock pulse width low
SDA (out) fall time(3)
Input signal rise time
Input signal fall time
600
1300
-
-
(2)
tQL1QL2
tXH1XH2
tXL1XL2
tDXCX
20
120
(4)
(4)
tR
(4)
(4)
tF
tSU:DAT Data in set up time
tHD:DAT Data in hold time
100
0
-
tCLDX
-
(5)
tCLQX
tDH
tAA
Data out hold time
100
-
-
(6)
tCLQV
Clock low to next data valid (access time)
900
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition set up time
600
600
600
-
-
-
Time between Stop condition and next Start
condition
tDHDL
tBUF
1300
-
ns
(7)(2)
tWLDL
tSU:WC WC set up time (before the Start condition)
tHD:WC WC hold time (after the Stop condition)
0
1
-
-
-
µs
µs
(8)(2)
tDHWH
tW
tWR
-
Write time
4
ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
(2)
tNS
-
80
ns
1. Test conditions (in addition to those in Table 7 and Table 8).
2. Characterized value, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C < 400 kHz.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 10.
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
DocID023765 Rev 4
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DC and AC parameters
Symbol
M24M01-A125
Table 12. 1 MHz AC characteristics
Parameter(1)
Alt.
Min.
Max.
Unit
fC
fSCL
Clock frequency
0
1
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tHIGH Clock pulse width high
260
tCLCH
tLOW
tR
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
400
-
(2)
(2)
tXH1XH2
tXL1XL2
(2)
(2)
tF
(3)
tQL1QL2
tF
-
120
tDXCX
tCLDX
tSU:DAT Data in setup time
tHD:DAT Data in hold time
50
0
-
-
(4)
tCLQX
tDH
tAA
Data out hold time
100
-
-
(5)
tCLQV
Clock low to next data valid (access time)
450
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition setup time
250
250
250
-
-
-
Time between Stop condition and next Start
condition
tDHDL
tBUF
500
-
-
ns
µs
µs
ms
ns
(6) (3)
tWLDL
tSU:WC WC set up time (before the Start condition)
tHD:WC WC hold time (after the Stop condition)
0
1
-
(7)
tDHWH
-
(3)
tW
tWR
-
Write time
4
80
Pulse width ignored (input filter on SCL and
SDA)
(3)
tNS
-
1. Test conditions (in addition to those in Table 7 and Table 8).
2. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when
fC < 1 MHz.
3. Characterized only, not tested in production.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 11.
6. WC=0 set up time condition to enable the execution of a WRITE command.
7. WC=0 hold time condition to enable the execution of a WRITE command.
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M24M01-A125
DC and AC parameters
2
Figure 10. Maximum R
value versus bus parasitic capacitance (C ) for an I C
bus
bus
bus at maximum frequency f = 400 kHz
C
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"US LINE CAPACITOR ꢋP&ꢌ
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2
Figure 11. Maximum R
value versus bus parasitic capacitance C ) for an I C
bus
bus
bus at maximum frequency f = 1MHz
C
6
ꢅꢁꢁ
##
2
BUS
4HE 2
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TIME CONSTANT
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DocID023765 Rev 4
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36
DC and AC parameters
M24M01-A125
Figure 12. AC waveforms
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32/37
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M24M01-A125
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
A1
A2
b
-
-
1.200
0.150
1.050
0.300
0.200
0.100
3.100
-
-
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
-
-
0.050
0.800
0.190
0.090
-
0.0020
0.0315
0.0075
0.0035
-
1.000
-
0.0394
-
c
-
-
CP
D
-
-
3.000
0.650
6.400
4.400
0.600
1.000
-
2.900
-
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
-
0.1142
-
e
E
6.200
4.300
0.450
-
6.600
4.500
0.750
-
0.2441
0.1693
0.0177
-
0.2598
0.1772
0.0295
-
E1
L
L1
α
0°
8°
0°
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
DocID023765 Rev 4
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36
Package mechanical data
M24M01-A125
Figure 14. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
Kꢀ[ꢀꢄꢇ
$ꢈ
$
F
FFF
E
H
ꢁꢉꢈꢇꢀPP
*$8*(ꢀ3/$1(
'
N
ꢃ
(ꢂ
(
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ꢂ
$ꢂ
/ꢂ
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1. Drawing is not to scale.
Table 14. SO8N – 8 lead plastic small outline, 150 mils body width, package data
millimeters
Min
inches (1)
Symbol
Typ
Max
Typ
Min
Max
A
-
-
1.750
0.250
-
-
-
0.0689
0.0098
-
A1
A2
b
-
0.100
1.250
0.280
0.170
-
-
0.0039
0.0492
0.0110
0.0067
-
-
-
-
0.480
0.230
0.100
5.000
6.200
4.000
-
-
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
-
c
-
-
ccc
D
-
-
4.900
6.000
3.900
1.270
-
4.800
5.800
3.800
-
0.1929
0.2362
0.1535
0.0500
-
0.1890
0.2283
0.1496
-
E
E1
e
h
0.250
0°
0.500
8°
0.0098
0°
0.0197
8°
k
-
-
L
-
0.400
-
1.270
-
-
0.0157
-
0.0500
-
L1
1.040
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
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M24M01-A125
Part numbering
10
Part numbering
Table 15. Ordering information scheme
Example:
M24M01-D
W
MN 3
T
P /K
Device type
M24 = I2C serial access EEPROM
Device function
M01-D = 1 Mbit (128 K x 8 bits) plus identification page
Operating voltage
W = VCC = 2.5 V to 5.5 V
Package
MN = SO8 (150 mil width)(1)
DW = TSSOP8 (169 mil width)(1)
Device grade
3 = -40 to 125 °C. Device tested with high reliability certified flow(2)
Option
blank = standard packing
T = Tape and reel packing
Plating technology
P = ECOPACK® (RoHS compliant)
Process
/K = Manufacturing technology code
1. RoHS-compliant and halogen-free (ECOPACK2®)
2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest
ST sales office for a copy.
For a list of available options (speed, package, etc.) or for further information on any aspect
of the devices, please contact your nearest ST sales office.
DocID023765 Rev 4
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36
Revision history
M24M01-A125
11
Revision history
Table 16. Document revision history
Changes
Date
Revision
24-Jan-2013
1
Initial release.
Document reformatted.
Document status changed from “Target specification” to “Preliminary
data”.
Updated:
– Section 3.6: Identification page
27-May-2013
2
– Note (1) under Table 5: Absolute maximum ratings
– ICC ,VIL and VOL values in Table 10: DC characteristics
– Package information in Table 15: Ordering information scheme
Removed information related to UFDFPN8 (MLP8) package.
Document status changed from “Preliminary data” to “Production
data”.
19-Aug-2013
04-Feb-2014
3
4
Updated “VOL” row in Table 10: DC characteristics.
Changed Data retention from "40 years at 55 °C" to "50 years at
125 °C" in Features.
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