M36L0R7050U1 [STMICROELECTRONICS]
128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package; 128兆位（ MUX I / O ，多银行，多层次，突发）闪存， 32或64 Mbit的PSRAM ， 1.8V电源多芯片封装
| 型号： | M36L0R7050U1 |
| 厂家： | 
ST |
| 描述： | 128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package |
| 文件： | 总22页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M36L0R7060U1 M36L0R7060L1
M36L0R7050U1 M36L0R7050L1
128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash
memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package
Preliminary Data
Feature summary
■ Multi-Chip Package
FBGA
– 1 die of 128 Mbit (8Mb x16, Mux I/O
Multiple Bank, Multi-level, Burst) Flash
Memory
– 1 die of 32 or 64Mbit Mux I/O, Burst
TFBGA88 (ZAM)
Pseudo SRAM
8 x 10mm
■ Supply voltage
– V
– V
= V
= V
= 1.7 to 1.95V
DDQF
DDF
PPF
DDP
= 9V for fast program
■ Dual operations
■ Electronic signature
– program/erase in one Bank while read in
others
– Manufacturer Code: 20h
– No delay between Read and Write
operations
– Device Codes (Top Flash Configuration):
M36L0R7060U1: 882Eh,
M36L0R7050U1: 882Eh
■
Block locking
– Device Codes (Bottom Flash Configuration)
M36L0R7060L1: 882Fh
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
M36L0R7050L1: 882Fh
■ ECOPACK® package
– WP for Block Lock-Down
F
– Absolute Write Protection with V
= V
SS
PPF
Flash memory
■ Common Flash Interface (CFI)
■ Multiplexed address/data
PSRAM
■ Synchronous / asynchronous read
– Synchronous Burst Read mode: 66MHz
– Random Access: 85ns
■ Access time: 70ns
■ Synchronous modes:
■ Synchronous burst read suspend
– Synchronous Write: continuous burst
programming time
– Synchronous Read: continuous burst or
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
fixed length: 4, 8 or 16 Words for 32 Mbit
devices or 4, 8,16 or 32 Words for 64 Mbit
devices
■ Memory organization
– Maximum Clock Frequency: 83MHz
– Multiple Bank Memory Array: 8 Mbit Banks
– Parameter Blocks (Top or Bottom location)
■ Low power consumption
■ Low power features
■ Security
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) Mode
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
– Automatic Temperature-compensated Self-
Refresh
■ 100,000 program/erase cycles per block
June 2006
Rev 1
1/22
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
1
Contents
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Address Inputs (ADQ0-ADQ15 and A16-A22) . . . . . . . . . . . . . . . . . . . . . 10
Data Input/Output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash memory Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.10 Flash memory Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11 PSRAM Chip Enable (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.13 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.14 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.15 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.16 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . 12
2.17
VDDF Flash memory Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.18 VCCP PSRAM Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.19
2.20
V
V
DDQF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PPF Flash memory Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . 13
2.21 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.22 SSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
3
4
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Contents
6
7
8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
List of tables
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating modes - Standard Asynchronous operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Stacked TFBGA88 8 × 10mm - 8 × 10 active ball array, 0.8mm pitch, package data . . . . 19
Part numbering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TFBGA88 8 × 10mm, 8 × 10 ball array - 0.8mm pitch, bottom view package outline. . . . . 19
5/22
Summary description
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
1
Summary description
The M36L0R7060U1, M36L0R7060L1, M36L0R7050U1 and M36L0R7050L1 combine two
memory devices in a Multi-Chip Package:
■
■
a 128-Mbit, Multiple Bank Flash memory, the M58LR128G(U/L)
a 32 or 64 Mbit PseudoSRAM, the M69KM048AA or M69KM096AA, respectively.
The purpose of this document is to describe how the two memory components operate with
respect to each other. It must be read in conjunction with the M58LRxxxGUL and
M69KM048AA or M69KM096AA datasheets, where all specifications required to operate
the Flash memory and PSRAM components are fully detailed. These datasheets are
available from the STMicroelectronics website: www.st.com.
Recommended operating conditions do not allow more than one memory to be active at the
same time.
The memory is offered in a Stacked TFBGA88 (8 ×10mm, 8 × 10 ball array, 0.8mm pitch)
package.
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
6/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Summary description
Figure 1.
Logic diagram
V
V
PPF
DDQF
V
V
DDF
DDP
23
16
ADQ0-ADQ15
A16-A22
E
G
F
F
F
WAIT
W
RP
WP
L
F
F
M36L0R7060U1
M36L0R7060L1
M36L0R7050U1
M36L0R7050L1
K
E
P
P
G
W
P
CR
P
UB
LB
P
P
V
SS
Ai12016
7/22
Summary description
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Table 1.
Signal names
A16-A22(1), (2)
Address Inputs
Flash memory and PSRAM common Data Input/Outputs, Address Inputs or
Command Inputs
ADQ0-ADQ15
VDDF
VDDQF
VPPF
VSS
Power Supply for Flash memory
Flash memory Power Supply for I/O Buffers
Flash memory Optional Supply Voltage for Fast Program and Erase
Ground
VDDP
NC
PSRAM Power Supply
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash memory and PSRAM Common Wait Data in Burst Mode
Flash memory and PSRAM Latch Enable Input
Flash memory and PSRAM Burst Clock
WAIT
L
K
Flash Memory
EF
Chip Enable Input
Output Enable Input
Write Enable Input
Reset Input
GF
WF
RPF
WPF
PSRAM
EP
Write Protect Input
Chip Enable Input
GP
Output Enable Input
WP
Write Enable Input
CRP
UBP
LBP
Configuration Register Enable Input
Upper Byte Enable Input
Lower Byte Enable Input
1. A16-A20 (in the case of a 32Mb PSRAM) or A16-A21 (in the case of a 64Mb PSRAM) are common to the
Flash memory and the PSRAM
2. A21-A22 (if the MCP contains a 32Mb PSRAM) or A22 (if the MCP contains a 64Mb PSRAM) are Address
Input(s) for the Flash memory component only.
8/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Summary description
Figure 2.
TFBGA connections (top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
NC
NC
NC
NC
NC
NC
DU
A21
DU
DU
NC
NC
NC
NC
A16
NC
NC
A18
A19
NC
NC
NC
V
V
NC
K
V
SS
SS
DDF
LB
P
NC
A22
A17
NC
V
W
P
E
P
NC
PPF
WP
L
A20
NC
NC
F
NC
UB
P
RP
W
F
NC
F
G
H
J
ADQ8
ADQ0
ADQ2
ADQ1
ADQ9
DU
ADQ10
ADQ3
ADQ11
NC
ADQ5
ADQ12
ADQ4
ADQ13
ADQ14
ADQ6
NC
WAIT
ADQ7
ADQ15
G
P
NC
G
F
V
DDQF
E
F
K
L
DU
V
V
CR
DDP
DDQF
P
V
V
V
V
V
V
V
V
SS
SS
DDQF
DDF
SS
SS
SS
SS
DU
DU
M
DU
DU
Ai12017b
9/22
Signal descriptions
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (ADQ0-ADQ15 and A16-A22)
ADQ0-ADQ15 and A16-A20 (for the M36L0R7050U1/L1) or A16-A21 (for the
M36L0R7060U1/L1) are common to the Flash memory and PSRAM components.
In the Flash memory, the Address Inputs select the cells in the array to access during Bus
Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the Program/Erase Controller.
In the PSRAM, the Address Inputs A16-A20 (/A21) are used in conjunction with ADQ0 to
ADQ15, to select the cells in the memory array that are accessed during read and write
operations.
2.2
2.3
Data Input/Output (ADQ0-ADQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
Latch Enable (L)
The Latch Enable input is common to the Flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the
respective memory components: M69KM048AA or M69KM096AA for the PSRAM and
M58LRxxxGUL for the Flash memory.
2.4
2.5
Clock (K)
The Clock input is common to the Flash memory and PSRAM components.
For details of how the Clock signal behaves, please refer to the datasheets of the respective
memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL
for the Flash memory.
Wait (WAIT)
The Wait output is common to the Flash memory and PSRAM components.
For details of how the WAIT signal behaves, please refer to the datasheets of the respective
memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL
for the Flash memory
10/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Signal descriptions
2.6
Flash memory Chip Enable (EF)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V and Reset is at V the device is in active
IL
IH
mode. When Chip Enable is at V the memory is deselected, the outputs are high
IH
impedance and the power consumption is reduced to the stand-by level.
It is not allowed to set both E and E to V at the same time.
F
P
IL
2.7
2.8
Flash memory Output Enable (GF)
The Output Enable input controls data outputs during the Bus Read operation of the Flash
memory.
Flash memory Write Enable (WF)
The Write Enable input controls the Bus Write operation of the Flash memory’s Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
2.9
Flash memory Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at V , the Lock-Down is enabled and the protection status of the Locked-
IL
Down blocks cannot be changed. When Write Protect is at V , the Lock-Down is disabled
IH
and the Locked-Down blocks can be locked or unlocked. (refer to M58LRxxxGUL
datasheet).
2.10
Flash memory Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at V , the
IL
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I
. Refer to the M58LRxxxGUL datasheet for the
DD2
value of I
After Reset all blocks are in the Locked state and the Configuration Register is
DD2.
reset. When Reset is at V , the device is in normal operation. Exiting reset mode the device
IH
enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is
required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to V
(refer to the M58LRxxxGUL datasheet).
RPH
2.11
PSRAM Chip Enable (EP)
Chip Enable, E , activates the device when driven Low (asserted). When de-asserted (V ),
P
IH
the device is disabled and goes automatically in low-power Standby mode or Deep Power-
Down mode, according to the RCR settings.
It is not allowed to set both E and E to V at the same time.
F
P
IL
11/22
Signal descriptions
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
2.12
PSRAM Output Enable (GP)
When held Low, V , the Output Enable, G , enables the Bus Read operations of the
IL
P
memory.
2.13
PSRAM Write Enable (WP)
Write Enable, W , controls the Bus Write operation of the memory. When asserted (V ), the
P
IL
device is in write mode and write operations can be performed either to the configuration
registers or to the memory array.
2.14
2.15
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UB , gates the data on the Upper Byte of the Address Inputs/ Data
P
Inputs/Outputs (ADQ8-ADQ15) to or from the upper part of the selected address during a
write or read operation.
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LB , gates the data on the Lower Byte of the Address Inputs/Data
P
Input/Outputs (ADQ0-ADQ7) to or from the lower part of the selected address during a write
or read operation.
If both LB and UB are disabled (High), the device will disable the data bus from receiving
P
P
or transmitting data. Although the device will seem to be deselected, it remains in an active
mode as long as E remains Low.
P
2.16
PSRAM Configuration Register Enable (CRP)
When this signal is driven High, V , bus read or write operations access either the value of
IH
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
2.17
2.18
VDDF Flash memory Supply Voltage
V
provides the power supply to the internal core of the Flash memory. It is the main
DDF
power supply for all Flash memory operations (Read, Program and Erase).
VCCP PSRAM Supply Voltage
The V
Supply Voltage is the core supply voltage.
CCP
12/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Signal descriptions
2.19
VDDQF Supply Voltage
V
provides the power supply to the I/O pins and enables all Outputs to be powered
DDQF
independently of V . V
can be tied to V
or can use a separate supply.
DDF DDQF
DDF
2.20
VPPF Flash memory Program Supply Voltage
V
is both a control input and a power supply pin. The two functions are selected by the
PPF
voltage range applied to the pin.
If V is kept in a low voltage range (0V to V
) V is seen as a control input. In this
PPF
PPF
DDQF
case a voltage lower than V
gives absolute protection against program or erase, while
PPLK
V
in the V
range enables these functions (see the M58LRxxxGUL datasheet for the
PPF
PP1
relevant values). V
is only sampled at the beginning of a program or erase; a change in
PPF
its value after the operation has started does not have any effect and program or erase
operations continue.
If V
is in the range of V
it acts as a power supply pin. In this condition V
must be
PPF
PPH
PPF
stable until the Program/Erase algorithm is completed.
2.21
VSS Ground
V
ground is the common Flash memory and PSRAM ground. It is the reference for the
SS
core supplies. It must be connected to the system ground.
2.22
VSSQ Ground
V
ground is the reference for the input/output circuitry driven by V
. V
must be
SSQ
DDQF SSQ
connected to V
SS
Note:
Each device in a system should have V , V
and V decoupled with a 0.1µF ceramic
DDF DDQF PP
capacitor close to the pin (high frequency, inherently low inductance capacitors should be as
close as possible to the package). See Figure 5: AC measurement load circuit. The PCB
track widths should be sufficient to carry the required V program and erase currents.
PP
13/22
Functional description
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
3
Functional description
The PSRAM and Flash memory components have separate power supplies but share the
same grounds. They are distinguished by two Chip Enable inputs: E for the Flash memory
F
and E for the PSRAM.
P
Recommended operating conditions do not allow more than one device to be active at a
time. The most common example is simultaneous read operations on one of the Flash
memory and the PSRAM components which would result in a data bus contention.
Therefore it is recommended to put the other devices in the high impedance state when
reading the selected device.
Figure 3.
Functional block diagram
V
V
V
PPF
DDQF
DDF
(1)
A21-A22
(2)
or A22
E
F
W
F
128 Mbit
Flash
RP
F
WP
Memory
F
G
F
WAIT
K
L
V
V
CCP
SS
(1)
(2)
A16-A20
or A16-A21
ADQ0-ADQ15
E
P
32 Mbit
or
64 Mbit
PSRAM
G
P
W
P
CR
P
UB
LB
P
P
AI12335
1. Address Inputs corresponding to the M36L0R7050U1 and M36L0R7050L1 devices.
2. Address Inputs corresponding to the M36L0R7060U1 and M36L0R7060L1 devices.
14/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Functional description
Table 2.
Operating modes - Standard Asynchronous operation
WAIT
Other
A19 A18 Address
ADQ0- ADQ8-
Operation(1) (2)
EP WP GP UBP LBP CRP
EF GF WF RPF
L
(3)
ADQ7 ADQ15
Inputs
Bus Read
Bus Write
VIL VIL VIH VIH
VIL VIH VIL VIH
VIH
VIH
VIL
Data Output
Data Input
The PSRAM must be disabled.
Address Latch VIL VIH
Output
Disable
Standby
Reset
X
VIH
Address Input
VIL VIH VIH VIH
VIH
Hi-Z
Any PSRAM mode is allowed.
VIH
X
X
X
X
X
VIH Hi-Z
VIL Hi-Z
X
X
Hi-Z
Hi-Z
Address In/ Data
Out Valid
VIH VIL VIL VIL VIL
VIL VIH VIL VIL VIL
Word Read
Word Write
Address In Valid
Address In Valid
Address In/ Data In
Valid
\_/
Read
00(RCR)
Configuration
Register (CR
controlled
method)(4)
Address In/ BCR,
RCR or DIDR
Content Valid
The Flash memory must
be disabled.
VIH VIL VIL VIL
10(BCR)
X
X1(DIDR)
VIL
VIH
0 or 00
(RCR)
1 or 10
(BCR)(6)
Program
BCR/
RCR
Data
Configuration
Register (CR
Controlled)(5)
VIL
VIL VIH
X
X
X
X
Address In Valid
High-Z
Output
Disable/No
Operation
VIH
VIL
X
X
X
X
Any Flash memory
mode is allowed.
X
Deep Power-
Down(7)
VIH
VIH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
High-Z
VIL
Standby
1. The Clock signal, K, must remain Low when the PSRAM is operating in asynchronous mode.
2. X = Don’t Care
3. In the Flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
4. Operating mode available in the M36L0R7060U1 and M36L0R7060L1 only (see M69KM096AA datasheet).
5. BCR and RCR only.
6. In the PSRAM of the M36L0R7050U1 and M36L0R7050L1, A19 is used to select between the BCR and the RCR whereas
in the PSRAM of the M36L0R7060U1 and M36L0R7060L1 both A18 and A19 are used to select the BCR, the RCR or the
DIDR.
7. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR
set to ‘0’. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP)
.
15/22
Maximum rating
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Min
Max
TA
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
–25
–25
–55
–0.2
85
85
°C
°C
°C
V
TBIAS
TSTG
VIO
125
2.45
Input or Output Voltage
VDDF, VDDQF Core and Input/Output Supply
–0.2
–0.2
2.45
V
VCCP
VPPF
IO
Voltages
Flash Program Voltage
Output Short Circuit Current
Time for VPPF at VPPFH
10
V
100
100
mA
tVPPFH
hours
16/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 4: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 4.
Operating and AC measurement conditions
Flash memory
Parameter
PSRAM
Max
Unit
Min
Max
Min
VDDF Supply Voltage
VCCP Supply Voltage
1.7
–
1.95
–
–
1.7
–
–
1.95
–
V
V
V
VDDQF Supply Voltage
1.7
1.95
VPPF Supply Voltage (Factory
environment)
8.5
9.5
–
–
V
V
VPPF Supply Voltage (Application
environment)
VDDQF
+0.4
–0.4
–25
–
–
Ambient Operating Temperature
Load Capacitance (CL)
85
5
–25
85
°C
pF
kΩ
ns
V
30
30
Output Circuit Resistors (R1, R2)
Input Rise and Fall Times
16.7
16.7
2
Input Pulse Voltages
0 to VDDQF
VDDQF/2
0 to VCCP/2
VCCP/2
Input and Output Timing Ref. Voltages
V
Figure 4.
AC measurement I/O waveform
V
DDQF
0V
V
/2
DDQF
AI06161b
17/22
DC and AC parameters
Figure 5.
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
AC measurement load circuit
VDDQF
VDDF
VDDQF
R1
DEVICE
UNDER
TEST
CL
0.1µF
R2
0.1µF
CL includes JIG capacitance
AI08364c
Table 5.
Symbol
Device capacitance
Parameter
Test Condition
Min
Max(1)
Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
14
18
pF
pF
COUT
VOUT = 0V
1. Sampled only, not 100% tested.
Please refer to the M58LRxxxGUL and M69KM048AA or M69KM096AA datasheets for
further DC and AC characteristics values and illustrations.
18/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Package mechanical
6
Package mechanical
Figure 6.
TFBGA88 8 × 10mm, 8 × 10 ball array - 0.8mm pitch, bottom view package
outline
D
D1
e
SE
E
E2 E1
b
BALL "A1"
ddd
FE FE1
FD
SD
A
A2
A1
BGA-Z42
1. Drawing is not to scale.
Table 6.
Stacked TFBGA88 8 × 10mm - 8 × 10 active ball array, 0.8mm pitch,
package data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.200
0.0079
0.850
0.350
8.000
5.600
0.0335
0.0138
0.3150
0.2205
0.300
7.900
0.400
8.100
0.0118
0.3110
0.0157
0.3189
D
D1
ddd
E
0.100
0.0039
0.3976
10.000
7.200
8.800
0.800
1.200
1.400
0.600
0.400
0.400
9.900
–
10.100
0.3937
0.2835
0.3465
0.0315
0.0472
0.0551
0.0236
0.0157
0.0157
0.3898
E1
E2
e
–
–
–
FD
FE
FE1
SD
SE
19/22
Part numbering
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
7
Part numbering
Table 7.
Part numbering scheme
Example:
M36 L 0 R 7 0 5 0 L 1 ZAM F
Device Type
M36 = Multi-Chip Package (Flash + RAM)
Flash 1 Architecture
L = Multi-Level, Multiple Bank, Burst Mode
Flash 2 Architecture
0 = No Die
Operating Voltage
R = VDDF = VDDP = VDDQF = 1.7V to 1.95V
Flash 1 Density
7 = 128 Mbit
Flash 2 Density
0 = No Die
RAM 1 Density
5 = 32 Mbit
6 = 64 Mbit
RAM 2 Density
0 = No Die
Parameter Block Location
U = Top Boot Block Flash
L = Bottom Boot Block Flash
Product Version
1 = 0.13µm Flash technology and multilevel design, 85ns speeds;
RAM, 70ns speed Mux I/O
Package
ZAM = Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch
Packing Option
E = ECOPACK® Package, Standard Packing
F = ECOPACK® Package, Tape & Reel Packing
Note:
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to
’1’. For further information on any aspect of this device, please contact your nearest ST
Sales Office.
20/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Revision history
8
Revision history
Table 8.
Date
08-Jun-2006
Document revision history
Revision
Changes
1
Initial release.
21/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
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22/22
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