M40Z111 [STMICROELECTRONICS]
NVRAM CONTROLLER for up to TWO LPSRAM; NVRAM控制器，最多两个LPSRAM
| 型号： | M40Z111 |
| 厂家： | 
ST |
| 描述： | NVRAM CONTROLLER for up to TWO LPSRAM |
| 文件： | 总12页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M40Z111
M40Z111W
NVRAM CONTROLLER for up to TWO LPSRAM
CONVERT LOW POWER SRAMs into
SNAPHAT (SH)
Battery
NVRAMs
PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
AUTOMATIC WRITE-PROTECTION when VCC
is OUT-OF-TOLERANCE
CHOICE of SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
– M40Z111:
VCC = 4.5V to 5.5V
THS = VSS 4.5V ≤ VPFD ≤ 4.75V
THS = VOUT 4.2V ≤ VPFD ≤ 4.5V
28
1
– M40Z111W:
SOH28 (MH)
VCC = 3.0V to 3.6V
THS = VSS 2.8V ≤ VPFD ≤ 3.0V
VCC = 2.7V to 3.3V
THS = VOUT 2.5 ≤ VPFD ≤ 2.7V
Figure 1. Logic Diagram
LESS THAN 15ns CHIP ENABLE ACCESS
PROPAGATION DELAY (for 5.0V device)
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY
V
CC
DESCRIPTION
The M40Z111/111W NVRAM Controller is a self-
contained device which converts a standard low-
power SRAM into a non-volatile memory.
THS
E
V
E
OUT
M40Z111
M40Z111W
A precision voltage reference and comparator
monitors the VCC input for an out-of-tolerance con-
dition.
CON
Table 1. Signal Names
THS
E
Threshold Select Input
Chip Enable Input
Conditioned Chip Enable Output
Supply Voltage Output
Supply Voltage
V
SS
AI02238B
ECON
VOUT
VCC
VSS
Ground
February 1999
1/12
M40Z111, M40Z111W
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
Storage Temperature (VCC Off)
0 to 70
°C
SNAPHAT
SOIC
–40 to 85
–55 to 125
TSTG
°C
(2)
TSLD
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
260
°C
V
VIO
VCC
IO
–0.3 to VCC +0.3
–0.3 to 7
V
Output Current
20
1
mA
W
PD
Power Dissipation
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Figure 2. SOIC Pin Connections
During a power failure, the SRAM is switched from
the VCC pin to the lithium cell within the SNAPHAT
to provide the energy required for data retention.
On a subsequent power-up, the SRAM remains
write protected until a valid power condition returns.
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
battery package to be mounted on top of the SOIC
package after the completion of the surface mount
process. Insertion of the SNAPHAT housing after
reflow preventspotential battery damagedueto the
high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion. The SOIC and battery
packages are shipped separately in plastic anti-
static tubes or in Tape & Reel form. For the 28 lead
SOIC, the battery package (i.e. SNAPHAT) part
number is "M4Z28-BR00SH1" or "M4Z32-
BR00SH1" (See Table 7).
V
1
28
V
E
OUT
NC
CC
2
27
NC
NC
NC
3
26
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E
4
25
5
24
23
V
V
6
CC
NC
7
M40Z111 22
M40Z111W
8
21
CC
NC
9
20
19
NC
NC
NC
10
11
12
13
14
18
17
THS
16
CON
V
15
NC
SS
AI02239B
OPERATION
The M40Z111/111W, as shown in Figure 4, can
control up to two standard low-power SRAMs.
These SRAMs must be configured to have the chip
enable input disable all other input signals. Most
slow, low-power SRAMs are configured like this,
however many fast SRAMs are not. During normal
operating conditions, the conditioned chip enable
(ECON) output pin follows the chip enable (E) input
pin with timing shown in Table 6. An internal switch
connects VCC to VOUT. This switch has a voltage
drop of less than 0.3V (IOUT1).
Warning:
NC = Not Connected.
DESCRIPTION
(cont’d)
When an invalid VCC condition occurs, the condi-
tioned chip enable (ECON) output is forced inactive
to write-protect the stored data in the SRAM.
2/12
M40Z111, M40Z111W
Figure 3. Hardware Hookup
3.3V or 5V
V
V
V
E
CC
OUT
CC
CMOS
SRAM
1N5817 or
MBR5120T3
0.1µF
0.1µF
M40Z111
E
CON
E
x8 or x16
Thereshold
THS
V
SS
AI02394
When VCC degrades during a power failure,ECON
is forced inactive independent of E. In this situation,
the SRAM is unconditionally write protected as VCC
falls below an out-of-tolerance threshold (VPFD).
The power fail detection value associated with VPFD
is selected by the THS pin and is shown in Table 5.
(Note: THS pin must be connected to either VSS or
VOUT). If chip enable access is in progress during
a power fail detection, that memory cycle continues
to completion before the memory is write protected.
If the memory cycle is not terminated within time
tWP, ECON is unconditionally driven high, write pro-
tecting the SRAM.
ECON is held inactive for tER (200ms maximum)
after the power supply has reached VPFD, inde-
pendent of the E input, to allow for processor
stabilization (see Figure 6).
DATA RETENTION LIFETIME CALCULATION
Most low power SRAMs on the market today can
be used with the M40Z111/111W NVRAM Control-
ler. There are, however some criteria which should
be used in making the final choice of which SRAM
to use. The SRAM must be designed in a way
where the chip enable input disables all other in-
puts to the SRAM. This allows inputs to the
M40Z111/111W and SRAMs to be Don’t Care once
VCC falls below VPFD (min). The SRAM should also
guarantee data retention down to VCC =2.0V. The
chip enable access time must be sufficient to meet
the system needs with the chip enable propagation
delays included. If the SRAM includes a second
A power failure during a write cycle may corrupt
data at the currently addressed location, but does
not jeopardize the rest of the SRAM’s contents. At
voltages below VPFD (min), the user can be assured
the memory will be write protected provided the
VCC fall time exceeds tF.
chip enable pin (E2), this pin should be tied to VOUT
.
As VCC continues to degrade, the internal switch
disconnects VCC and connects the internal battery
to VOUT. This occurs at the switchover voltage
(VSO). Below the VSO, the battery provides a volt-
age VOHB to the SRAM and can supply current
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular SRAMs
being evaluated. Most SRAMs specify a data re-
tention current at 3.0V.
IOUT2 (see Table 5). When VCC rises above VSO
,
VOUT is switched back to the supply voltage. Output
3/12
M40Z111, M40Z111W
Table 3. AC Measurement Condition
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
1.5V
Input and Output Timing Ref. Voltages
645Ω
DEVICE
Note that Output Hi-Z is defined as the point where data is no
longer driven.
UNDER
TEST
Manufacturers generally specify a typical condition
for room temperature along with a worst case
condition (generally atelevated temperatures). The
system level requirements will determine the
choice of which value to use. The data retention
current value of the SRAMs can then be added to
the ICCDR value of the M40Z111/111W to determine
the total current requirements for data retention.
The available battery capacity for the SNAPHAT of
your choice can then be divided by this current to
determine the amount of data retention available
(see Table 7). For more information on Battery
Storage Life refer to the Application Note AN1012.
1.75V
C
= 100pF
or 5pF
L
C
includes JIG capacitance
L
AI02326
µ
A ceramic bypass capacitor value of 0.1 F (as
shown in Figure 4) is recommended in order to
provide the needed filtering. In addition to tran-
sients that are caused by normal SRAM operation,
power cycling can generate negative voltage
spikes on VCC that drive it to values below VSS by
as much as one volt. These negative spikes can
cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage
spikes, ST recommends connecting a schottky di-
VCC NOISE AND NEGATIVE-GOING TRAN-
SIENTS
ICC transients, including those produced by output
switching, can produce voltage fluctuations, result-
ing in spikes on the VCC bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the VCC bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur.
ode from VCC to VSS (cathode connected to VCC
anode to VSS).
,
Table 4. Capacitance (1)
°
(TA = 25 C; f = 1MHz)
Symbol
Parameter
Test Condition
VIN = 0V
Min
Max
8
Unit
pF
CIN
Input Capacitance
Output Capacitance
(2)
COUT
VOUT = 0V
10
pF
Note:
1. Sampled only, not 100% tested.
2. Outputs deselected.
4/12
M40Z111, M40Z111W
Table 5A. DC Characteristics for M40Z111
(TA = 0 to 70°C; VCC = 4.5V to 5.5V)
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
Min
Typ
Max
Unit
µA
µA
mA
V
(1)
ILI
±1
±1
(1)
ILO
ICC
VIL
3
6
Input Low Voltage
–0.3
2.2
0.8
VIH
Input High Voltage
VCC + 0.3
0.4
V
VOL
VOH
VOHB
Output Low Voltage
Output High Voltage
VOH Battery Back-up
IOL = 4.0mA
IOH = –2.0mA
IOUT2 = 1.0µA
V
2.4
2.0
V
2.9
3.6
160
100
V
V
OUT > VCC –0.3
OUT > VCC –0.2
mA
mA
µA
nA
V
IOUT1
VOUT Current (Active)
V
IOUT2
ICCDR
THS
VOUT Current (Battery Back-up)
Data Retention Mode Current
VOUT > VBAT –0.3
100
150
VOUT
4.75
4.5
Threshold Select Voltage
VSS
4.5
4.2
Power-fail Deselect Voltage (THS = 0)
Power-fail Deselect Voltage (THS = 1)
Battery Back-up Switchover Voltage
4.6
4.35
3.0
V
VPFD
V
VSO
V
Note:
1. Outputs deselected.
5/12
M40Z111, M40Z111W
Table 5B. DC Characteristics for M40Z111W
(TA = 0 to 70°C; VCC = 3V to 3.6V or 2.7V to 3.3V)
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
Min
Typ
Max
Unit
µA
µA
mA
V
(1)
ILI
±1
±1
(1)
ILO
ICC
VIL
2
4
Input Low Voltage
–0.3
2.0
0.8
VIH
Input High Voltage
VCC + 0.3
0.4
V
VOL
VOH
VOHB
Output Low Voltage
Output High Voltage
VOH Battery Back-up
IOL = 4.0mA
IOH = –2.0mA
IOUT2 = 1.0µA
V
2.4
2.0
V
2.9
3.6
100
65
V
V
OUT > VCC –0.3
OUT > VCC –0.2
mA
mA
µA
nA
V
IOUT1
VOUT Current (Active)
V
IOUT2
ICCDR
THS
VOUT Current (Battery Back-up)
Data Retention Mode Current
VOUT > VBAT –0.3
100
150
VOUT
3.0
Threshold Select Voltage
VSS
2.8
2.5
Power-fail Deselect Voltage (THS = 0)
Power-fail Deselect Voltage (THS = 1)
Battery Back-up Switchover Voltage
2.9
2.6
2.5
V
VPFD
2.7
V
VSO
V
Note:
1. Outputs deselected.
6/12
M40Z111, M40Z111W
Table 6. Power Down/Up AC Characteristics
(TA = 0 to 70°C)
Symbol
Parameter
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSO VCC Fall Time
Min
300
10
Max
Unit
µs
µs
µs
ns
(1)
tF
(2)
tFB
tR
VPFD(min) to VPFD (max) VCC Rise Time
10
M40Z111
15
20
tEDL
Chip Enable Propagation Delay
Chip Enable Propagation Delay
M40Z111W
M40Z111
ns
10
ns
tEDH
M40Z111W
20
ns
tER
Chip Enable Recovery
Write Protect Time
40
40
40
200
150
250
ms
µs
µs
M40Z111
tWP
M40Z111W
Notes
µ
: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down Timing
V
CC
V
V
V
(max)
(min)
PFD
PFD
PFD
V
SO
tF
tFB
E
E
tWPT
V
OHB
CON
AI02396
7/12
M40Z111, M40Z111W
Figure 6. Power Up Timing
V
CC
V
V
V
(max)
(min)
PFD
PFD
PFD
V
SO
tR
tER
E
E
tEDH
tEDL
V
OHB
CON
AI02397
Table 7. Battery Table
Part Number
Description
Package
M4Z28-BR00SH1
M4Z32-BR00SH1
Lithium Battery (50mAh) SNAPHAT
Lithium Battery (130mAh) SNAPHAT
SH
SH
8/12
M40Z111, M40Z111W
ORDERING INFORMATION SCHEME
Example:
M40Z111W MH
1
TR
Supply Voltage
and Write Protect Voltage
Package
Temp. Range
Shipping Method
for SOIC
111
V
CC = 4.5V to 5.5V
MH(1) SOH28
1
0 to 70 °C
blank Tubes
THS = VSS 4.5V ≤ VPFD ≤ 4.75V
THS = VOUT 4.2V ≤ VPFD ≤ 4.5V
TR
Tape & Reel
111W VCC = 3.0V to 3.6V
THS = VSS 2.8V ≤ VPFD ≤ 3.0V
VCC = 2.7V to 3.3V
THS = VOUT 2.5 ≤ VPFD ≤ 2.7V
Note:
1. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
"M4ZxxBR00SH1" in plastic tube or "M4Zxx-BR00SH1TR" in Tape & Reel form.
Caution:
Do not place the SNAPHAT battery package "M4Zxx-BR00SH1" in conductive foam since will drain the lithium button-cell
battery.
For a list of available options (Package, etc...) or for further information on any aspect of this device, please
contact the STMicroelectronics Sales Office nearest to you.
9/12
M40Z111, M40Z111W
SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
eB
H
1.27
0.050
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
10/12
M40Z111, M40Z111W
SH - SNAPHAT Housing for 28 lead Plastic Small Outline
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
A2
A1
A
A3
L
eA
D
B
eB
E
SH
Drawing is not to scale.
11/12
M40Z111, M40Z111W
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
® SNAPHAT is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
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12/12
相关型号：
M40Z111MH1TR
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO28, 0.330 INCH, SNAPHAT, PLASTIC, SOIC-28
STMICROELECTR
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