M41T81M6E [STMICROELECTRONICS]
Serial access Real-Time Clock with alarm; 报警串行访问实时时钟
| 型号： | M41T81M6E |
| 厂家： | 
ST |
| 描述： | Serial access Real-Time Clock with alarm |
| 文件： | 总30页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M41T81
Serial access Real-Time Clock with alarm
Feature summary
■ Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
8
■ 32KHz crystal oscillator integrating load
capacitance (12.5pF) providing exceptional
oscillator stability and high crystal series
resistance operation
1
2
■ Serial interface supports I C bus (400kHz
protocol)
SO8 (M)
8-pin SOIC
■ Ultra-low battery supply current of 0.6µA
(typ@3V)
■ 2.0 to 5.5V clock operating voltage
■ Automatic switch-over and deselect circuitry
(for 3V application select M41T81S data sheet)
■ Power-down time stamp (HT bit) allowing
determination of time elapsed in battery back
up
■ Programmable alarm and interrupt function
(valid even during battery back-up mode)
■ Accurate programmable watchdog timer (from
62.5ms to 128s)
■ Software clock calibration to compensate
crystal deviation due to temperature
■ Operating temperature of –40 to 85°C
■ ECOPACK® package available
July 2006
Rev 8
1/30
www.st.com
1
Contents
M41T81
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
2.3
2.4
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
5
6
7
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/30
M41T81
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Square wave output frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO8 – 8-lead plastic small outline (150 mils body width), package mechanical data. . . . . 27
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/30
List of figures
M41T81
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8-pin SOIC (M) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Back-up mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4/30
M41T81
Summary description
1
Summary description
The M41T81 is a low power Serial RTC with a built-in 32.768kHz oscillator (external crystal
controlled). Eight bytes of the SRAM (see Table 2: Clock register map on page 14) are used
for the clock/calendar function and are configured in binary coded decimal (BCD) format. An
additional 12 bytes of SRAM provide status/control of Alarm, Watchdog and Square Wave
2
functions. Addresses and data are transferred serially via a two line, bi-directional I C
interface. The built-in address register is incremented automatically after each WRITE or
READ data byte.
The M41T81 has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the SRAM and clock operations can be supplied by a small lithium button
supply when a power failure occurs.
Functions available to the user include a non-volatile, time-of-day clock/calendar, Alarm
interrupts, Watchdog Timer and programmable Square Wave output. The eight clock
address locations contain the century, year, month, date, day, hour, minute, second and
tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year -
valid until year 2100), 30 and 31 day months are made automatically.
The M41T81 is supplied in an 8-pin SOIC.
Figure 1.
Logic diagram
VCC VBAT
M41T81
VSS
XI
XO
IRQ/FT/OUT/SQW
SCL
SDA
AI04613
5/30
Summary description
Table 1.
M41T81
Signal names
XI
XO
Oscillator input
Oscillator output
IRQ/OUT/FT/SQW
Interrupt / output driver / frequency test / square wave (open drain)
SDA
SCL
VBAT
VCC
VSS
NC
Serial data input/output
Serial clock input
Battery supply voltage
Supply voltage
Ground
No connect
NF
No function
Figure 2.
8-pin SOIC (M) connections
XI
XO
VBAT
VSS
1
8
7
6
5
VCC
2
3
4
IRQ/FT/OUT/SQW
SCL
SDA
M41T81
AI04769
6/30
M41T81
Summary description
Figure 3.
Block diagram
REAL TIME CLOCK
CALENDAR
32KHz
OSCILLATOR
CRYSTAL
RTC W/ALARM
& CALIBRATION
AFE
IRQ/FT/OUT/SQW(1,2)
WATCHDOG
SDA
I2C
INTERFACE
SQWE
SQUARE WAVE
SCL
FT
FREQUENCY TEST
OUTPUT DRIVER
WRITE
PROTECT
OUT
INTERNAL
POWER
VCC
VBAT
(3)
VSO
COMPARE
AI04616
1. Open drain output
2. Square Wave function has the highest priority on IRQ/FT/OUT/SQW output.
3. VSO = VBAT – 0.5V (typ)
7/30
Operation
M41T81
2
Operation
The M41T81 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 20 bytes
contained in the device can then be accessed sequentially in the following order:
st
●
●
●
●
●
●
●
●
●
●
●
●
●
1 Byte: tenths/hundredths of a second register
nd
2
3
Byte: seconds register
Byte: minutes register
rd
th
4 Byte: century/hours register
th
5 Byte: day register
th
6 Byte: date register
th
7 Byte: month register
th
8 Byte: year register
th
9 Byte: control register
th
10 Byte: watchdog register
th
th
11 - 16 Bytes: alarm registers
th
th
17 - 19 Bytes: reserved
th
20 Byte: square wave register
The M41T81 clock continually monitors V for an out-of-tolerance condition. Should V
CC
CC
fall below V , the device terminates an access in progress and resets the device address
SO
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. The device also
automatically switches over to the battery and powers down into an ultra low current mode
of operation to conserve battery life. As system power returns and V rises above V , the
CC
SO
battery is disconnected, and the power supply is switched to external V
.
CC
For more information on Battery Storage Life refer to Application Note AN1012.
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
●
●
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is High.
Changes in the data line, while the clock line is High, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
8/30
M41T81
Operation
2.1.2
Start data transfer
A change in the state of the data line, from high to Low, while the clock is High, defines the
START condition.
2.1.3
2.1.4
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the
STOP condition.
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
2.1.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line High to enable the master to generate the
STOP condition.
9/30
Operation
M41T81
Figure 4.
Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 5.
Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
MSB
LSB
DATA OUTPUT
BY RECEIVER
AI00601
2.2
READ mode
In this mode the master reads the M41T81 slave after setting the slave address (see
Figure 7 on page 11). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge
Bit, the word address 'An' is written to the on-chip address pointer. Next the START
condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1).
At this point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an Acknowledge Bit to the
slave transmitter. The address pointer is only incremented on reception of an Acknowledge
Clock. The M41T81 slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a Stop Condition or when the
pointer increments to any non-clock address (08h-13h).
Note:
This is true both in READ Mode and WRITE Mode.
10/30
M41T81
Operation
An alternate READ Mode may also be implemented whereby the master reads the M41T81
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 8 on page 11).
Figure 6.
Slave address location
R/W
START
SLAVE ADDRESS
A
1
1
0
1
0
0
0
AI00602
Figure 7.
READ mode sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (An)
SDA LINE
S
S
DATA n
DATA n+1
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n+X
P
AI00899
Figure 8.
Alternative READ mode sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00895
11/30
Operation
M41T81
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T81 slave receiver. Bus protocol is
shown in Figure 9 on page 12. Following the START condition and slave address, a logic '0'
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T81 slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
see Figure 6 on page 11 and again after it has received the word address and each data
byte.
2.4
Data retention mode
With valid V applied, the M41T81 can be accessed as described above with READ or
CC
WRITE Cycles. Should the supply voltage decay, the power input will be switched from the
V
pin to the battery when V falls below the Battery Back-up Switchover Voltage (V ).
CC
CC SO
At this time the clock registers will be maintained by the attached battery supply. On power-
up, when V returns to a nominal value, write protection continues for t (see Figure 10
CC
rec
on page 23, Table 11 on page 24).
For a further, more detailed review of lifetime calculations, please see Application Note
AN1012.
Figure 9.
WRITE mode sequence
BUSACTIVITY:
MASTER
SDA LINE
DATA n+1
S
DATA n
DATA n+X
P
BUSACTIVITY:
SLAVE
ADDRESS
AI00895
12/30
M41T81
Clock operation
3
Clock operation
The 20-byte Register Map (see Table 2 on page 14) is used to both set the clock and to read
the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of
Seconds, Seconds, Minutes, and Hours are contained within the first four registers.
Note:
The Tenths/Hundredths of Seconds cannot be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/Hours Register) contain the CENTURY
ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle,
either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial
state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain
the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month
and Years. The ninth clock register is the Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a
'1' will cause the oscillator to stop. If the device is expected to spend a significant amount of
time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0'
the oscillator restarts within one second.
The eight Clock Registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
3.1
3.2
Power-down time-stamp
When a power failure occurs, the HT Bit will automatically be set to a '1.' This will prevent the
clock from updating the TIMEKEEPER registers, and will allow the user to read the exact
time of the power-down event. Resetting the HT Bit to a '0' will allow the clock to update the
TIMEKEEPER registers with the current time. For more information, see Application Note
AN1572.
®
Clock registers
The M41T81 offers 20 internal registers which contain Clock, Alarm, Watchdog, Flag,
Square Wave and Control data. These registers are memory locations which contain
external (user accessible) and internal copies of the data (usually referred to as BiPORT
™
cells). The external copies are independent of internal functions except that they are
updated periodically by the simultaneous transfer of the incremented internal copy. The
internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock
address.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a Stop Condition or when
the pointer increments to any non-clock address (08h-13h).
Clock and Alarm Registers store data in BCD. Control, Watchdog and Square Wave
Registers store data in Binary Format.
13/30
Clock operation
M41T81
(1)
Table 2.
Addr
Clock register map
Function/range BCD
format
D7
D6
D5
D4
D3
D2
D1
D0
00h
01h
02h
0.1 seconds
0.01 seconds
Seconds
Seconds
Seconds
Minutes
00-99
00-59
00-59
ST
0
10 seconds
10 minutes
Minutes
Century/
hours
03h
CEB
CB
10 hours
Hours (24 hour format)
0-1/00-23
04h
05h
0
0
0
0
0
0
0
0
0
Day of week
Date: day of month
Month
Day
Date
01-7
01-31
01-12
00-99
10 date
06h
0
10M
Month
07h
10 years
Year
Year
08h
OUT
0
FT
S
Calibration
Control
Watchdog
Al month
Al date
Al hour
Al min
09h
BMB4
SQWE
RPT5
HT
BMB3
ABE
BMB2
BMB1
BMB0
RB1
RB0
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
AFE
RPT4
RPT3
RPT2
RPT1
WDF
0
Al 10M
Alarm month
01-12
01-31
00-23
00-59
00-59
AI 10 date
AI 10 hour
Alarm date
Alarm hour
Alarm 10 minutes
Alarm minutes
Alarm seconds
Alarm 10 seconds
Al sec
AF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Flags
10h
Reserved
Reserved
Reserved
SQW
11h
0
0
0
12h
0
0
0
13h
RS3
RS2
RS1
RS0
1. Keys:
S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to '0'
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
OUT = Output level
ABE = Alarm in Battery Back-up Mode Enable Bit
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag (Read only)
AF = Alarm Flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
14/30
M41T81
Clock operation
3.3
Calibrating the clock
The M41T81 is driven by a quartz controlled oscillator with a nominal frequency of
32,768Hz. The devices are tested not exceed 35 ppm (parts per million) oscillator
o
frequency error at 25 C, which equates to about +1.9 to –1.1 minutes per month (see
Figure 10 on page 16). When the Calibration circuit is properly employed, accuracy
improves to better than 2 ppm at 25°C.
The oscillation rate of crystals changes with temperature. The M41T81 design employs
periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 16. The
number of times pulses which are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five Calibration Bits found in the
Control Register. Adding counts speeds the clock up, subtracting counts slows the clock
down.
The Calibration Bits occupy the five lower order bits (D4-D0) in the Control Register 08h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register (see Figure 11 on page 16).
Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the
Calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a
total range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T81 may
require.
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration values,
including the number of seconds lost or gained in a given period, can be found in Application
®
Note AN934, “TIMEKEEPER CALIBRATION.” This allows the designer to give the end user
the ability to calibrate the clock as the environment requires, even if the final product is
packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the IRQ/FT/OUT/SQW pin. The pin will toggle at 512Hz, when the Stop Bit (ST, D7 of
01h) is '0,' the Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm Flag Enable Bit (AFE, D7
of 0Ah) is '0,' and the Square Wave Enable Bit (SQWE, D6 of 0Ah) is '0' and the Watchdog
Register (09h = 0) is reset.
Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the Calibration Byte
for correction. Note that setting or changing the Calibration Byte does not affect the
Frequency Test output frequency.
15/30
Clock operation
M41T81
The IRQ/FT/OUT/SQW pin is an open drain output which requires a pull-up resistor to V
CC
for proper operation. A 500-10k resistor is recommended in order to control the rise time.
The FT Bit is cleared on power-down.
Figure 10. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
2
∆F
F
= K x (T – TO)
–80
–100
–120
–140
–160
= –0.036 ppm/°C2 0.006 ppm/°C2
O = 25°C 5°C
K
T
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Figure 11. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
16/30
M41T81
Clock operation
3.4
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go
off at a prescribed time on a specific month, date, hour, minute, or second or repeat every
year, month, day, hour, minute, or second. It can also be programmed to go off while the
M41T81 is in the battery back-up mode to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 3 on page 18 shows
the possible configurations. Codes not listed in the table default to the once per second
mode to quickly alert the user of an incorrect alarm setting.
When the clock information matches the alarm clock settings based on the match criteria
defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set
(and SQWE is '0.'), the alarm condition activates the IRQ/FT/OUT/SQW pin.
Note:
If the address pointer is allowed to increment to the Flag Register address, an alarm
condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a
different address. It should also be noted that if the last address written is the “Alarm
Seconds,” the address pointer will increment to the Flag address, causing this situation to
occur.
The IRQ/FT/OUT/SQW output is cleared by a READ to the Flags Register as shown in
Figure 12. A subsequent READ of the Flags Register is necessary to see that the value of
the Alarm Flag has been reset to '0.'
The IRQ/FT/OUT/SQW pin can also be activated in the battery back-up mode. The
IRQ/FT/OUT/SQW will go low if an alarm occurs and both ABE (Alarm in Battery Back-up
Mode Enable) and AFE are set. Figure 13 illustrates the back-up mode alarm timing.
Figure 12. Alarm interrupt reset waveform
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/FT/OUT/SQW
AI04617
17/30
Clock operation
Figure 13. Back-up mode alarm waveform
M41T81
V
CC
V
SO
trec
ABE and AFE Bits
AF Bit in Flags
Register
IRQ/FT/OUT/SQW
HIGH-Z
AI05663
Table 3.
RPT5
Alarm repeat modes
RPT4
RPT3
RPT2
RPT1
Alarm setting
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Once per second
Once per minute
Once per hour
Once per day
Once per month
Once per year
3.5
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the Watchdog
Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order
bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1
second, and 11 = 4 seconds. The amount of time-out is then determined to be the
multiplication of the five-bit multiplier value with the resolution. (For example: writing
00001110 in the Watchdog Register = 3*1, or 3 seconds). If the processor does not reset
the timer within the specified period, the M41T81 sets the WDF (Watchdog Flag) and
generates a watchdog interrupt.
The watchdog timer can be reset by having the microprocessor perform a WRITE of the
Watchdog Register. The time-out period then starts over.
Should the watchdog timer time-out, a value of 00h needs to be written to the Watchdog
Register in order to clear the IRQ/FT/OUT/SQW pin. This will also disable the watchdog
function until it is again programmed correctly. A READ of the Flags Register will reset the
Watchdog Flag (Bit D7; Register 0Fh).
The watchdog function is automatically disabled upon power-up and the Watchdog Register
is cleared. If the watchdog function is set, the frequency test function is activated, and the
SQWE Bit is '0,' the watchdog function prevails and the frequency test function is denied.
18/30
M41T81
Clock operation
3.6
Square wave output
The M41T81 offers the user a programmable square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These
frequencies are listed in Table 4. Once the selection of the SQW frequency has been
completed, the IRQ/FT/OUT/SQW pin can be turned on and off under software control with
the Square Wave Enable Bit (SQWE) located in Register 0Ah.
Table 4.
Square wave output frequency
Square wave bits
Square wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
None
32.768
8.192
4.096
2.048
1.024
512
256
128
64
-
kHz
kHz
kHz
kHz
kHz
Hz
Hz
Hz
Hz
32
Hz
16
Hz
8
Hz
4
Hz
2
Hz
1
Hz
3.7
Century bit
Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the
CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
19/30
Clock operation
M41T81
3.8
Output driver pin
When the FT Bit, AFE Bit, SQWE Bit, and Watchdog Register are not set, the
IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the
Control Register. In other words, when D7 (OUT Bit) and D6 (FT Bit) of address location 08h
are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low.
Note:
The IRQ/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor.
3.9
Preferred initial power-on default
Upon initial application of power to the device, the following register bits are set to a '0' state:
Watchdog Register; AFE; ABE; SQWE; and FT. The following bits are set to a '1' state: ST;
OUT; and HT (see Table 5 on page 20).
Table 5.
Preferred default values
WATCHDOG
register(1)
Condition
ST
HT
Out
FT
AFE SQWE ABE
Initial power-up(2)
1
1
1
1
0
0
0
0
0
0
0
Subsequent power-up (with
battery back-up)(3)
UC
UC
UC
UC
UC
1. BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = unchanged
20/30
M41T81
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 6.
Sym
Absolute maximum ratings
Parameter
Value
Unit
Storage temperature (VCC off,
oscillator off)
TSTG
SOIC
–55 to 125
°C
V
Supply voltage
–0.3 to 7
260
V
CC
Lead-free lead finish(1)
°C
Lead solder temperature for 10
seconds
TSLD
Standard (SnPb)
lead finish(2)
240
°C
VIO
IO
Input or output voltages
Output current
–0.3 to Vcc+0.3
V
mA
W
20
1
PD
Power dissipation
1. For SO8 package, lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater
than 30 seconds).
2. For SO8 package, standard (SnPb) lead finish: Reflow at peak temperature of 240°C (total thermal budget not to exceed 180°C for between
90 to 150 seconds).
Caution:
Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-
up Mode
21/30
DC and AC parameters
M41T81
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
(1)
Table 7.
Operating and AC measurement conditions
Parameter
M41T81
Supply voltage (VCC
)
2.0 to 5.5V
–40 to 85°C
100pF
Ambient operating temperature (TA)
Load capacitance (CL)
Input rise and fall times
≤50ns
Input pulse voltages
0.2VCC to 0.8 VCC
0.3VCC to 0.7 VCC
Input and output timing ref. voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
Figure 14. AC measurement I/O waveform
0.8V
CC
0.7V
0.3V
CC
CC
0.2V
CC
AI02568
Table 8.
Symbol
Capacitance
Parameter(1) (2)
Min
Max
Unit
CIN
COUT
tLP
Input capacitance
Output capacitance
Low-pass filter input time constant (SDA and SCL)
7
pF
pF
ns
(3)
10
50
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
22/30
M41T81
DC and AC parameters
Table 9.
Sym
DC characteristics
Parameter
Test condition(1)
Min
Typ
Max
Unit
ILI
Input leakage current
Output leakage current
0V ≤VIN ≤VCC
0V ≤VOUT ≤VCC
1
1
µA
µA
µA
µA
V
ILO
ICC1 Supply current
ICC2 Supply current (standby)
Switch freq = 400kHz
SCL,SDA = VCC – 0.3V
400
100
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
–0.3
0.3VCC
VCC + 0.3
0.4
0.7VCC
V
IOL = 3.0mA
IOL = 10mA
V
V
OL
Output low voltage (open
drain)(2)
0.4
V
Pull-up supply voltage
(open drain)
IRQ/OUT/FT/SQW
5.5
3.5(5)
1
V
V
2.5(4)
3
(3)
VBAT
Battery supply voltage
TA = 25°C, VCC = 0V
IBAT Battery supply current
0.6
µA
oscillator on, VBAT = 3V
1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.0 to 5.5V (except where noted).
A
CC
2. For IRQ/FT/OUT/SQW pin (Open Drain)
3. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
4. After switchover (V ), V (min) can be 2.0V for crystal with R = 40KΩ.
SO
BAT
S
5. For rechargeable back-up, V
(max) may be considered V
.
CC
BAT
Table 10.
Sym
Crystal electrical characteristics
Parameter(1) (2)
Min
Resonant frequency
Typ
Max
Units
fO
RS
CL
32.768
kHz
kΩ
pF
Series resistance
Load capacitance
60
12.5
1. Externally supplied. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S:
1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or
http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T81. Circuit board layout considerations for the 32.768kHz crystal of minimum trace lengths and
isolation from RF generating signals should be taken into account.
Figure 15. Power down/up mode AC waveforms
V
CC
V
SO
tPD
trec
SDA
SCL
DON'T CARE
AI00596
23/30
DC and AC parameters
M41T81
Unit
Table 11. Power down/up AC characteristics
Symbol
Parameter(1) (2)
Min
Typ
Max
tPD
trec
SCL and SDA at VIH before power down
SCL and SDA at VIH after power Up
0
nS
µS
10
1.
V
fall time should not exceed 5mV/µs.
CC
2. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.0 to 5.5V (except where noted).
A
CC
Table 12. Power down/up trip points DC characteristics
Sym Min
Parameter(1) (2)
VSO Battery back-up switchover voltage VBAT – 0.80 VBAT – 0.50 VBAT – 0.30
Typ
Max
Unit
V
1. All voltages referenced to V
.
SS
2. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.0 to 5.5V (except where noted).
A
CC
Figure 16. Bus timing requirements sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
P
S
tLOW
SR
P
AI00589
24/30
M41T81
DC and AC parameters
Table 13. AC characteristics
Sym
Parameter(1)
Min
Typ
Max
Units
fSCL
tLOW
tHIGH
tR
SCL clock frequency
Clock low period
0
400
kHz
µs
1.3
600
Clock high period
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
300
300
ns
tF
ns
tHD:STA
600
600
ns
ns
(after this period the first clock pulse is
generated)
START condition setup time
tSU:STA
tSU:DAT
(only relevant for a repeated start condition)
Data setup time
100
0
ns
µs
ns
(2)
tHD:DAT
tSU:STO
Data hold time
STOP condition setup time
600
Time the bus must be free before a new
transmission can start
tBUF
1.3
µs
1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.0 to 5.5V (except where noted).
A
CC
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
25/30
Package mechanical information
M41T81
6
Package mechanical information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
26/30
M41T81
Package mechanical information
Figure 17. SO8 – 8-lead plastic small package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 14. SO8 – 8-lead plastic small outline (150 mils body width), package
mechanical data
Millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.75
0.25
0.069
0.010
0.10
1.25
0.28
0.17
0.004
0.049
0.011
0.007
0.48
0.23
0.10
5.00
6.20
4.00
–
0.019
0.009
0.004
0.197
0.244
0.157
–
c
ccc
D
4.90
6.00
3.90
1.27
4.80
5.80
3.80
–
0.193
0.236
0.154
0.050
0.189
0.228
0.150
–
E
E1
e
h
0.25
0°
0.50
8°
0.010
0°
0.020
8°
k
L
0.40
1.27
0.016
0.050
L1
1.04
0.041
27/30
Part numbering
M41T81
7
Part numbering
Table 15. Ordering information scheme
Example:
M41T
81
M
6
E
Device type
M41T
Supply voltage and write protect voltage
81 = VCC = 2.0 to 5.5V
Package
M = SO8
Temperature range
6 = –40°C to 85°C
Shipping method
For SO8:
E = ECOPACK® package, standard package
F = ECOPACK® package, tape & reel 24mm packing
For other options, or for more information on any aspect of this device, please contact the
ST Sales Office nearest you.
28/30
M41T81
Revision history
8
Revision history
Table 16. Revision history
Date
Revision
Revision details
December 2001
21-Jan-02
1.0
1.1
1.2
1.3
1.4
First issue
Fix table footnotes (Table 9, Table 10)
01-May-02
05-Jun-02
Modify reflow time and temperature footnote (Table 6)
Modify data retention text, trip points (Table 12)
Corrected supply voltage values (Table 6, Table 7)
10-Jun-02
Modify DC characteristics, crystal electrical table footnotes, preferred
default values (Table 9, Table 10, Table 5)
03-Jul-02
11-Oct-02
1.5
1.6
Add marketing status (Figure 2; Table 15); adjust footnotes (Figure 2;
Table 9)
Add embedded crystal package option (Figure 1, 3, 23; Table 16);
modified pre-existing mechanical drawing (Figure 17; Table 14).
21-Jan-03
05-Mar-03
12-Sep-03
1.7
1.8
2.0
Correct dimensions (Table 16); remove SNAPHAT® package option
Updated disclaimer, v2.2 template; add SOX18 package (Figure 2, 4;
Table 15)
Reformatted; update characteristics (Figure 4, 3, Figure 3, Figure 10,
Figure 13, Table 1, Table 6, Table 9, Table 12, Table 15)
27-Apr-04
17-Jun-04
3.0
4.0
Reformatted; add lead-free information; add dual footprint
connections (Figure 5;Table 6, Table 15)
7-Sep-04
5.0
6.0
Update footprint and maximum ratings (Figure 5; Table 6)
Update max ratings (Table 6)
13-Sep-04
Remove SOX18 and SOX28 references (Features summary,
Figure 1; Table 1, Table 6, Table 10, Table 15)
03-Jun-05
7
8
Changed document to new template; Updated package mechanical
data in Section 6: Package mechanical information; small text
changes for entire document; ecopack compliant.
12-Jul-2006
29/30
M41T81
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