M58BF008ZA_技术文档

M58BF008

8 Mbit (256Kb x32, Burst) Flash Memory

PRELIMINARY DATA

■ SUPPLY VOLTAGE

– V = 5V Supply Voltage

DD

– V

= 3.3V Input/Output Supply Voltage

DDQ

– Optional V = 12V for fast Program and Erase

PP

■ CONFIGURABLE OPTIONS

BGA

– Synchronous or Asynchronous write mode

– Burst Wrap/No-wrap default

– Critical Word X (3 or 4) and Burst Word

Y (1 or 2) latency times

LBGA80 (ZA)

10 x 8 solder balls

PQFP80 (D)

■ ACCESS TIME

– Synchronous X-Y-Y-Y Burst Read

up to 40MHz

– Asynchronous Read: 100ns

■ PROGRAMMING TIME: 10µs typical

■ MEMORY BLOCKS

Figure 1. Logic Diagram

V

– 32 equal Main blocks of 256 Kbit

– One Overlay block of 256 Kbit

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: F0h

DD DDQ PP

18

32

A17-A0

DQ31-DQ0

CLK

RP

E

– Version Code: 0-7h

DESCRIPTION

The M58BF008 is a family of 8 Mbit non-volatile

Flash memories that can be erased electrically at

the blocklevel and programmed in-system. Family

members are configured during product testing for

a specific Synchronous or Asynchronous Write

mode, a Burst default of Wrap or No-wrap and for

Critical Word X = 3 or 4 and Burst Word Y = 1 or 2

latency times. The Main memory array matrix al-

lows each of the 32 equal blocks of 256 Kbit to be

erased separately and re-programmed without af-

fecting other blocks. The memory features a

256 Kbit Overlay block having the same address

space asthe firstMain memory block. The Overlay

block provides a secure storage area that is con-

trolled by special Instructions and an external in-

G

M58BF008

GD

W

LBA

WR

BAA

V

SS

V

SSQ

put. A separate supply V

allows the Input/

DDQ

Output signals to be at 3.3V levels, while the main

AI02656B

supply V is 5V.

DD

February 2000

1/36

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M58BF008

Figure 2. LBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A16

A15

A13

A11

A9

A8

A4

A3

A17

DQ1

A14

DQ2

DQ3

DQ5

DQ6

DQ9

DQ12

DQ13

RP

A12

A10

A7

A6

A0

A1

A5

A2

DQ0

V

DQ31

DQ28

DQ27

DQ25

DQ24

DQ19

DQ17

DQ16

DD

SS

DQ4

V

DU

V

DQ30

DQ29

DQ26

DQ23

DQ201

DQ21

DU

DDQ

PP

DDQ

DQ7

V

DU

V

SSQ

DDQ

SSQ

DQ8

V

G

H

J

DQ10

DQ11

DQ14

DQ15

V

DDQ

SSQ

DDQ

BAA

CLK

LBA

V

DQ22

SS

DD

G

W

DQ18

GD

K

E

WR

AI02668

2/36

M58BF008

Figure 3. PQFP Connections

73

DQ16

DQ17

DQ18

DQ19

1

DQ15

DQ14

DQ13

DQ12

V

DDQ

SSQ

DDQ

V

SSQ

DQ20

DQ11

DQ10

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

12

M58BF008

53

V

DDQ

SSQ

DDQ

V

SSQ

DQ28

DQ3

DQ2

DQ1

DQ0

NC

DQ29

DQ30

DQ31

NC

A0

NC

A1

A17

A16

A2

32

AI02661

3/36

M58BF008

Table 1. Signal Names

A Command Interface decodes the Instructions

written to the memory to access or modify the

memory content, to toggle the enable/disable of

read access to the Overlay block, to toggle the

burst Wrap/No-wrap or to toggle the Synchronous

or Asynchronous Read mode. A Program/Erase

Controller (P/E.C.) executes the algorithms taking

care of the timings necessary for program and

erase operations. The P/E.C. also takes care of

verification to unburden the system microproces-

sor, while a Status Register tracks the status of

each operation.

The following Instructions are executed by the

memory in either Asynchronous or Synchronous

mode.

Access or modify memory content:

- Read Array

A0-A17

DQ0-DQ31

CLK

RP

Address Inputs

Data Input/Output

System Clock

Reset/Power-down

Chip Enable

E

G

Output Enable

GD

Output Disable

Write Enable

W

LBA

WR

Load Burst Address

Write/Read

BAA

Burst Address Advance

Supply Voltage

- Read or Clear Status Register

- Read Electronic Signature

V

DD

- Erase Main memory block or Overlay block

- Program Main memory or Overlay memory

- Program Erase Suspend or Resume

Toggle:

– Asynchronous/Synchronous Read

– Overlay Block Read Enable/Disable

– Burst Wrap/No-wrap

Supply Voltage for Input/Output

Buffers

V

DDQ

V

Program Supply Voltage

Ground

PP

V

SS

V

Input/Output Ground

Not Connected Internally

Don’t Use as Internally Connected

SSQ

NC

DU

The M58BF008 devices are offered in PQFP80

and LBGA80 1.0mm ball pitch packages.

When the V supply is at V this prevents pro-

PP

SS

gramming and erasure of the memory blocks and,

in addition, it prevents reading of the Overlay

block. When the V

supply is at 5V it enables

PP

both in-system program/erase and read access to

the Overlay block. For a limited time and number

of program/erase cycles the V supply may be

PP

raised to 12V to provide fast program and erase

times.

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

V

T

A

–40 to 125

–55 to 150

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input Output Voltage

Supply Voltage

T

BIAS

T

STG

V

–0.6 to V

+0.6

IO

DDQ

–0.6 to 7

V

, V

DD DDQ

V

Program Voltage

–0.6 to 13.5

V

PP

Note: 1. Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device.

4/36

M58BF008

ORGANISATION

status orsignatures read from the memory, or they

input data to be programmed or Instruction com-

mands to the Command Interface.

The M58BF008 has a data path width of 32 bit

(Double-Word) and is organised as a Main memo-

ry array of 32 blocks of 256 Kbit plus an Overlay

block of 256 Kbit having the same address space

as the first Main memory block. The memory map

is shown in Table 3.

Asynchronous mode

Memory control is provided by Chip Enable E, Out-

put Enable G and Write Enable W for read and

write operations.

The memory is addressed by A0-A17 which are

static for Asynchronous or latched for Synchro-

nous operation. Data Input/Output is static or

latched on DQ0-DQ31, these signals output data,

Synchronous mode

Memory control is provided by Load Burst Address

LBA which loads a read or write address. A Syn-

chronous Single Read or a Synchronous Burst

Read is performed under control of Output Enable

G. Synchronous Write is controlled by Write/Read

Enable WR, Load Burst Address LBA and Write

Enable W. Internal advance of the burst address is

controlled by Burst Address Advance BAA.

Table 3. Block Addresses

Size

#

Address Range

(Kbit)

256

31

3E000-3FFFF

3C000-3DFFF

3A000-3BFFF

38000-39FFF

36000-37FFF

34000-35FFF

32000-33FFF

30000-31FFF

2E000-2FFFF

2C000-2DFFF

2A000-2BFFF

28000-29FFF

26000-27FFF

24000-25FFF

22000-23FFF

20000-21FFF

1E000-1FFFF

1C000-1DFFF

1A000-1BFFF

18000-19FFF

16000-17FFF

14000-15FFF

12000-13FFF

10000-11FFF

0E000-0FFFF

0C000-0DFFF

0A000-0BFFF

08000-09FFF

06000-07FFF

04000-05FFF

02000-03FFF

00000-01FFF

30

SIGNAL DESCRIPTIONS

29

See Figure 1 and Table 1.

Address Inputs (A0-A17). The address signal

A17 is the MSB and A0 the LSB.

28

27

In the Asynchronous mode the addresses must be

stable before Chip Enable E and Write Enable W

26

25

go to V . They must remain stable during the read

IL

24

or write cycle.

23

In the Synchronous modes, the addresses are

latched by the rising edge of the System Clock

CLK when both Latch Burst Address LBA and

Chip Enable E are at V . The addresses are

latched for a read operation if Write/Read WR is at

22

21

IL

20

19

V

IH

or for a write operation when it is at V .

IL

18

Data Input/Output (DQ0-DQ31). The data signal

DQ31 is the MSB and DQ0 the LSB. Commands

are input on DQ0-DQ7.

Data input is a Double-Word to be programmed in

the memory or an Instruction command to the

Command Interface. Data is read from the Main or

Overlay memory blocks, the Status Register or the

Electronic Signature.

In the Asynchronous mode data is read when the

addresses are stable and Chip Enable E and Out-

put Enable G are at V . Commands or address/

data are written when Chip Enable E and Write W

17

16

15

14

13

12

11

10

IL

9

8

are at V .

IL

7

In the Synchronous mode, after addresses are

latched, data is read on a rising edge of the Sys-

tem Clock CLK when Chip Enable E is at V and

if Output Enable was at V on the previous rising

clock edge. Data is written on a rising edge of the

6

IL

5

IL

4

3

System Clock CLK when Chip Enable E and Write

Enable W are at V .

IL

2

The outputs are high impedance when Chip En-

able E or OutputEnable G are at V , or when Out-

put Disable GD is at V . Outputs are also high

impedance when System Reset RP is at V .

1

IH

0

IL

Overlay Block

IL

5/36

M58BF008

System Clock (CLK). All synchronous signals

are input and output relative to the System Clock.

Synchronous input signals must respect the set-

up and hold times relative to the System Clock ris-

ing edge.

Load Burst Address (LBA). In the Asynchro-

nous mode Load Burst Address LBA is Don’t Care

(but if it falls during an asynchronous read then a

new read cycle is started). In the Synchronous

mode Load Burst Address LBAenables latching of

the burst starting address for Synchronous read or

write. The address is latched on the rising edge of

the System Clock CLK if Load Burst Address LBA

Reset/Power-down (RP). The

down RP input provides a hardware reset for the

memory. When Reset/Power-down RP is at V

Reset/Power-

IL

is at V .

IL

the memory is reset and in the Power-down mode.

In this mode the outputs are high impedance and

the current consumption is minimised. When Re-

Write/Read (WR). Write/Read WR is used in

Synchronous mode to control write or read opera-

set/Power-down RP is at V the memory is in the

tions. If Load Burst Address LBA is at V and

IH

IL

normal operating mode. When leaving the Power-

down mode the memory enters the Asynchronous

Read Array mode.

Write/Read is at V then the rising edge of the

IL

System Clock CLK latches a write address. If

Write/Read is at V then a read address is

IH

latched.

Reset/Power-down has a weak pull-up resistor to

V

and will assume a high level if not connect-

Write/Read has a weak pull-up resistor to V

DDQ

and will assume a high level if not externally con-

nected.

DDQ

ed.

Chip Enable (E). When the Chip Enable E input

is at V it activates the memory control logic, input

Burst Address Advance (BAA). When

Burst

IL

buffers, decoders and sense amplifiers. When

Address Advance BAA is at V , the rising edge of

IL

Chip Enable E is at V the memory is deselected

the System Clock CLK advances the burst ad-

IH

and the power consumption is reduced to the

standby level.

dress. When Burst Address Advance BAA is at V

the advance is suspended.

IH

Output Enable (G). Output Enable G controls the

data output buffers. In the Asynchronous mode

V

Supply Voltage. The supply V

provides

DD

the power to the internal circuits of the memory.

data is output when Output Enable G is at V . In

The V supply voltage is 4.5 to 5.5V.

IL

DD

the Synchronous mode, Output Enable G is sam-

V

Input/Output Supply Voltage. The Input/

DDQ

Output supply V

pled on the rising edge of the System Clock CLK.

provides the power for the in-

DDQ

If Output Enable E is at V then valid output data

IL

put/outputs of the memory, independent from the

on DQ0-DQ31 can be read at the next rising edge

of the System Clock CLK.

supply V . The Input/Output supply V may

DD

DDQ

be connected to the V

supply or it can use a

DD

Output Disable (GD). In

the

Asynchronous

separate supply of 3.0 to 3.6V.

mode thedata outputs DQ0-DQ31 are high imped-

V

Program/Erase Supply Voltage. The Pro-

PP

ance when Output Disable GD is at V , irrespec-

IL

gram/Erase supply V is used for programming

PP

tive of the state of Output Enable G. In

Synchronous mode Output Disable GD is sam-

pled, together with Output Enable G, on the rising

edge of the System Clock CLK. If Output Disable

and erase operations. The memory normally exe-

cutes program and erase operations at the supply

V

PP1

voltage levels.

In a manufacturing environment, programming

may be speeded up by applying a higher V lev-

el to the V Program/Erase Supply. This is not in-

is at V then the data outputs DQ0-DQ31 are high

IL

PPH

impedance at the next rising edge of the System

Clock CLK, irrespective of the state of Output En-

able G.

PP

tended for extended use. The V

supply may be

PPH

applied for a total of 80 hours maximum and during

program and erase for a maximum of 1000 cycles.

Stressing the device beyond these limits could

damage the device.

Output Disable has a weak pull-up resistor to

V

and will assume a high level if not externally

DDQ

connected.

Write Enable (W). The Write Enable W input

controls the writing of commands or input data. In

the Asynchronous mode commands or data are

written when Chip Enable E and Write Enable W

When V

Program/Erase supply is at V

all

SS

PP

blocks are protected from programming or erase.

Leaving V floating is equivalent to connecting it

PP

to V due to an internal pull-down circuit.

SS

are at V . In the Synchronous mode with Chip En-

IL

Ground (V and V

reference for the internal supply voltage V . The

Ground V

supply V

). The Ground V is the

SS

SSQ

able E at V , input data is sampled if Write Enable

IL

DD

W is at V on the rising edge of the System Clock

IL

is the reference for the Input/Output

SSQ

CLK.

.

DDQ

6/36

M58BF008

DEVICE OPERATIONS

See Table 4 for Asynchronous or Synchronous

Bus Operations.

power-down mode when Reset/Power-Down RP

is Low.

Read. Read operations are used to output the

contents of the memory, the Electronic Signature

or the Status Register. The data read depends on

the previous Instruction given to the memory.

In the Asynchronous mode the memory is selected

with Chip Enable E Low. The data outputs are en-

abled by Output Enable G Low or disabled by Out-

put Disable GD Low. Data is input by Write Enable

W Low.

In the Synchronous mode the memory latches ad-

dresses and data (input or output) on the rising

edge of the System Clock CLK. Burst address

latching is enabled by Load Burst Address LBA

Low with Write/Read WR Low for a write cycle or

High for a read cycle.

Read operations can be Asynchronous or Syn-

chronous, witha single or burst read. On power-up

the device is in Asynchronous read mode, the In-

struction Asynchronous/Synchronous Read Tog-

gle ART can be used to enter the Synchronous

read mode.

– Asynchronous Read. To read a data Double-

Word in Asynchronous mode the address inputs

must be stable and Chip Enable E must be Low

during the read cycle. Output Enable G must be

Low and Output Disable GD High. The Load

Burst Address LBA is Don’t Care, but its falling

edge will start a new read cycle.

Data outputs are enabled for reading on the rising

edge of the System Clock CLK when Output En-

able G is low. Data is input on the rising edge of

the System Clock CLK when Write Enable W is

Low.

The memory is deselected and in standby mode

when Chip Enable E is High, and it is reset or in

(1,2)

Table 4. Bus Operations

Operation

Asynchronous Read

Asynchronous Write

Synchronous Read

RP

CLK

X

E

LBA

X

WR

X

W

GD

G

DQ0-DQ31

Data Output

Data Input

V

IH

IL

IH

IL

V

X

IH

IL

IH

V

X

Data Output

IH

IL

Synchronous Write Address for

Read

V

X

IH

IL

IH

Synchronous Write Address for

Command

V

IH

IL

IH

V

Synchronous Data Write

Output Disabled by G

Output Disabled by GD

Standby

Data Input

Hi-Z

IH

IL

IH

IL

IH

X

V

X

Hi-Z

IL

X

Hi-Z

IH

V

Reset / Power-down

X

Hi-Z

IL

Note: 1. See Device Operations, Instructions and Commands, sections for more details.

2. X=V or V

IL

IH.

Table 5. Read Electronic Signature

Code

Manufacturer

Device

RP

E

G

W

A0

A1

A2-A17

DQ0-DQ31

00000020h

000000F0h

0000000xh

V

Don’t Care

IH

IL

IH

IL

V

IH

IL

V

Version

IH

IL

IH

Note: ”x” = version level. The first version is ”0” and it can have a value up to ”7”.

7/36

M58BF008

– Synchronous Single Read. To read a single

data Double-Word in Synchronous mode Chip

Enable E must be Low. Load Burst Address

LBA must be Low for one System Clock CLK ris-

ing edgewith Write/Read WR High. This latches

the read address, after which the address bus

inputs are Don’t Care. The Output Enable G is

Low for a single System Clock CLK cycle. The

Double-Word of valid data is output on the next

System Clock CLK rising edge.

then a read operation will read the contents of the

Main block at the same address.

When the Overlay block is enabled for reading,

only this one block of 256 Kbit is accesible and

none of the other Main blocks may be accessed,

the address signals A13-A17 are Don’t Care.

Read Electronic Signature. The memory con-

tains three Electronic Signature codes identifying

the manufacturer, device and version, which can

be read after giving the Instruction RSIG. The

manufacturer code 00000020h is read when the

– Synchronous Burst Read. To read a burst of

four Double-Words in Synchronous mode Chip

Enable /E must be Low. Load Burst Address

LBA must be Low for one System Clock CLK ris-

ing edgewith Write/Read WR High. This latches

the first address of the burst sequence, after

which the address bus inputs are Don’t Care.

The Output Enable G is driven Low before the

burst output sequence. Four Double-Words of

data are output on the subsequent System

Clock CLK rising edges if Burst Address Ad-

vance BAA is maintained Low. The address ad-

vance for synchronous burst read is suspended

if Burst Address Advance BAA goes High and

the output data remains constant. The data bus

will go high impedance on the rising edge of the

System Clock CLK after Output Enable G goes

High.

address inputs A0 and A1 are at V . The device

IL

code 000000F0h is read when A0 is at V and A1

IH

is at V . The version code 0000000xh is read

IL

when A0 is at V and A1 is at V . The codes are

IL

IH

read on DQ0-DQ31, all other address signal inputs

are Don’t Care. See Table 5.

Write. Write operations are used to give com-

mands to the memory that latch input data and ad-

dresses to program or block addresses to erase.

– Asynchronous Write. To write data in the

Asynchronous mode the address inputs must

be stable and Chip Enable E must be Low dur-

ing the write cycle. Write W must be Low and in-

put data valid on the rising edge is Write W.

– Synchronous Write. To write input data in

Synchronous mode Chip Enable E must be

Low. Load Burst Address LBA must be Low for

one System Clock CLK rising edge with Write/

Read WR Low. This latches the write address,

after which the address bus inputs are Don’t

Care. When Write Enable W is Low input data is

latched on the next System Clock CLK rising

edge.

The burst timing depends on the device config-

uration for the Critical Word X and Burst Word Y

latency times and the choice of wrap or no-wrap

for burst addresses. The operation burst wrap is

shown in Table 13. The wrap sequence uses

only the address bits A0 and A1 and does not

repeat after the last Double-Word has been out-

put.

Output Disable. The data outputs are high im-

pedance when the Output Enable G is High or

when the Output Disable GD is Low, independent

of the level on Output Enable G.

Read Overlay Block. The Overlay block can be

read, as for a Main block, after it has been en-

abled. To enable the Overlay block the Overlay

Block Enable bit OBEB and the Overlay Block Sta-

tus bit OBS in the Status Register must be set to

’1’ - see Table 9.

Standby. The memory is in standby when the P/

E.C. is not running, the memory is in read mode

and Chip Enable E is High. The power consump-

tion is reduced to the standby level and the outputs

are high impedance, independent of the Output

Enable G or Write Enable W inputs.

If Chip Enable goes High during a program or

erase operation the device enters the standby

mode when the internal algorithm has finished.

The Overlay Block Enable bit OBEB can be set to

’1’ in three ways - see Table 10:

– By Toggling the Reset/Power-Down signal RP

with the V Program/Erase supply in the range

PP

V

PP1

or V

. V out of range will reset the

PPH PP

OBEB bit to ’0’.

– By a leaving power-on reset with V Program/

Reset/Power-down. During power-down all in-

ternal circuits are switched off, the memory is de-

selected and the outputs are high impedance. The

memory is in Power-down mode when Reset/Pow-

er-down RP is Low. The power consumption is re-

duced to the power-down level, independent of the

Chip Enable E, Load Burst Address LBA, Output

Enable G or Write Enable W inputs.

PP

Erase supply in the range V

orV

. V out

PP1

PPH PP

of range will reset the OBEB bit to ’0’.

– By giving the Overlay Block Enable/Disable for

Read Instruction OBT.

The Overlay Block Status bit OBS monitors the

V

Program/Erase supply and will be set to ’1’

PP

when in the range V

or V

. The Overlay

PP1

PPH

If Reset/Power-down RP is pulled Low during a

program or erase operation this is aborted and the

memory content is no longer valid.

block is enabled with OBEB at ’1’ but will not be

read unless OBS status bit is also at ’1’. If it is not

8/36

M58BF008

INSTRUCTIONS AND COMMANDS

The V Program and Erase Supply Voltage must

PP

be within the range V

orV

for programming

PP1

PPH

The Instructions are listed in Tables 6 and 7. They

may be broadly divided into two types, those that

access or modify the memory content and those

that toggle a mode or function.

or erasure. If V

out of range, the program or

PP

erase algorithms do not start and Status Register

bit V Status V will be set to ’1’.

PP

PPS

The Instructions that access or modify the memory

content include:

Table 6. Commands

Code

– Read Memory Array (RD)

– Read Status Register (RSR) and Clear Status

Register (CLRS)

Command

02h

04h

Overlay Block Erase Set-up

Overlay Block Program Set-up

– Read Electronic Signature (RSIG)

– Erase (EE) and Overlay Block Erase (OBEE)

– Program (PG) and Overlay Block Program (OB-

PG)

Overlay Block Read Enable/

Disable

06h

– Program or Erase Suspend (PES) and Program

or Erase Resume (PER)

0Dh

20h

30h

40h

50h

Overlay Block Erase Confirm

Erase Set-up

The Instructions that toggle a mode or function in-

clude:

– Asynchronous/Synchronous Read mode Tog-

gle (ART)

Wrap/No-wrap Burst Toggle

Program Set-up

– Wrap/No-wrap Burst mode Toggle (WBT)

– Overlay Block Enable/Disable function Toggle

(OBT)

Clear Status Register

Asynchronous/Synchronous

Read Toggle

60h

Instructions are written, in one or more write cy-

cles, to the memory Command Interface (C.I.) for

decoding. The Command Interface is reset to

Read Memory Array at power-up, when exiting

from power-down. Any invalid sequence of com-

mands will also reset the Command Interface to

Read Memory Array.

A Program/Erase Controller (P/E.C.) handles all

the timing and verifies the correct execution of the

Program or Erase instructions. The P/E.C. has a

Status Register which monitors the operations and

which may be read at any time during program or

erase. The Status Register bits indicate the oper-

ation and exit status of the internal algorithms.

70h

90h

B0h

Read Status Register

Read Electronic Signature

Program/Erase Suspend

Program/Erase Resume or

Erase Confirm

D0h

FFh

Read Memory Array

9/36

M58BF008

Table 7. Instructions

1st Cycle

Address

2nd Cycle

Address.

Mne-

Instruction

monic

Cycles

Operation

Data

Operation

Data

Read Memory

RD

1+

1

Write

00000h

FFh

Read Address Data Output

Read

Array

Read Status

Register

Status

RSR

Write

70h

50h

Read

X

Register

Clear Status

CLRS

Register

Read Electronic

RSIG

Signature

Address

Electronic

Signature

1+++

Write

00000h

90h

20h

02h

Read

Write

Signature

EE

Erase

2

Block Address

D0h

0Dh

Overlay Block

Erase

Overlay Block

Address

OBEE

Program

Address

PG

Program

2

Write

00000h

40h

04h

Write

Data Input

Overlay Block

Program

Address

Overlay Block

Program

OBPG

Program/Erase

Suspend

PES

PER

ART

WBT

1

Write

00000h

B0h

D0h

60h

30h

Program/Erase

Resume

Asynch/Synch

Read Toggle

Wrap//No-wrap

Burst Toggle

Overlay Block

Read En/Dis

Toggle

OBT

1+

Write

00000h

06h

Read

Read Address Data Output

Read Memory Array (RD). The Read Memory

Array instruction consists of one write cycle giving

the command FFh at the address 00000h. Subse-

quent read operations will read the addressed lo-

cation and output the memory data. The data can

be read from the Main memory Array or the Over-

lay memory block if it is enabled.

Read Status Register (RSR). The Read Status

Register instruction consists of one write cycle giv-

ing the command 70h at the address 00000h. Sub-

sequent read operations will output the Status

Register contents. See Table 8 for an explanation

of the Status Register bits. The Status Register in-

dicates when a program or Erase operation is

complete and its success or failure. The Status

Register also indicates if the Overlay block is ac-

cessible for reading. The Read Status Register in-

struction may be given at any time, including while

a program or erase operation in progress.

Clear Status Register (CLRS). The Clear Status

Register instruction consists of one write cycle giv-

ing the command 50h at the address 00000h. The

Clear Status Register command clears the bits 3,

4 and 5 of the Status Registerif they have been set

to ’1’ by the P/E.C. operation. The Clear Status

Register command should be given after an error

has been detected and before any new operation

is attempted. A Read Memory Array command

should also be given before data can be read from

the memory array.

Read Electronic Signature (RSIG). The Read

Electronic Signature instruction consists of a first

write cycle giving the command 90h at the address

00000h. This is followed by three read operations

at addresses xxxx0h, xxxx1h and xxxx2h which

output the manufacturer, device and version

codes respectively.

10/36

M58BF008

Table 8. Status Register Bits

Mne-

Logic

Level

Bit

Name

Definition

Ready

Note

monic

’1’

’0’

‘1’

Indicates the P/E.C. status, check during

Program or Erase

P/ECS

7

P/E.C. Status

Busy

Suspend

On Program/Erase Suspend instruction both

P/ECS and PESS bits are set to ‘1’.

Either ES bit or PS bit is set to ‘1’.

PESS and either ES or PS bits remain at ‘1’

until Erase Resume instruction is given.

Program/Erase

Suspend Status

PESS

ES

6

5

In Progress or

Completed

‘0’

’1’

Erase Error or

Erase Suspend

ES bit is set to ‘1’ if either PESS instruction is

given or Erase operation fails. If ES bit is ‘1’,

check PESS bit.

Erase Status

’0’

’1’

Erase Success

Program Error or

Program Suspend

PS bit is set to ‘1’ if either PESS instruction is

given or Program operation fails. If PS bit is ‘1’,

check PESS bit.

PS

4

3

Program Status

’0’

’1’

Program Success

V

Invalid

OK

VPPS bit is set to ‘1’ if initially V is not V

PPH

PP

V

Status

VPPS

nor V

are executed.

, when Program or Erase Instruction

PP

PP1

’0’

Reserved

OBEB

2

1

’1’

’0’

’1’

’0’

Enabled

Overlay Block

Enable Bit

OBEB bit is set to ‘1’ when Overlay Block is

Enabled.

Disabled

Activated

Not Activated

OBS bit is set to ‘1’ when OBEB is ‘1’ and V

Overlay Block

Status

PP

OBS

0

is in the range V

or V

.

PPH

PP1

Erase (EE). The Erase instruction consists of two

write cycles, the first is the erase set-up command

20h at the address 00000h. This is followed by the

Erase Confirm command D0h written to an ad-

dress within the block to be erased. If the second

is not the Erase Confirm command the Status

Register bits 4 and 5 are set to ’1’ and the instruc-

tion aborts. While erasing is in progress only the

Read Status Registerand Erase Suspend instruc-

tions are valid.

Status Register bit 3 is set to ’1’ if V is not within

PP

the allowed ranges when erasing is attempted or if

it falls out of the ranges during erase execution.

The erase operation aborts if V drops out of the

PP

allowed range or if Reset/Power-down RP falls to

V . As data integrity cannot be guaranteed when

IL

the erase operation is aborted, the erase must be

repeated.

A Clear Status Register instruction must be given

to clear the Status Register bits.

Blocks are erased one at a time. An erase opera-

tion sets all bits in a block to ’1’. The erase algo-

rithm automatically programs all bits to ’0’ before

erasing the block to all ’1’s.

Overlay Block Erase (OBEE). The

Overlay

Block Erase instruction consists of two write cy-

cles, the first is the Overlay block erase set-up

command 02h at the address 00000h. This is fol-

lowed by the Overlay Block Erase Confirm com-

mand 0Dh written to an address within the Overlay

block. If the secondis not the Overlay Block Erase

Confirm command the Status Register bit 5 is set

to ’1’ and the instruction aborts. While erasing is in

progress only the Read Status Register instruction

is valid.

Read operations output the Status Register after

the erase operation has started. The Status Reg-

ister bit 7 is ’0’ while the erase is in progress and is

set to ’1’ when it is completed. After completion the

Status Register bit 5 is set to ’1’ if there has been

an erase failure.

Erasure should not be attempted when the V

PP

Program/Erase Supply Voltage is out of the range

The operation is executed as described for the

Erase (EE) instruction of the Main memory array.

V

or V as the results will be uncertain. The

PP1

PPH

A Clear Status Register instruction must be given

to clear the Status Register bits.

11/36

M58BF008

Program (PG). The Program instruction consists

of two write cycles, the first is the program set-up

command 40h at the address 00000h. This is fol-

lowed by a second write cycle to latch the address

and data to be programmed. This second com-

mand starts the P/E.C. A program operation can

be aborted by writing FFFFFFFFh to any address

after the program set-up command has been giv-

en. While programming is in progress only the

Read Status Register and Program Suspend in-

structions are valid.

program or erase operation. The suspended pro-

gram or erase operation may be restarted by using

the Program/Erase Resume instruction. Program/

Erase Suspend is not allowed during the Overlay

block program/erase operation and the command

is ignored.

The Program/Erase Suspend instruction consists

of one write cycle giving the command B0h at the

address 00000h.

If a program operation is in progress when the in-

struction is given, the Status Register bits 4 and 6

are set to ’1’ after it has been suspended. If an

erase operation is in progress when theinstruction

is given, the Status Register bits 5 and 6 are set to

’1’ after it has been suspended.

Read operations output the Status Register after

the program operation has started. The Status

Register bit 7 is ’0’ while programming is in

progress and is set to ’1’ when it is completed. Af-

ter completion the Status Register bit 4 is set to ’1’

if there has been a programming failure.

The valid instructions that may be given to the

memory while programing is suspended are

– Read Memory Array (RD)

Programming should not be attempted when the

V

Program/Erase Supply Voltage is out of the

PP

– Read Status Register (RSR)

– Read Electronic Signature (RSIG)

– Program/Erase Resume (PER)

range V

or V

as the results will be uncer-

PP1

PPH

tain. The Status Register bit 3 is set to ’1’ if V is

PP

not within the allowed ranges when programming

is attempted or if it falls out of the ranges during

program execution.

In addition, while erasure is suspended, the Pro-

gram (PG) instruction may be given.

In Program/Erase Suspend mode the memory can

be placed in a pseudo-standby mode by taking

Chip Enable /E to VIH to reduce power consump-

tion.

Program/Erase Resume (PER). If a Program/

Erase Suspend instruction has previously been

executed, then the operation may be resumed by

giving the command D0h at the address 00000h.

The Status Register bits 4, 5 and 6 are cleared

when program or erase resumes. A Read Memory

Array instruction will output the Status Register af-

ter program or erase is resumed.

The program operation aborts if V drops out of

PP

the allowed ranges or if Reset/Power-Down RP

falls to V . As data integrity cannot be guaranteed

IL

when the program operation is aborted, the mem-

ory block must be erased and programming re-

peated.

A Clear Status Register instruction must be given

to clear the Status Register bits.

Overlay Block Program (OBPG). The Overlay

Block Program instruction consists of two write cy-

cles, the first is the program set-up command 04h

at the address 00000h. This is followed by a sec-

ond write cycle to latch the address and data to be

programmed. This second command starts the P/

E.C.

The operation is executed as described for the

Program (PG) instruction of the Main memory ar-

ray.

Suggested flow charts for software that uses pro-

gramming, erasure and program/erase suspend/

resume operations are shown in Figures 11, 12,

13 and 14.

Asynchronous/Synchronous Read Toggle (ART).

Asynchronous Read Memory Array is the memory

default at power-up or when returning from Power-

Down. To read data in Synchronous mode, either

single or burst, the Asynchronous/Synchronous

Read Toggle instruction must be used.

The Asynchronous/Synchronous Read Toggle in-

struction consists of one write cycle giving the

command 60h at the address 00000h. Two con-

secutive instructions are not recognised and an-

other Instruction, for example the Read Memory

Array, must be given before another Asynchro-

nous/Synchronous Read Toggle will be recogn-

ised.

While programming of the Overlay block in

progress only the ReadStatus Register instruction

is valid.

Program/Erase Suspend (PES). As

memory

erasure takes of the order of seconds to complete

and programming a few microseconds, a Pro-

gram/Erase Suspend instruction is implemented.

Program/Erase Suspend interrupts the operations

to allow reading or programming in a block other

than one in which program or erase is suspended.

A Program/Erase Suspend instruction is accepted

only during a Program or Erase instruction. When

the Program/Erase Suspend command is written

to the Command Interface, the P/E.C. freezes the

12/36

M58BF008

Wrap/No-wrap Burst Toggle (WBT). The

de-

Overlay Block Read Enable/Disable Toggle

(OBT). Read operations in the Overlay block can

be enabled or disabled using the Overlay Block

Read Enable/Disable Toggle instruction. This tog-

gle instruction consists of one write cycle giving

the command 06h at the address 00000h. Two

consecutive instructions are not recognised.

fault for burst read is set by the device configura-

tion. The Wrap/No-wrap Burst Toggle can be used

to toggle the burst wrap operation.

The Wrap/No-wrap Burst Toggle instruction con-

sists of one write cycle giving the command 30h at

the address 00000h. Two consecutive instructions

are not recognised and another Instruction, for ex-

ample the Read Memory Array, must be given be-

fore another Wrap/No-wrap Burst Toggle will be

recognised.

The Status Register bit 1 is set to ’1’ when the

Overlay block is enabled.

Table 9. Read Access to Overlay Block or Main Block

V

OBEB Status Bit

OBS Status Bit

Read Access

PP

In the range V

or V

PPH

1

Overlay Block

PP1

Out of the range

1

0

Main Block

V

or V

PP1

PPH

0

1

X

0

Main Block

Unknown

Not guaranteed

Table 10. Overlay Block Enable/Disable Bit (OBEB)

Method

OBEB Status Bit

Prior state of

Next state of

OBEB

V

PP

OBEB

In the range

X

1

0

1

0

V

or V

PP1

PPH

(1)

Toggle RP

Out of the range

or V

X

V

PP1

PPH

In the range

or V

V

PP1

PPH

Power-on-reset

Out of the range

V

or V

PP1

PPH

–

0

1

0

Overlay Block Read Enable/Disable instruction OBT

–

Note: 1. Toggle H-L-H for t

minimum.

PLPH

13/36

M58BF008

CONFIGURATION

Wrap/No-Wrap. The burst function can be set to

default to wrap or no-wrap. The behaviour is

shown in Table 13. Wrap/No-wrap can be toggled

using the Wrap/No-wrap Burst Toggle Instruction.

The M58BF008 is configured during testing which

sets the default for the write and burst interface.

The settings are:

Critical Word and Burst Word Latency Times.

The Critical Word and Burst Word latency times

can be set permanently to

– Critical Word Latency Time X = 3 or 4

– Burst Word Latency Time Y = 1 or 2

A burst sequence is described as X-Y-Y-Y.

Write Interface. The write interface can be set

permanently to either Asynchronous or Synchro-

nous. Note that the read interface is not affected

by this configuration and defaults to Asynchronous

read at power-up, it can be toggled to Synchro-

nous read and back using the Asynchronous/Syn-

chronous Read Toggle Instruction.

Table 11. Configuration

Name

Option 1

Synchronous

Option 2

Asynchronous

No-wrap

Write Interface

Wrap/No-wrap Burst

Wrap

4

1

3

2

Critical Word Latency Time (X)

Burst Word Latency Time (Y)

Table 12. Wrap/No-wrap Burst Sequence

First Burst Address A1-A0

Data Wrap

Data No-wrap

00

01

10

11

Double-Word 0

1

2

3

0

2

3

0

1

3

0

1

2

Double-Word 0

Double-Word 1

Double-Word 2

Double-Word 3

1

2

3

2

3

Double-Word 1

Double-Word 2

Double-Word 3

POWER SUPPLY

Power Up. The V Supply Voltage, V

Input/

Program/

DD

DDQ

Output Supply Voltage and the V

PP

The M58BF008 places itself in one of three differ-

ent modes depending on the status of the control

signals which define decreasing levels of current

consumption. This minimises the memory power

consumption, allowing an overall decrease in the

system power consumption without affecting per-

formance. A different recovery time is, however,

linked to the different modes - see the AC timing

tables.

Erase Supply Voltage can be applied in any order.

The memory Command Interface is reset on pow-

er-up to Read Memory Array, but a negative tran-

sition on Chip Enable E or a change of the

addresses is required to ensure valid data is out-

put.

Care must be taken to avoid writes to the memory

when the V Supply Voltage is above V

and

DD

LKO

V

Program/Erase Supply Voltage powers-up

PP

Active Power mode. When Chip Enable E is at

first. Writes can be inhibited by driving either Write

Enable W or Write/Read WR to V .

V and Reset/Power-Down RP is at V the mem-

IL

IH

ory is in Active Power mode. The DC characteris-

tics tables show the current consumption figures.

Standby mode. Refer to the Device Operating

section

The memory is disabled until Reset/Power-Down

RP is up to V .

IH

SUPPLY RAILS

Power-Down mode. Refer to the Device Operat-

ing section.

Normal precautions must be taken for supply rail

decoupling. Each device in a system should have

the V , V

and V

rails decoupled with a

DD

DDQ

PP

0.1µF capacitor close to the package pins. PCB

track widths should be sufficient to carry the re-

quired program and erase currents on the V

supply.

PP

14/36

M58BF008

Table 13. AC Measurement Conditions

Figure 5. AC Testing Load Circuit

Input Rise and Fall Times

≤ 10ns

0 to V

V

/2

DDQ

Input Pulse Voltages

DDQ

Input and Output Timing Ref. Voltages

V

/2

DDQ

1N914

3.3kΩ

Figure 4. AC Testing Input Output Waveform

DEVICE

UNDER

TEST

OUT

V

DDQ

C

= 80pF

L

V

/2

DDQ

0V

C

includes JIG capacitance

L

AI00610

AI02657

(1)

Table 14. Capacitance (T = 25 °C, f = 1MHz)

A

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

= 0V

Min

Max

6

Unit

pF

C

IN

V

IN

C

OUT

V

OUT

= 0V

12

pF

Note: 1. Sampled only, not 100% tested.

15/36

M58BF008

Table 15. DC Characteristics

(T = –40 to 125°C; V = 5V ± 10% and V

= 3.3V ± 0.3V)

A

DD

DDQ

Symbol

Parameter

Test Condition

0V≤ V ≤ V

Min

Max

±1

Unit

µA

I

Input Leakage Current

LI

IN

DDQ

I

0V≤ V

≤V

Output Leakage Current

±10

–600

200

25

µA

LO

OUT

DDQ

I

0V≤ V ≤ V

IN

Input Leakage Current pull-up

Input Leakage Current pull-down

Supply Current (Async. Read)

Supply Current (Burst Read)

Supply Current (Standby)

Supply Current (Power-down)

–20

µA

LT1

I

0≤ V ≤ 12.6

PP

µA

LIVPP

I

E = V , G = V , f = 5MHz

mA

µA

CC

IL

I

E = V , G = V , f = 40MHz

IL IL

25

CCB

I

E = V , RP = V

10

CC1

IH

I

RP = V

10

µA

CC2

IL

V

= V

≥ V

≤ V

25

mA

µA

PP

PP1

PPH

PP1

PPH

PP1

Supply Current (Program)

Program in Progress

I

CC3

25

PP

V

25

PP

Supply Current (Erase)

Erase in Progress

I

CC4

V

25

PP

I

V

Program Current (Read or Standby)

Program Current (Power-down)

200

±15

5

PP

I

µA

PP1

PP2

I

RP = V

IL

µA

Program Current (Program)

Program in Progress

V

= V

15

mA

PP

PP1

I

PP3

PP4

25

15

25

mA

V

PP

PPH

V

PP

PP1

PPH

Program Current (Erase)

Erase in Progress

I

V

0.1V

DDQ

Input Low Voltage

Input High Voltage

–0.3

IL

V

DDQ

+0.3

0.9V

V

IH

DDQ

I

OL

= 100µA,

= V min,

DD

V

Output Low Voltage

Output High Voltage

0.2

OL

DD

= V

min

DDQ

I

V

= –100µA,

OL

DD

= V min,

V

–0.2

DDQ

V

OH

DD

V

= V

min

DDQ

Program Voltage

(Program or Erase operations)

V

4.5

5.5

V

PP1

Program Voltage

(Program or Erase operations)

11.4

12.6

PPH

V

Supply Voltage Lock-out

DD

1.5

V

LKO

V

Program Voltage Lock-out

PPLK

16/36

M58BF008

(1)

Table 16. Asynchronous Read AC Characteristics

(T = –40 to 125°C; V = 5V ± 10% and V = 3.3V ± 0.3V)

A

DD

Alt

DDQ

Symbol

Parameter

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

Max

Unit

ns

t

RC

100

AVAV

t

ACC

100

ns

AVQV

(2)

t

Address Transition to Output Transition

Chip Enable High to Output Transition

Chip Enable Low to Output Valid

0

ns

t

OH

AXQX

(2)

t

OH

EHQX

(2, 3)

t

100

25

t

CE

ELQV

(2)

t

Chip Enable Low to Output Transition

Chip Enable High to Output Hi-Z

0

t

LZ

ELQX

(2)

t

HZ

EXQZ

t

Output Enable High to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

t

OH

GHQX

t

25

30

t

DF

GHQZ

t

OE

GLQV

t

0

t

OLZ

GLQX

Note: 1. See AC Testing Measurements Conditions for timing measurements.

2. Sampled only, not 100% tested.

3. G may be delayed up to t

-t

after falling edge of E without increasing t

.

ELQV

ELQV GLQV

Figure 6. Asynchronous Read AC Waveforms

tAVAV

VALID

A12-A29

tAVQV

E, LBA

tELQV

tELQX

tEHQX

tEHQZ

G

tGLQX

tGLQV

tGHQX

tGHQZ

VALID

DQ0-DQ31

tPHQV

RP

AI03571

17/36

M58BF008

(1)

Table 17. Synchronous Read AC Characteristics

(T = –40 to 125°C; V = 5V ± 10% and V

= 3.3V ± 0.3V)

A

DD

DDQ

Symbol

Parameter

Min

Max

Unit

DC

System Clock Duty Cycle

45

55

%

CLK

(2)

Address Valid to System Clock High

10

ns

t

AVCH

t

Burst Address Advance Low to System Clock High

Load Burst Address Low to System Clock High

BALCH

(2)

t

BLCH

CHAX

(2)

System Clock High to Address Transition

System Clock High to Load Burst Address High

System Clock Fall Time

5

ns

t

CHBH

t

3

CHCL

(2)

System Clock High to Output Disable High

System Clock High to Output Enable High

System Clock High to Data Valid

5

t

CHGDH

(2)

t

CHGH

(2)

20

t

CHQV

System Clock High to Data Transition

System Clock High to Data Hi-Z

0

5

t

CHQX1

CHQX2

t

20

t

CHQZ

t

System Clock Rise Time

3

ns

CLCH

t

System Clock Period

25

CLCL

t

Chip Enable Low to System Clock High

20

10

ELCH

(2)

Output Disable Low to System Clock High

Output Enable Low to System Clock High

ns

t

GDLCH

(2)

t

GLCH

t

Reset/Power-down High to Load Burst Address Low

Write/Read High to System Clock High

20

10

ns

PHBL

t

WRHCH

Note: 1. See AC Testing Measurement Conditions for timing measurements.

2. Sampled only, not 100% tested.

18/36

M58BF008

Figure 7. Synchronous Single Read AC Waveforms

CLK

tAVCH

tCHAX

A0-A17

LBA

VALID

tBLCH

tCHBH

G

E

tGLCH

tCHGH

tELCH

tCHQV

tCHQX1

tCHQZ

tCHQX2

DQ0-DQ31

RP

VALID

tPHBL

tWRHCH

WR

AI02658

19/36

M58BF008

Figure 8. Synchronous Burst Read AC Waveforms

CLK

tAVCH

tCHAX

A0-A17

LBA

VALID

tBLCH

tCHBH

G

E

tGLCH

tELCH

tCHQV

tCHQX1

tCHQV

tCHQX2

DQ0-DQ31

RP

VALID

tPHBL

tWRHCH

WR

tBALCH

BAA

AI03583

20/36

M58BF008

(1)

Table 18. Asynchronous Write AC Characteristics

(T = –40 to 125°C; V = 5V ± 10% and V

= 3.3V ± 0.3V)

A

DD

DDQ

Symbol

Alt

Parameter

Min

70

0

Max

Unit

ns

t

WC

Write Cycle Time

AVAV

t

AS

Address Valid to Write Enable High

Data Valid to Write Enable High

ns

AVWH

t

DS

ns

DVWH

t

CS

Chip Enable Low to Write Enable Low

Reset/Power-down High to Write Enable Low

ns

ELWL

t

70

ns

PHWL

PS

(2)

Output Valid to V out of the range V

or V

PPH

0

ns

t

PP

PP1

QVVPL

t

V

High to Write Enable High

PP

200

0

ns

µs

t

VPS

VPHWH

t

Write Enable High to Address Transition

Write Enable High to Data Transition

Write Enable High to Chip Enable High

Write Enable High to Output Valid, Program

WHAX

AH

t

0

WHDX

DH

t

0

WHEH

CH

(3)

10

t

WHQV1

(3)

Write Enable High to Output Valid, Erase

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

2.1

30

70

sec

ns

t

WHQV2

t

WPH

WHWL

t

ns

WLWH

WP

Note: 1. See AC Testing Measurement conditions for timing measurements.

2. Sampled only, not 100% tested.

3. Time is measured to Status Register Read giving bit b7 = ’1’.

21/36

M58BF008

Figure 9. Asynchronous Write AC Waveforms

tAVAV

VALID

A0-A17

00000h

tWHAX

tAVWH

G

E

tELWL

tWLWH

tWHEH

tWHWL

W

tWHQV1,2

tDVWH

tWHDX

COMMAND

or DATA

STATUS

REGISTER

DQ0-DQ31

COMMAND

tVPHWH

tQVVPL

V

PP

tPHWL

RP

WR

WRITE

READ

AI02660

22/36

M58BF008

(1)

Table 19. Synchronous Write AC Characteristics

(T = –40 to 125°C; V = 5V ± 10% and V

= 3.3V ± 0.3V)

A

DD

DDQ

Symbol

Parameter

Min

Max

Unit

DC

System Clock Duty Cycle

45

55

%

CLK

(2)

Address Valid to System Clock High

10

5

ns

t

AVCH

BLCH

CHAX

(2)

Load Burst Address Low to System Clock High

System Clock High to Address Transition

t

System Clock High to Load Burst Address High

System Clock Fall Time

5

ns

t

CHBH

t

3

CHCL

(3)

System Clock High to Output Valid, Program

System Clock High to Output Valid, Erase

System Clock High to Data Transition

10

2.1

5

µs

t

CHQV1

CHQV2

(3)

(2)

sec

ns

t

CHQX

System Clock High to Write/Read High

5

ns

t

CHWH

System Clock High to Write Enable High

System Clock Rise Time

5

ns

t

CHWRH

t

3

CLCH

t

System Clock Period

25

CLCL

t

Chip Enable Low to System Clock High

Reset/Power-down High to System Clock High

Data Valid to System Clock High

20

ELCH

t

200

PHCH

(2)

10

0

t

QVCH

(2)

Output Valid to V out of range V

or V

PPH

ns

t

PP

PP1

QVVPL

VPHCH

V

High to System Clock High

200

10

t

PP

Write Enable Low to System Clock High

Write/Read Low to System Clock High

t

WLCH

t

WRLCH

Note: 1. See AC Testing Measurement conditions for timing measurements.

2. Sampled only, not 100% tested.

3. Time is measured to Status Register Read giving bit b7 = ’1’.

23/36

M58BF008

Figure 10. Synchronous Write AC Waveforms

CLK

tAVCH

tCHAX

A17-A0

LBA

00000h

VALID

tBLCH

tCHBH

WR

W

tWRLCH

tCHWRH

tWLCH

tQVCH

tCHWH

tCHQX

tWHQV1,2

COMMAND

or DATA

STATUS

REGISTER

DQ31-DQ0

RP

COMMAND

tPHCB

tVPHCH

V

PP

tELCH

E

WRITE

READ

AI02659

24/36

M58BF008

Table 20. Reset/Power-down AC Characteristics

(T = –40 to 125°C; V = 5V ± 10% and V

= 3.3V ± 0.3V)

A

DD

DDQ

Mode

Symbol

Parameter

Min

Max

Unit

ns

t

Reset/Power-down High to Chip Enable Low

Reset/Power-down High to Output Valid

Reset/Power-down High to Write Enable Low

70

PHEL

t

100

ns

PHQV

t

70

ns

Async

PHWL

(1)

Reset/Power-down Pulse Width

100

ns

µs

ns

µs

t

PLPH

t

Reset/Power-down Low to Program Erase Abort

Reset/Power-down High to Load Burst Address Low

22

PLRH

t

20

PHBL1

PHBL2

Sync

Note: 1. The device Reset is possible but not guaranteed if t

< 100ns.

PLPH

A Reset will complete within 100ns if RP is Low while not in Program or Erase.

Figure 11. Reset/Power-down AC Waveforms

Reset during Read Mode

tPLPH

RP

tPHQV

tPHBL1

Reset during Program with t_PLPH≤ t_PLRH

Abort

Complete

tPHWL

tPHEL

tPLRH

tPLPH

tPHBL1

RP

Reset during Program/Erase with t_PLPH> t_PLRH

Abort

Complete Down

tPLRH

Power

tPHWL

tPHEL

tPHBL2

tPLPH

RP

AI00624

25/36

M58BF008

Table 21. Program, Erase Times and Program/Erase Endurance Cycles

(T = –40 to 125°C; V = 5V ± 10% and V

= 3.3V ± 0.3V)

A

DD

DDQ

Test Conditions

= V

Parameter

Min

Max

Unit

Typ

0.14

0.18

0.21

0.33

V

1.4

1.8

2.1

3.3

sec

PP

PPH

Main/Overlay Block Program Time

Main/Overlay Block Erase Time

Program/Erase Cycles (per Block)

V

= V

PP

PP1

sec

PP

PPH

V

= V

sec

PP

PP1

V

= V

1,000

cycles

PPH

V

10,000

PP

PP1

Figure 12. Program Flowchart and Pseudo Code

Start

Write 40h/04h

Command

PG/OBPG instructions:

– write 40h/04h command

– write Address & Data

(memory enters read status

state after the PG instruction)

Write Address

& Data

Read Status

Register

do:

– read status register

(E or G must be toggled)

NO

b7 = 1

while b7 = 1

YES

NO

V

Invalid

Error (1)

If b3 = 1, V

invalid error:

– error handler

PP

b3 = 0

YES

Program

Error (1)

If b4 = 1, Program error:

– error handler

b4 = 0

YES

End

AI02663

Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

26/36

M58BF008

Figure 13. Program Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Command

Write 70h

Command

PES instruction (note 1):

– write B0h command

(memory enters read register

state after the PES instruction)

do:

Read Status

Register

– read status register

(E or G must be toggled)

NO

b7 = 1

YES

while b7 = 1

b6 = 1

YES

If b4 = 0, Program completed

(at this point the memory will

accept only the RD or PER instruction)

b4 = 1

YES

Program Complete

Write FFh

Command

RD instruction:

– write FFh command

– one or more data reads

from another block

Read data from

another block

Write D0h

Command

Write FFh

Command

PER instruction:

– write D0h command

to resume erasure

– if the program operation completed

then this is not necessary. The device

returns to Read Array as normal

(as if the Program/Erase suspend

was not issued).

Read Data

Program Continues

AI02664

Note: 1. PES instruction is not allowed during OBPG operation.

27/36

M58BF008

Figure 14. Erase Flowchart and Pseudo Code

Start

Write 20h/02h

Command

EE/OBEE instructions:

– write 20h/02h command

– write Block Address

(A12-A17) & command D0h/0Dh

(memory enters read status

state after the EE instruction)

Write Block Address

& D0h Command

do:

Read Status

Register

– read status register

(E or G must be toggled)

NO

b7 = 1

while b7 = 1

YES

NO

V

Invalid

If b3 = 1, V

invalid error:

PP

Error (1)

PP

– error handler

b3 = 0

YES

Command

Sequence Error

If b4, b5 = 1, Command Sequence error:

– error handler

b4, b5 = 0

YES

Erase

Error (1)

If b5 = 1, Erase error:

– error handler

b5 = 0

YES

End

AI02680

Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

28/36

M58BF008

Figure 15. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Command

Write 70h

Command

PES instruction (note 1):

– write B0h command

(memory enters read register

state after the PES instruction)

do:

Read Status

Register

– read status register

(E or G must be toggled)

NO

b7 = 1

YES

while b7 = 1

b6 = 1

YES

If b6 = 0, Erase completed

(at this point the memory wich

accept only the RD or PER instruction)

b5 = 1

YES

Erase Complete

Write FFh

Command

RD instruction:

– write FFh command

– one o more data reads

from another block

Read data from

another block

or Program

PG instruction:

– write 40h command

– write Address & Data

PER instruction:

– write D0h command

to resume erasure

Write D0h

Command

Write FFh

Command

– if the program operation completed

then this is not necessary. The device

returns to Read Array as normal

(as if the Program/Erase suspend

was not issued).

Read Data

Program Continues

AI02681

Note: 1. PES instruction is not allowed during OBEE operation.

29/36

M58BF008

Figure 16. Command Interface and Program Erase Controller Flowchart (a)

WAIT FOR

COMMAND

WRITE (1)

NO

90h

READ

ARRAY

YES

READ

SIGNATURE

NO

06h

YES

OBEB

TOGGLE

NO

70h

YES

READ

STATUS

NO

30h

YES

NO

WRAPPING

TOGGLE

50h

YES

CLEAR

STATUS

NO

04h

YES

PROGRAM

OB SET-UP

NO

02h

YES

ERASE

A

NO

OB SET-UP

YES

PROGRAM

OB

READY

NO

0Dh

READ

STATUS

ERASE

COMMAND

ERROR

NO

YES

ERASE

OB

READY

D

B

AI02682

Note: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or

if V falls below V , the Command Interface defaults to Read Array mode.

DD

LKO

2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

30/36

M58BF008

Figure 17. Command Interface and Program Erase Controller Flowchart (b)

A

C

B

NO

40h

YES

PROGRAM

SET UP

PROGRAM

(READ STATUS)

YES

READY

(2)

NO

B0h

YES

READ

STATUS

PROGRAM

SUSPEND

YES

READY

(2)

NO

PROGRAM

SUSPENDED

READ

STATUS

YES

READ

STATUS

70h

NO

YES

NO

READ

SIGNATURE

90h

NO

YES

READ

ARRAY

READ

STATUS

D0h

(PROGRAM RESUME)

AI02684

Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

31/36

M58BF008

Figure 18. Command Interface and Program Erase Controller Flowchart (c)

C

D

B

20h

NO

FFh

YES

ERASE

SET-UP

NO

D0h

ERASE

COMMAND

ERROR

YES

ERASE

(READ STATUS)

YES

READY

(2)

NO

B0h

YES

READ

STATUS

ERASE

SUSPEND

ERASE

SUSPENDED

NO

YES

READY

(2)

YES

NO

YES

READ

STATUS

READ

70h

NO

STATUS

READ

SIGNATURE

90h

NO

PROGRAM

SET-UP

40h or

10h

c

NO

YES

READ

ARRAY

READ

STATUS

D0h

(ERASE RESUME)

AI02683

Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

32/36

M58BF008

Table 22. Ordering Information Scheme

Example:

M58BF008B

100 ZA

6

T

Device Type

M58

Architecture

B = Burst Mode

Operating Voltage

F = V = 5V ± 10%; V

= 3.0V or 3.6V

DDQ

DD

Device Function

008 = 8 Mbit (256Kb x 32), Burst

Configuration

B = Synchronous Write, Burst Wrap,

Critical Word Latency = 4

Burst Word Latency = 1

Speed

100 = 100ns

Package

D = PQFP80

ZA = LBGA80: 1.0 mm pitch

Temperature Range

3 = –40 to 125 °C

Option

T = Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Configuration, Package, etc...) or for further information on any aspect of

this device, please contact the STMicroelectronics Sales Office nearest to you.

33/36

M58BF008

Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data

mm

Min

inches

Symbol

Typ

Max

Typ

Min

Max

A

A1

A2

b

3.40

0.1339

0.25

2.55

0.30

0.11

–

0.0098

2.80

3.05

0.45

0.23

–

0.1102

0.1004

0.1201

0.0118

0.0177

c

0.0043

0.0091

D

23.90

20.00

0.80

0.9409

0.7874

0.0315

0.7047

0.5512

0.0346

3.5 °

–

D1

e

–

E

17.90

14.00

0.88

–

E1

L

–

0.73

0 °

80

1.03

7 °

0.0287

0 °

80

24

16

0.0406

7 °

α

3.5 °

N

Nd

Ne

CP

24

16

0.250

0.0098

Figure 19. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline

D

D1

D2

A2

e

Ne

E2 E1 E

b

N

1

Nd

A

CP

c

A1

α

L

TQFP

Drawing is not to scale.

34/36

M58BF008

Table 24. LBGA80 - 10 x 8 balls, 1mm pitch, Package Mechanical Data

mm

inch

Min

Symbol

Typ

Min

Max

1.700

0.450

Typ

Max

A

A1

A2

b

0.0669

0.0177

0.400

1.100

0.500

12.000

9.000

0.350

0.0157

0.0433

0.0197

0.4724

0.3543

0.0138

–

D

–

D1

ddd

e

–

0.150

0.0059

1.000

10.000

7.000

1.500

0.500

–

0.0394

0.3937

0.2756

0.0591

0.0197

–

E

E1

FD

FE

SD

SE

Figure 20. LBGA80 - 10 x 8 balls, 1mm pitch, Bottom View Package Outline

E

E1

FE

FD

SE

SD

D

D1

ddd

e

b

A

A2

A1

BGA-Z05

Drawing is not to scale.

35/36

M58BF008

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

36/36


型号：	M58BF008ZA
厂家：	ST
描述：	8 Mbit 256Kb x32, Burst Flash Memory 8兆位256Kb的32倍，突发闪存闪存
文件：	总36页 (文件大小：232K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58BF008ZA [STMICROELECTRONICS]

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