M69AW048BL70ZB8F [STMICROELECTRONICS]
2MX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48;
| 型号： | M69AW048BL70ZB8F |
| 厂家： | 
ST |
| 描述： | 2MX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48 存储 静态存储器 |
| 文件： | 总29页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M69AW048B
32 Mbit (2M x16) 3V Asynchronous PSRAM
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
SUPPLY VOLTAGE: 2.7 to 3.3V
ACCESS TIMES: 70ns
Figure 1. Package
LOW STANDBY CURRENT: 100µA
DEEP POWER-DOWN CURRENT: 10µA
BYTE CONTROL: UB/LB
PROGRAMMABLE PARTIAL ARRAY
COMPATIBLE WITH STANDARD LPSRAM
TRI-STATE COMMON I/O
8 WORD PAGE ACCESS CAPABILITY: 18ns
WIDE OPERATING TEMPERATURE
– TA = –30 to +85°C
FBGA
TFBGA48 (ZB)
6x8 mm
■
POWER-DOWN MODES
– Deep Power-Down
– 4 Mbit Partial Array Refresh
– 8 Mbit Partial Array Refresh
– 16 Mbit Partial Array Refresh
November 2004
1/29
M69AW048B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Enable (E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Upper Byte Enable (UB).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description of Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-Down Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Power-Down Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Power-Down Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Power-Down Configuration Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/29
M69AW048B
Table 9. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. Read Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. UB/LB Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10.Page Address and Chip Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . 16
Figure 11.Random and Page Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . 17
Table 12. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14.Write Enable and UB/LB Controlled, Write AC Waveforms 1 . . . . . . . . . . . . . . . . . . . . . 20
Figure 15.Write Enable and UB/LB Controlled, Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . . 20
Figure 16.Write Enable and LB/UB Controlled, Write AC Waveforms 3 . . . . . . . . . . . . . . . . . . . . . 21
Figure 17.Write Enable and LB/UB Controlled, Write AC Waveforms 4 . . . . . . . . . . . . . . . . . . . . . 21
Figure 18.Chip Enable Controlled, Read Followed by Write Mode AC Waveforms . . . . . . . . . . . . 22
Figure 19.E1, W, G Controlled, Read and Write Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . 22
Figure 20.Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms . . . 23
Figure 21.Output Enable, Write Enable and UB/LB Controlled, Read and Write Mode AC Waveforms
23
Table 13. Standby/Power-Down Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 22.Power Down Program AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 23.Power-Down Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 24.Power-Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 25.Standby Mode Entry AC Waveforms, After Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 26.TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View . . . . 26
Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M69AW048B
SUMMARY DESCRIPTION
The M69AW048B is a 32 Mbit (33,554,432 bit)
CMOS memory, organized as 2,097,152 words by
16 bits, and is supplied by a single 2.7V to 3.3V
supply voltage range.
M69AW048B is a member of STMicroelectronics
PSRAM memory family. These devices are manu-
factured using dynamic random access memory
cells, to minimize the cell size, and maximize the
amount of memory that can be implemented in a
given area.
However, through the use of internal control logic,
the device is fully static in its operation, requiring
no external clocks or timing strobes, and has a
standard Asynchronous SRAM Interface.
The internal control logic of the M69AW048B han-
dles the periodic refresh cycle, automatically, and
without user involvement.
Write cycles can be performed on a single byte by
using Upper Byte Enable (UB) and Lower Byte En-
able (LB).
The device can be put into standby mode using
Chip Enable (E1) or in Power-Down mode by us-
ing Chip Enable (E2).
The device features various kinds of Power-Down
modes for power saving as a user configurable op-
tion:
■
The Partial Array Refresh (PAR) performs a
limited refresh of the part of the PSRAM array
(4 Mbits, 8 Mbits, 16Mbits) that contains
essential data.
■
Deep Power-Down mode: this mode achieves
a very low current consumption by halting all
the internal activities. Since the refresh
circuitry is halted, the duration of the power-
down should be less than the maximum period
for refresh.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A20
Address Input
DQ0-DQ15
Data Input/Output
Chip Enable, Power Down
Output Enable
V
CC
E1, E2
G
21
16
A0-A20
DQ0-DQ15
W
Write Enable
W
E1
E2
G
UB
LB
Upper Byte Enable
Lower Byte Enable
Supply Voltage
Ground
M69AW048B
V
CC
V
SS
UB
LB
Not Connected
(no internal connection)
NC
V
SS
AI05844c
4/29
M69AW048B
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A2
E1
E2
A
B
C
D
E
F
LB
G
A0
A3
A1
A4
A6
DQ8
DQ9
DQ0
DQ2
UB
A5
DQ10
DQ11
DQ12
DQ13
A19
DQ1
DQ3
DQ4
DQ5
W
A7
V
A17
NC
A14
A12
A9
V
SS
CC
V
A16
A15
A13
A10
V
CC
SS
DQ14
DQ15
A18
DQ6
DQ7
A20
G
H
A8
A11
AI07242
5/29
M69AW048B
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Read and Write operations.
these, Deep Power-Down mode, is the lowest
power mode.
Output Enable (G). The Output Enable, G, pro-
vides a high speed tri-state control, allowing fast
read/write cycles to be achieved with the common
I/O data bus.
Data Inputs/Outputs (DQ8-DQ15). The Upper
Byte Data Inputs/Outputs carry the data to or from
the upper part of the selected address during a
Write or Read operation, when Upper Byte Enable
(UB) is driven Low.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Upper Byte Enable (UB). The Upper Byte En-
able, UB, gates the data on the Upper Byte Data
Inputs/Outputs (DQ8-DQ15) to or from the upper
part of the selected address during a Write or
Read operation.
Lower Byte Enable (LB). The Lower Byte En-
able, LB, gates the data on the Lower Byte Data
Inputs/Outputs (DQ0-DQ7) to or from the lower
part of the selected address during a Write or
Read operation.
Data Inputs/Outputs (DQ0-DQ7). The
Lower
Byte Data Inputs/Outputs carry the data to or from
the lower part of the selected address during a
Write or Read operation, when Lower Byte Enable
(LB) is driven Low.
Chip Enable (E1). When asserted (Low), the
Chip Enable, E1, activates the memory state ma-
chine, address buffers and decoders, allowing
Read and Write operations to be performed. When
de-asserted (High), all other pins are ignored, and
the device is put, automatically, in low-power
Standby mode.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Write,
etc.) and for driving the refresh logic, even when
the device is not being accessed.
Chip Enable (E2). The Chip Enable, E2, puts the
device in Power-down mode (Deep Power-Down,
PAR and Standby) when it is driven Low. One of
V
SS Ground. The VSS Ground is the reference for
all voltage measurements.
6/29
M69AW048B
Figure 4. Block Diagram
ARBITRATION
LOGIC
INTERNAL
CLOCK
REFRESH
GENERATOR
CONTROLLER
DYNAMIC
MEMORY
ARRAY
ADDRESS
DQ0-DQ7
INPUT/OUTPUT
BUFFER
E1
E2
G
DQ8-DQ15
COLUMN
DECODER
CONTROL
LOGIC
W
LB
UB
ADDRESS
V
POWER
CONTROLLER
CC
V
SS
AI07221b
7/29
M69AW048B
OPERATION
Operational modes are determined by device con-
trol inputs W, E1, E2, LB and UB as summarized
in the Operating Modes table (see Table
2., Operating Modes).
See Figures 12, 13, 14, 15, 16 and 17 and Table
12., Write Mode AC Characteristics, for details of
when the outputs become valid.
Standby Mode
The device is in Standby mode when:
Power-Up Sequence
–
–
Chip Enable (E1) is High and
Chip Enable (E2) is High
Because the internal control logic of the
M69AW048B needs to be initialized, the following
Power-Up procedure must be followed before the
memory is used:
The input/output buffers and the decoding/control
logic are switched off, but the dynamic array con-
tinues to be refreshed. In this mode, the memory
current consumption, ISB, is reduced, and the data
remains valid.
See Figures 17 and Table 13., Standby/Power-
Down Mode AC Characteristics, for details of
when the outputs become valid.
–
–
Apply power and wait for VCC to stabilize,
Wait 300µs while driving both Chip Enable
signals (E1 and E2) High.
See also Figure 24. for details on the Power-Up
AC waveforms.
Read Mode
Power-down Modes
The device is in Read mode when:
Description of Power-Down Modes. The
M69AW048B has four Power-down modes, Deep
Power-Down, 4 Mbit Partial Array Refresh, 8 Mbit
Partial Array Refresh, and 16 Mbit Partial Array
Refresh (see Table 4. and Figure 22.).
These can be entered using a series of read and
write operations. Each mode has following fea-
tures. The default state is Deep Power-Down and
it is the lowest power consumption but all data will
be lost once E2 is brought Low for Power-down.
No sequence is required to put the device in Deep
Power-Down mode after Power-up.
–
–
–
Write Enable (W) is High and
Output Enable (G) Low and
the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
The time taken to enter Read mode (tELQV, tGLQV
or tBLQV) depends on which of the above signals
was the last to reach the appropriate level.
Data out (DQ15-DQ0) may be indeterminate dur-
ing tELQX, tGLQX and tBLQX but data will always be
valid during tAVQV. See Figures 7, 8, 9, 10 and 11
and Table 11., Read Mode AC Characteristics, for
details of when the outputs become valid.
The device is in one of the Power-down modes
when:
Write Mode
–
Chip Enable (E2) is Low
The device is in Write mode when
All the device logic is switched off and all internal
operations are suspended. This gives the lowest
power consumption. In this operating mode, no re-
fresh is performed, and data is lost if the duration
is longer than 10ns. This mode is useful for those
applications where the data contents are no longer
needed, and can be lost, but where reduced cur-
rent consumption is of major importance.
Power-Down Program Sequence. The Power-
Down Program sequence is used to program the
Power-Down Configuration. It requires a total of
six read and write operations, with specific ad-
dresses and data. Between each read or write op-
eration the device must be in Standby mode.
Table 4. shows the sequence. In the first cycle, the
Byte at the highest memory address (MSB) is read.
In the second and third cycles, the data (RDa) read
by first cycle are written back. If the third cycle is
written into a different address, the sequence is
aborted, and the data written by the third cycle is
valid as in a normal write operation. In the fourth
and fifth cycles, the Power-Down Configuration
data is written. The data of the fourth cycle must be
–
–
–
Write Enable (W) is Low and
Chip Enable (E1) is Low and E2 is High
at least one of Upper Byte Enable (UB)
and Lower Byte Enable (LB) is Low.
The Write cycle begins just after the event (the fall-
ing edge) that causes the last of these conditions
to become true (tAVWL or tAVEL or tAVBL).
The Write cycle is terminated by the rising edge of
Write Enable (W) or Chip Enable (E1), whichever
occurs first.
If the device is in Write mode (Chip Enable (E1) is
Low, Output Enable (G) is Low, Upper Byte En-
able (UB) and/or Lower Byte Enable (LB) is Low,
then Write Enable (W) will return the outputs to
high impedance within tWHDZ of its rising edge.
Care must be taken to avoid bus contention in this
type of operation. Data input must be valid for tD-
VWH before the rising edge of Write Enable (W), or
for tDVEH before the rising edge of Chip Enable
(E1), whichever occurs first, and remain valid for
tBHDZ, WHDZ, tEHDZ.
t
8/29
M69AW048B
set to ‘0000h’, and the data of the fifth cycle is the
Power-Down Configuration data (see Table
5., Power-Down Configuration Data). If the fourth
cycle is written into a different address, the se-
quence is aborted. In the last cycle, a read is made
from the specific Power-Down Configuration ad-
dress (see Table 6., Power-Down Configuration
Addresses). The Power-Down Configuration data
and address must correspond, otherwise the se-
quence is aborted.
When this sequence is performed to take the de-
vice from one PAR mode to another, the write data
may be lost. So, if a PAR mode is used, this se-
quence should be performed prior to any normal
read or write operations.
Table 2. Operating Modes
Operation
E1
E2
W
G
LB
UB
DQ0-DQ7
DQ8-DQ15
Power
V
V
Standby (I
)
SB
Standby (Deselected)
X
X
X
X
Hi-Z
Hi-Z
IH
IH
Power-Down
(I
(2)
I
V
X
X
X
X
X
Hi-Z
Hi-Z
CCPD, CCP4,
IL
Power-Down
I
I
)
CCP8, CCP16
(1)
V
V
V
V
V
V
Hi-Z
Data Output
Data Input
Hi-Z
Hi-Z
Hi-Z
Output Disable
IL
IH
IH
IH
IL
IH
IH
No Read
(1)
V
IL
V
V
V
V
V
V
Active (I
Active (I
)
)
IH
IL
IL
IH
CC
CC
Lower Byte Read
(1)
V
IL
V
V
V
V
V
V
Hi-Z
IH
IL
IL
IH
IH
IL
IH
Lower Byte Write
V
IL
V
V
V
V
No Write
Hi-Z
Output Disable
IH
IH
IH
(1)
V
IL
V
V
V
V
V
Active (I
Active (I
Active (I
Active (I
)
)
)
)
Hi-Z
Data Output
Data Input
Data Output
Data Input
IH
IH
IL
IH
IL
CC
CC
CC
CC
Upper Byte Read
(1)
V
IL
V
V
V
V
Hi-Z
IH
IL
IH
IH
IL
Upper Byte Write
(1)
V
IL
V
V
V
IL
V
V
Data Output
Data Input
IH
IH
IL
IL
Word Read
(3)
(1)
V
IL
V
V
V
V
IH
IL
V
IL
IL
Word Write
IH
Note: X = V or V .
IH
IL
1. Should not be kept in this logic condition for a period longer than 1µs.
2. Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state. The Power-Down current and data re-
tention depend on the selection of Power-Down programming.
3. G can be V during the Write operation if the following conditions are satisfied:
IL
a. Write pulse is initiated by E1 (E1 Controlled Write timing), or cycle time of the previous operation cycle is satisfied;
b. G stays V during the entire Write cycle.
IL
Table 3. Power-Down Modes
Mode
Data Retention
No
Retention Address
N/A
Deep Power-Down (Default)
4Mb PAR
8Mb PAR
16Mb PAR
4 Mbit
00000h – 3FFFFh
00000h – 7FFFFh
00000h – FFFFFh
8 Mbit
16 Mbit
9/29
M69AW048B
Table 4. Power-Down Program Sequence
Cycle #
1st
Operation
Read
Address
1FFFFFh (MSB)
1FFFFFh
Data
Read Data (RDa)
RDa
2nd
3rd
Write
Write
1FFFFFh
RDa
4th
Write
1FFFFFh
0000h
(1)
5th
Write
1FFFFFh
PDC Data
(1)
6th
Read
Read Data (RDb)
PDC Address
Note: 1. PDC Power-Down Configuration.
Table 5. Power-Down Configuration Data
Power-Down Configuration Data
Power-Down Modes
DQ15–DQ9
DQ8-DQ2
DQ1
DQ0
Deep Power-Down
(default)
0
0
1
1
4Mb PAR
8Mb PAR
16Mb PAR
0
0
0
0
0
0
1
0
0
0
1
0
Table 6. Power-Down Configuration Addresses
Power-Down Configuration Addresses
Power-Down Modes
A20
A19
A18–A0
Binary
Deep Power-Down
(default)
1
1
1
1FFFFFh
4Mb PAR
8Mb PAR
16Mb PAR
0
1
0
1
0
0
1
1
1
0FFFFFh
17FFFFh
07FFFFh
10/29
M69AW048B
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 7. Absolute Maximum Ratings
Symbol
Parameter
Min
–50
–30
–55
–0.5
–0.5
Max
50
Unit
mA
°C
°C
V
I
O
Output Current
T
A
Ambient Operating Temperature
Storage Temperature
85
T
125
3.6
3.6
STG
V
CC
Core Supply Voltage
V
IO
Input or Output Voltage
V
11/29
M69AW048B
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 8., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 8. Operating and AC Measurement Conditions
M69AW048B
Parameter
70
Unit
Min
Max
3.3
85
1
2.7
V
°C
pF
Ω
V
Supply Voltage
CC
Ambient Operating Temperature
–30
Load Capacitance (C )
50
50
L
Output Circuit Protection Resistance (R )
1
V
Input Pulse Voltages
0
V
CC
V
CC
/2
Input and Output Timing Ref. Voltages
V
V
RL
= 0.3V ; V = 0.7V
CC RH CC
Output Transition Timing Ref. Voltages
V
2
Input Transition Time (tτ) between V and
IL
5
ns
V
IH
Note: 1. All voltages are referenced to V
.
SS
2. The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 8.
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
V
/2
CC
I/O Timing Reference Voltage
R
1
V
CC
V
/2
CC
DEVICE
UNDER
TEST
OUT
0V
C
L
Output Timing Reference Voltage
V
CC
0.7V
0.3V
CC
CC
0V
AI04831
C
includes JIG capacitance
L
AI07222c
12/29
M69AW048B
Table 9. Capacitance
Symbol
Test
Condition
Parameter
Min
Max
Unit
C
V
= 0V
= 0V
Input Capacitance on all pins (except DQ)
Output Capacitance
5
8
pF
pF
IN
IN
C
V
OUT
OUT
Table 10. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
t
/ t
=
RC WC
V
= 3.3V,
= V or V ,
IH IL
CC
I
30
mA
CC1
minimum
V
IN
V
Active Current
CC
CC
E1 = V and E2 = V ,
IL
IH
t
/ t
1 µs
=
RC WC
I
3
mA
mA
CC2
I
= 0mA
OUT
V
= 3.3V,
CC
V
= V or V ,
IH IL
E1 = V and E2 = V ,
IN
I
V
Page Read Current
Power Down Current
10
CC3
IL
IH
I
= 0mA, t
= min.
OUT
PRC
Deep
Power-
Down
I
10
µA
CCPD
V
= 3.3V,
= V or V ,
IH IL
CC
V
CC
V
I
IN
4 Mb PAR
8 Mb PAR
16 Mb PAR
40
50
65
1
µA
µA
µA
µA
µA
CCP4
E2 ≤ 0.2V
I
CCP8
I
CCP16
I
LI
0V ≤ V ≤ V
IN CC
Input Leakage Current
Output Leakage Current
–1
–1
I
0V ≤ V
≤ V
OUT CC
1
LO
V
= 3.3V,
CC
I
SB
V ≤ 0.2V or V ≥ V –0.2V,
IN IN CC
Standby Supply Current CMOS
100
µA
E1 = E2 ≥ V –0.2V
CC
(1)
0.8V
V
+ 0.2
CC
Input High Voltage
Input Low Voltage
V
V
V
CC
IH
(2)
0.2V
–0.3
2.4
V
CC
IL
V
V
CC
= 2.7V, I = –0.5mA
Output High Voltage
Output Low Voltage
V
V
OH
OH
V
I
OL
= 1mA
0.4
OL
Note: 1. Maximum DC voltage on input and I/O pins is V + 0.2V.
CC
During voltage transitions, input may positive overshoot to V + 1.0V for a period of up to 5ns.
CC
2. Minimum DC voltage on input or I/O pins is –0.3V.
During voltage transitions, input may positive overshoot to V + 1.0V for a period of up to 5ns.
SS
13/29
M69AW048B
Table 11. Read Mode AC Characteristics
M69AW048B
Symbol
Alt.
Parameter
Unit
Min
Max
(1,2)
t
Address Valid Time
70
25
1000
ns
ns
t
RC
AVAX
(1,6,7)
t
Page Read Cycle Time
1000
1000
t
t
PRC
AVAX2
(1,6,7)
t
Page Read Cycle Time
25
–5
10
ns
ns
ns
ns
PRC
AVEH2
t
t
t
Address Valid to Chip Enable Low
Address Valid to Output Enable Low
Address Valid to Output Valid
AVEL
ASC
t
AVGL
ASO
(3,5)
(3,6)
(5,8)
(6,8)
(3)
t
70
18
10
10
t
AA
AVQV
t
Page Address Access Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PAA
AVQV2
t
Address Invalid Time
t
AX
AXAV
t
Page Address Invalid Time
t
AXP
AXAV2
t
t
Data hold from address change
Upper/Lower Byte Enable High to Output Transition
Upper/Lower Byte Enable High to Output Hi-Z
Upper/Lower Byte Enable Low to Output Valid
Upper/Lower Byte Enable Low to Output Transition
Chip Enable High to Address Invalid
Chip Enable High to Chip Enable Low
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
Read Cycle Time
3
3
t
OH
AXQX
BHQX
BHQZ
(3)
(4)
(3)
(4)
(9)
t
t
OH
t
20
30
BHZ
t
t
BA
BLQV
BLQX
t
0
–5
15
3
t
BLZ
t
t
CHAH
EHAX
t
t
EHEL
CP
(3)
(4)
t
t
t
OH
EHQX
t
20
1000
1000
70
CHZ
EHQZ
(1,2)
(1,2)
(3)
t
70
70
t
RC
ELAX
t
Read Cycle Time
t
RC
ELEH
t
Chip Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable High to Address Invalid
Output Data Hold Time
t
CE
ELQV
(4)
t
3
–5
3
t
CLZ
ELQX
t
t
OHAH
GHAX
(3)
t
t
OH
GHQX
(4)
(3)
(4)
t
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
20
40
t
OHZ
GHQZ
t
t
t
OE
GLQV
GLQX
t
0
OLZ
Note: 1. Maximum value is applicable if E1 is kept Low without change of address input of A3 to A20. If needed by system operation, please
contact your local ST representative for relaxation of the 1000ns limitation.
2. Address should not be changed within minimum Read Cycle Time.
3. The output load 50pF with 50Ω termination to V *0.5 V.
CC
4. The output load 5pF without any other load.
5. Applicable to A3 to A20 when E1 is kept Low.
6. Applicable only to A0, A1 and A2 when E1 is kept Low for the page address access.
7. In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4µs. In other words, Page
Read Cycle must be closed within 4µs.
8. Applicable when at least two of address inputs among applicable are switched from previous state.
9. Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied.
14/29
M69AW048B
Figure 7. Read Mode AC Waveforms
tELEH
A0-A20
ADDRESS VALID
VALID
tAVEL
tAVEL
tEHAX
tELQV
E1
tEHEL
tGLQV
tBLQV
tEHQZ
tGHQZ
tBHQZ
G
LB, UB
tBLQX
tGLQX
tEHQX
tELQX
DQ0-DQ15
VALID DATA OUTPUT
AI08986
Note: E2 = High, W = High.
Figure 8. Output Enable Controlled, Read Mode AC Waveforms
tAXAV
tAVAX
tAVAX
ADDRESS VALID
tAVQV tAXAV
A0-A20
ADDRESS VALID
tAVQV
tAXAV
E1
G
tGLQV
tGHAX
tAVGL
tGHQX
tGHQZ
UB, LB
tGLQX
tAXQX
DATA
OUT
DQ0-DQ15
DATA OUT
AI08987
Note: Write Enable (W) = High, E2 = High.
15/29
M69AW048B
Figure 9. UB/LB Controlled, Read Mode AC Waveforms
tAXAV
A0-A20
tAVAX
tAXAV
ADDRESS VALID
tAVQV
Low
E1
LB
tBLQV
tBLQV
tBHQZ
tBHQZ
tBLQV
UB
tBLQX
tBHQX
tBLQX
tBHQX
DQ0-DQ7
VALID DATA OUT
VALID DATA OUT
tBHQZ
tBHQX
tBLQX
DQ8-DQ15
VALID DATA OUTPUT
ai08990
Note: E1 = Low, E2 = High, G = Low, W = High.
Figure 10. Page Address and Chip Enable Controlled, Read Mode AC Waveforms
tELEH
A20-A3
A2-A0
ADDRESS VALID
tAVAX2
tAVAX2
tAVAX
tAVEH
ADDRESS
VALID
ADDRESS
VALID
ADDRESS VALID
ADDRESS VALID
tAVQV2
tAXAV2
tAVQV2
tAVEL
tAVQV
tELAX
tAVQV2
tEHAX
tAXAV2
tAXAV2
E
tEHQZ
tELQV
G
LB, UB
DQ0-DQ15
tELQX
tAXQX
tAXQX
tAXQX
tEHQX
VALID DATA
OUTPUT
VALID DATA
OUTPUT
VALID DATA
OUTPUT
VALID DATA
OUTPUT
AI08991
Note: Write Enable (W) = High, E2 = High.
16/29
M69AW048B
Figure 11. Random and Page Address Controlled, Read Mode AC Waveforms
tAXAV
tAVAX
tAVAX
tAXAV
A20-A3
ADDRESS VALID
ADDRESS VALID
tAXAV2
tAXAV
tAVAX2
tAXAV2
tAVAX
tAVAX
tAVAX2
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
A2-A0
tAVQV
Low
tAVQV2
tAVQV
tAVQV2
E
G
tGLQV
tBLQV
LB, UB
tGLQX
tBLQX
tAXQX
tAXQX
tAXQX
tAXQX
DATA
OUT
(Normal Access)
DATA
OUT
(Page Access)
DATA
OUT
(Normal Access)
DATA
OUT
(Page Access)
DQ0-DQ15
AI08992
Note: E2 = High.
17/29
M69AW048B
Table 12. Write Mode AC Characteristics
M69AW048B
Symbol
Alt.
Parameter
Unit
Min
Max
(1,2)
t
Write Cycle Time
70
0
1000
ns
ns
ns
ns
ns
ns
ns
ns
t
WC
AVAX
(2)
t
Address Valid to LB, UB Low
Address Valid to Chip Enable Low
Address Valid to Write Enable Low
Address Invalid Time for Write
LB, UB High to Address Transition
LB, UB High to Input High-Z
t
t
AS
AVBL
AVEL
(2)
(2)
(5)
(4)
t
0
AS
t
0
t
AS
AVWL
t
10
t
AXW
AXAV
t
15
0
1000
t
BR
BHAX
t
t
BHDZ
DH
(3)
t
LB, UB Low to LB, UB High
45
t
BW
BLBH
t
t
BWO
LB, UB Low to LB, UB High for Page Access
LB, UB Low to Write Enable High
Input Valid to LB, UB High
20
45
20
20
20
ns
ns
ns
ns
ns
BLBH2
(3)
t
t
BW
BLWH
t
t
DVBH
DS
t
t
Input Valid to Chip Enable High
Input Valid to Write Enable High
DVEH
DS
t
t
DVWH
DS
(4)
t
Chip Enable High to Address Transition
Chip Enable High to Input High-Z
15
0
ns
ns
ns
t
WRC
EHAX
t
t
EHDZ
DH
t
t
Chip Enable High to Chip Enable Low
15
EHEL
CP
(1,2)
(3)
t
Write Cycle Time
70
45
0
1000
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WC
ELAX
t
Chip Enable Low to Chip Enable High
Output Enable High to Address Valid
Output Enable High to Chip Enable Low
Output Enable High to Output Hi-Z
Write Enable High to Address Transition
Write Enable High to Input High-Z
Write Enable Low to LB, UB High
Write Enable Low to Write Enable High
t
CW
ELEH
(7)
(6)
(4)
(4)
t
t
OES
GHAV
t
–5
t
OHCL
GHEL
t
20
t
OHZ
GHDZ
t
15
0
1000
t
WR
WHAX
t
t
WHDZ
DH
(3)
t
45
45
t
WP
WLBH
WLWH
(3)
t
t
WP
Note: 1. Maximum value is applicable if E1 is kept Low without any address change. If needed by system operation, please contact your
local ST representative for relaxation of the 1000ns limitation.
2. Minimum value must be equal to or greater than the sum of write pulse (t
WHAX
3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last.
, t
or t
) and write recovery time (t
,
ELEH WLBH
BLBH
EHAX
t
or t
).
BHAX
4. Write recovery is defined from Write pulse is defined from the rising edge of E1, W, or LB/UB, whichever occurs first.
5. Applicable to any address change when E1 stays Low.
6. If G is Low after minimum t
, the read cycle is initiated. In other words, G must be brought High within 5ns after E1 is brought
GHEL
Low. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
7. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before
new address valid. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
18/29
M69AW048B
Figure 12. Chip Enable Controlled, Write AC Waveforms
tELAX
A0-A20
ADDRESS VALID
ADDRESS VALID
tEHAX
tWHAX
tBHAX
tAVEL
tAVWL
tAVBL
tELEH
tWLWH
tBLWH
tAVEL
E1
tAVWL
W
tAVBL
LB, UB
tGHEL
G
tDVEH
tDVWH
tDVBH
tEHDZ
tWHDZ
tBHDZ
DQ0-DQ15
VALID DATA INPUT
ai08993
Note: E2 = High.
Figure 13. Write Enable Controlled, Write AC Waveforms
tAVAX
tAVAX
tAXAV
A0-A20
ADDRESS VALID
ADDRESS VALID
tWHAX
tWLWH
E1
W
Low
tAVWL
tAVWL
tWLWH
tWHAX
LB, UB
G
tGHAV
tDVWH
tGHDZ
tWHDX
tDVWH
tWHDZ
VALID DATA
INPUT
VALID DATA
INPUT
DQ0-DQ15
AI08994b
Note: E2 = High.
19/29
M69AW048B
Figure 14. Write Enable and UB/LB Controlled, Write AC Waveforms 1
tAVAX
tAVAX
A0-A20
E1
ADDRESS VALID
ADDRESS VALID
tAXAV
Low
tAVWL
tWLBH
tAVWL
tWLBH
tBHAX
W
tBHAX
LB
UB
tDVBH
tBHDZ
VALID DATA
INPUT
DQ0-DQ7
tDVBH
tBHDZ
VALID DATA
INPUT
DQ8-DQ15
AI08995b
Note: E2 = High.
Figure 15. Write Enable and UB/LB Controlled, Write AC Waveforms 2
tAXAV
tAVAX
tAVAX
A0-A20
E1
ADDRESS VALID
ADDRESS VALID
tAXAV
Low
tAVBL
tBLWH
tBLWH
tWHAX
W
tWHAX
LB
tAVBL
UB
tDVWH
tWHDZ
VALID DATA
INPUT
DQ0-DQ7
tDVWH
tWHDZ
VALID DATA
INPUT
DQ8-DQ15
AI08996b
Note: E2 = High.
20/29
M69AW048B
Figure 16. Write Enable and LB/UB Controlled, Write AC Waveforms 3
tAVAX
tAVAX
tAXAV
A0-A20
E1
ADDRESS VALID
ADDRESS VALID
tAXAV
Low
tAVBL
tBLBH
tBLBH
tBHAX
W
tBHAX
LB
tAVBL
UB
tDVBH
tBHDZ
VALID DATA
INPUT
DQ0-DQ7
tBVWH
tBHDZ
VALID DATA
INPUT
DQ8-DQ15
AI08997b
Note: E2 = High.
Figure 17. Write Enable and LB/UB Controlled, Write AC Waveforms 4
tAXAV
tAVAX
tAVAX
A0-A20
E1
ADDRESS VALID
ADDRESS VALID
tAXAV
Low
W
tBHAX
tBLBH
tAVBL
tAVBL
tBLBH
tBHAX
LB
tBLBH2
tDVBH
tAVBL
tDVBH
tBHDZ
tBHAX
tBHDZ
VALID DATA
INPUT
VALID DATA
INPUT
DQ0-DQ7
UB
tBHAX
tBLBH
tBLBH2
tBLBH
tAVBL
tDVBH
tBHDZ tDVBH
tBHDZ
VALID DATA
INPUT
VALID DATA
INPUT
DQ8-DQ15
AI08998b
Note: E2 = High.
21/29
M69AW048B
Figure 18. Chip Enable Controlled, Read Followed by Write Mode AC Waveforms
tELAX
tELAX(read)
A0-A20
WRITE ADDRESS
READ ADDRESS
tAVEL
(read)
tEHAX
(read)
tAVEL
tEHAX
tEHAX(read)
E1
W
tEHEL
tELEH
tEHEL
tELQV
UB, LB
G
tGHEL
tEHQZ
tEHQX
tELQX
tDVEH
tEHDZ
tEHQX
READ DATA
OUTPUT
WRITE DATA
INPUT
READ DATA
OUTPUT
DQ0-DQ15
ai08999b
Note: Write address is valid from either E1 or W of last falling edge.
Figure 19. E1, W, G Controlled, Read and Write Mode AC Waveforms
tELAX
tELAX(read)
READ ADDRESS
tAVEL
A0-A20
WRITE ADDRESS
tEHAX
(read)
tAVEL
tWHAX
tEHAX(read)
(read)
E1
W
tEHEL
tELEH
tEHEL
tELQV
tWLWH
UB, LB
G
tGHEL
tGHQV
tEHQZ
tEHQX
tGLQX
tWHDZ
tGHQX
tDVWH
READ DATA
OUTPUT
WRITE DATA
INPUT
READ DATA
OUTPUT
DQ0-DQ15
ai09400b
Note: G can be Low fixed in write operation under E1 control read-write-read operation.
22/29
M69AW048B
Figure 20. Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms
tAXAV
tAVAX
tAVAX(read)
A0-A20
WRITE ADDRESS
READ ADDRESS
tAXAV
tAVQV
E1
W
Low
tWLWH
tWHAX
tAVWL
UB, LB
G
tAVGL
tGLQV
tGHQZ
tGLQX
tWHDZ
tGHQZ
tGHQX
tGHQX
DATA
tDVWH
DATA
IN
DATA
OUT
DQ0-DQ15
OUT
ai09401b
Note: E1 can be tied to Low for W and G controlled operation.
When E1 is tied to Low, output is exclusively controlled by G.
Figure 21. Output Enable, Write Enable and UB/LB Controlled, Read and Write Mode AC
Waveforms
tAXAV
tAVAX
tAVAX(read)
A0-A20
WRITE ADDRESS
READ ADDRESS
tAXAV
tAVQV
E1
W
Low
tAVBL
tBLBH
tBHAX
tBLQV
UB, LB
G
tAVGL
tBHQZ
tBHQX
tBHQZ
tBHQX
tBLQX
tBHDZ
tDVBH
DATA
OUT
DATA
IN
DATA
OUT
DQ0-DQ15
ai09402b
Note: E1 can be tied to Low for W and G controlled operation.
When E1 is tied to Low, output is exclusively controlled by G.
23/29
M69AW048B
Table 13. Standby/Power-Down Mode AC Characteristics
M69AW048B
Symbol
Alt.
Parameter
Unit
Min
Max
t
t
CSP
E2 Low Setup Time for Power Down Entry
E2 Low Hold Time after Power Down Entry
10
70
ns
ns
CLEX
t
t
C2LP
EXCH
E1 High Hold Time following E2 High after Power-
Down Exit (Deep Power-Down Mode only)
(1)
t
300
1
µs
µs
µs
t
CHH
EHEV
E1 High Hold Time following E2 High after Power-
Down Exit (not in Deep Power-Down Mode)
(2)
t
t
CHHP
CHEL
E1 High Setup Time following E2 High after Power-
Down Exit
t
t
0
EHCH
CHS
t
t
E1 High to G Invalid Time for Standby Entry
E1 High to W Invalid Time for Standby Entry
Input Transition Time
10
10
1
ns
ns
ns
EHGL
CHOX
CHWX
tτ
(3)
t
t
EHWL
(4)
25
tτ
Note: 1. Applicable also to Power-up.
2. Applicable when 4Mb, 8Mb and 16Mb PAR mode is programmed
3. Some data might be written into any address location if t
(min) is not satisfied.
EHWL
4. The Input Transition Time (tτ) at AC testing is 5ns as shown below. If actual tτ is longer than 5ns, it may violate AC specification of
some timing parameters.
Figure 22. Power Down Program AC Waveforms
tAVAX
2
2
2
2
2
3
PDCADD
A0-A20
E1
MSB
MSB
tAXAV
MSB
MSB
MSB
4
tAXAVL
G
W
LB, UB
4
DQ0-DQ15
RDa
RDa
Cycle 2
RDa
00
Cycle 4
PDCD
Cycle 5
RDb
Cycle 6
Cycle 1
Cycle 3
AI07225c
Note: 1. E2 = High.
2. All address inputs must be High from Cycle 1 to Cycle 5.
3. PDCADD stands for Power-Down Configuration Address. It must be compliant with the format specified in Table 6 otherwise the
data programmed during the Power-Down Program sequence may be incorrect.
4. PDCDAT stands for Power-Down Configuration Data. It must be compliant with the format specified in Table 5 otherwise the data
programmed during the Power-Down Program sequence may be incorrect.
5. t
after the end of Cycle 6, the Power Down Program is completed and the device returns to normal operation.
EHEL
24/29
M69AW048B
Figure 23. Power-Down Mode AC Waveforms
E1
tEHCH
tCHEL
E2
tCLEX
tEXCH
DQ0-D15
Hi-Z
Power-Down Power-Down Mode Power-Down
AI09403
Entry
Exit
Figure 24. Power-Up Mode AC Waveforms
E1
E2
tEHEL
VDDmin
VDD
AI09404
Figure 25. Standby Mode Entry AC Waveforms, After Read
E1
tEHGL
tEHWL
G
W
Read Active
Standby
Write Active
Standby
AI09405
Note: E2 = High.
25/29
M69AW048B
PACKAGE MECHANICAL
Figure 26. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View
D
D1
FD
FE
SD
SE
BALL "A1"
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z26
Note: Drawing is not to scale.
Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.260
0.0102
0.900
0.0354
0.350
5.900
–
0.450
0.0138
0.2323
–
0.0177
D
6.000
3.750
6.100
0.2362
0.1476
0.2402
D1
ddd
E
–
–
0.100
0.0039
8.000
5.250
0.750
1.125
1.375
0.375
0.375
7.900
8.100
0.3150
0.2067
0.0295
0.0443
0.0541
0.0148
0.0148
0.3110
0.3189
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
26/29
M69AW048B
PART NUMBERING
Table 15. Ordering Information Scheme
Example:
M69AW048 B
L
70 ZB
8
Device Type
M69 = PSRAM
Mode
A = Asynchronous
Operating Voltage
W = 2.7 to 3.3V
Array Organization
048 = 32 Mbit (2M x16)
Option 1
B = 2 Chip Enable
Option 2
L = Low Leakage
Speed Class
70= 70 ns
Package
ZB = TFBGA48, 0.75mm pitch
Operative Temperature
8 = –30 to 85 °C
The notation used for the device number is as shown in Table 15.. For a list of available options (speed,
package, etc.) or for further information on any aspect of this device, please contact your nearest STMi-
croelectronics Sales Office.
27/29
M69AW048B
REVISION HISTORY
Table 16. Document Revision History
Date
Version
-01
Revision Details
07-Oct-2002
10-Mar-2003
First Issue
2.0
Document completely revised
Data Key and Address Key renamed Power-Down Configuration data and Power-Down
Configuration Address respectively. Sleep mode renamed Deep Power-Down mode.
I
removed and I renamed I
in Table 10., DC Characteristics.
CCS
PD
CCPD
Partial mode renamed Partial Array Refresh.
Table 12. Write Mode AC Characteristics: t
9-Mar-2004
3.0
added and Note 2 updated.
GHDZ
t
changed to t
in Figure 13.Write Enable Controlled, Write AC Waveforms.
GHQZ
GHDZ
AC Waveforms converted to ST standard.
t
, t , t changed into t , t
, t
in Table 11., Read Mode AC
ELQZ GLQZ BLQZ
ELQX GLQX BLQX
21-Sep-2004
15-Nov-2004
4.0
5.0
Characteristics.
V
value updated in Table 10., DC Characteristics.
OH
28/29
M69AW048B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
29/29
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