PM6685 [STMICROELECTRONICS]

DUAL STEP-DOWN CONTROLLER WITH AUXILARY VOLTAGES FOR NOTEBOOK SYSTEM POWER; 与辅助的电压,用于笔记本电脑系统电源双路降压型控制器
PM6685
型号: PM6685
厂家: ST    ST
描述:

DUAL STEP-DOWN CONTROLLER WITH AUXILARY VOLTAGES FOR NOTEBOOK SYSTEM POWER
与辅助的电压,用于笔记本电脑系统电源双路降压型控制器

电脑 控制器
文件: 总16页 (文件大小:892K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
PM6685  
DUAL STEP-DOWN CONTROLLER WITH AUXILARY VOLTAGES  
FOR NOTEBOOK SYSTEM POWER  
Preliminary Data  
Features  
CONSTANT ON TIME TOPOLOGY ALLOWS  
VERY FAST LOAD TRANSIENTS  
6V TO 28V INPUT VOLTAGE RANGE  
FIXED 5V-3.3V OUTPUT VOLTAGES  
5V AND 3.3V ALWAYS VOLTAGES  
AVAILABLE DELIVER 100mA PEAK  
CURRENT  
VFQFPN-32 5X5  
1.23V ± ±1% REFERENCE VOLTAGE  
AVAILABLE  
Description  
NO R  
CURRENT SENSING USING  
SENSE  
PM6685 is  
a
dual step-down controller  
LOW SIDE MOSFETs’ R  
DS(on)  
specifically designed to provide extremely high  
efficiency conversion, with lossless current  
sensing technique. The constant on-time  
architecture assures fast load transient response  
and the embedded voltage feed-forward provides  
nearly constant switching frequency operation. An  
embedded integrator control loop compensates  
the DC voltage error due to the output ripple.  
Pulse skipping technique increases efficiency at  
very light load. Moreover a minimum switching  
frequency of 25kHz is selectable to avoid audio  
noise issues. The PM6685 provides a selectable  
switching frequency, allowing either 200kHz/  
300kHz, 300kHz/400Khz or 400kHz/500kHz  
operation of the 5V/3.3V switching sections...  
ACCURATE CURRENT SENSE WITH  
R
SENSE  
NEGATIVE CURRENT LIMIT  
SOFT START INTERNALLY FIXED AT 2ms  
SOFT OFF FOR OUTPUT DISCHARGE  
LATCHED OVP AND UVP  
SELECTABLE PULSE SKIPPING AT LIGHT  
LOADS  
SELECTABLE MINIMUM FREQUECY  
(25kHz) IN PULSE SKIP MODE  
4 mW MAXIMUM QUIESCENT POWER  
INDIPENDENT POWER GOOD SIGNALs  
OUTPUT VOLTAGE RIPPLE  
Applications  
COMPENSATION  
NOTEBOOK COMPUTERS  
TABLET PC OR SLATES  
MOBILE SYSTEM POWER SUPPLY  
3-4 CELLS Li+ BATTERY POWERED  
DEVICES  
Order codes  
Part number  
Marking  
Package  
Packing  
PM6685  
PM6685  
VFQFPN-32 5X5  
TAPE & REEL  
Rev 1  
1/16  
September 2005  
This is preliminary information on a new product now in development or undergoing evaluation.  
Details are subject to change without notice.  
www.st.com  
16  
PM6685  
Contents  
1
2
3
4
5
6
7
Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Block & pin connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Functional & block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
2/16  
PM6685  
1 Typical application circuit  
1
Typical application circuit  
Figure 1. Circuit  
3/16  
2 Electrical ratings  
PM6685  
2
Electrical ratings  
Table 1.  
Absolute maximum ratings  
Parameter  
Symbol  
Value  
Unit  
SGND1 to SGND2  
Shorted  
COMPx, FSEL, LDO3_SEL, VREF, SKIP to SGND1,  
SGND2  
-0.3 to V + 0.3  
V
CC  
Enx, SHDN, PGOD_LDO3, OUTx, PGOODx, V to  
CC  
-0.3 to 6  
SGND1, SGND2  
LDO3 to SGND1, SGND2  
LGATEx to PGND  
-0.3 to LDO5 + 0.3  
-0.3 to LDO5 + 0.3  
-0.3 to 6  
V
V
V
V
V
V
V
V
V
W
HGATEx and BOOTx, to PHASEx  
PHASEx to PGND  
-0.6 to 36  
-0.6 to 42  
-6 to 0.3  
CSENSEx, to PGND  
CSENSEx to BOOTx  
V5SW, LDO5 to PGND  
VIN to PGND  
-0.3 to 0.6  
-0.3 to 36  
-0.3 to 0.3  
2
PGND to SGND1, SGND2  
Power dissipation at T  
= 25°C  
amb  
Table 2.  
Symbol  
Thermal data  
Description  
Value  
Unit  
Thermal Resistance Junction to ambient (mounted on  
demoboard)  
R
T
45  
°C/W  
thJA  
Storage temperature range  
-40 to 150  
-10 to 125  
°C  
°C  
STG  
T
Junction operating temperature range  
J
4/16  
PM6685  
3 Block & pin connection diagrams  
3
Block & pin connection diagrams  
Figure 2. Pin connection diagram (top view)  
5/16  
3 Block & pin connection diagrams  
PM6685  
Table 3.  
Pin No  
Pin description  
PM6685  
Function  
1
2
SGND  
Signal ground. Reference for internal logic circuitry.  
COMP3  
DC voltage error compensation pin for the 3.3V switching section.  
Frequency selection pin. It provides a selectable switching frequency, allowing  
either 200kHz/300kHz, 300kHz/400kHz or 400kHz/500kz operation of the 5V/  
3.3V switching sections.  
3
FSEL  
EN3  
3.3V SMPS enable input. The 3.3V section is enabled appling a high logic level  
(>2.4V) to this pin, while is disabled appling a low logic level (<0.8V). When the  
section is disabled the High Side gate driver goes low and Low Side gate driver  
goes high. If both EN3 and EN5 pins are low and SHDN pin is high the device  
enters in standby mode.  
4
Shutdown control input. The device enters its shutdown mode with 9µA of supply  
current if VSHDN is less than the device off threshold voltage and doesn't restart  
until VSHDN is greater than the device on threshold voltage. The SHDN pin can  
be connected to Vbatt through a voltage divider to program an undervoltage  
lockout. In shutdown mode, the gate drivers of the two switching sections are in  
high impedance.  
5
6
SHDN  
Power Good ouput signal for the 3.3V linear regulator. This pin is an open drain  
PGOOD LDO3 output. It is shorted to GND if LDO3_SEL pin is at its low level or if the ouput  
voltage on LDO3 pin is lower than 2.6V.  
3.3V Linear regulator output. LDO3 can provide 100mA peak current. If  
LDO3_SEL pin is connected to VREF and OUT3 is greater than the LDO3  
bootstrap switch threshold, the LDO3 regulator shuts down and the LDO3 pin will  
7
8
LDO3  
be directly connected to OUT3 through a 3 (max) switch.  
If LDO3_SEL pin is at its low level the LDO3 is always OFF.  
If LDO3_SEL pin is at its high level the LDO3 is always ON.  
Output voltage sense for the 3.3V switching section.This pin must be directly  
connected to the output voltage of the switching section.  
OUT3  
Bootstrap capacitor connection for the switching 3.3V section. It supplies the high-  
side gate driver.  
9
BOOT3  
10  
11  
HGATE3  
PHASE3  
High-side gate driver ouput for the 3.3V section.  
Switch node connection and return path for the high side driver for the 3.3V  
section.  
Current sense input for the switching 3.3V section. This pin must be connected  
through a resistor to the drain of the synchronous rectifier (RDSON sensing) or to  
the source of the synchronous rectifier (RSENSE sensing) to set the current limit  
threshold.  
12  
CSENSE3  
13  
14  
15  
16  
LGATE3  
PGND  
Low-side gate driver output for the 3.3V section.  
Power ground.  
LGATE5  
SGND2  
Low-side gate driver output for the 5V section.  
Signal ground for analog circuitry.  
Internal 5V regulator bypass connection. When the main 5V ouput voltage is  
greater than the boostrap switch threshold, the LDO5 regulator shuts down and  
the LDO5 pin will be directly connected to OUT5 through a 3 (max) switch.  
17  
V5SW  
If not used, it must be tied to ground.  
6/16  
PM6685  
3 Block & pin connection diagrams  
Table 3.  
Pin description  
5V internal regulator output. LDO5 pin supplies all gate drivers, the internal  
circuitry and an external load. It can provide up to 100mA peak current.  
18  
LDO5  
Device input supply voltage. A bypass filter (4 and 4.7 µF) between the battery  
19  
20  
VIN  
and this pin is recommended.  
Current sense input for the switching 5V section. This pin must be connected  
through a resistor to the drain of the synchronous rectifier (R  
sensing) or to  
DSON  
CSENSE5  
the source of the synchronous rectifier (R  
threshold.  
sensing) to set the current limit  
SENSE  
21  
22  
PHASE5  
HGATE5  
Switch node connection and return path for the high side driver for the 5V section.  
High-side gate driver ouput for the 5V section.  
Bootstrap capacitor connection for the switching 5V section. It supplies the high-  
side gate driver.  
23  
BOOT5  
Pulse skipping mode control input. It is a three states pin.  
If the pin is at its high level(e.g. cnnected to LDO5) the PWM mode is enabled.  
If the pin is at its low level (e.g. connected to GND), the pulse skip mode is  
enabled.  
24  
SKIP  
If the pin is at its middle level (e.g. connected to Vref) the pulse skip mode is  
enabled but limiting the min frequency to 25KHz.  
5V SMPS enable input. The 5V section is enabled appling a high logic level  
(>2.4V) to this pin, while is disabled appling a low logic level (<0.8V). When the  
section is disabled the High Side gate driver goes low and Low Side gate driver  
goes high. If both EN3 and EN5 pins are low and SHDN pin is high the device  
enters in standby mode.  
25  
EN5  
Power Good ouput signal for the 5V section. This pin is an open drain ouput.  
26  
27  
PGOOD5  
PGOOD3  
The pin is pulled low if the output is disabled or is out of the specified window  
(approximately +/- 10% of its nominal value).  
Power Good ouput signal for the 3.3V section. This pin is an open drain ouput.  
The pin is pulled low if the output is disabled or is out of the specified window  
(approximately +/- 10% of its nominal value).  
Control pin for the 3.3V internal linear regulator. This pin determines three  
operative modes for the LDO3.  
If LDO3_SEL pin is at its low level the LDO3 is always OFF.  
If LDO3_SEL pin is at its high level the LDO3 is always ON  
28  
29  
LDP3SEL  
If LDO3_SEL pin is connected to VREF and OUT3 is greater than the LDO3  
bootstrap switch threshold, the LDO3 regulator shuts down and the LDO3 pin will  
be directly connected to OUT3 through a 3 (max) switch.  
Output voltage sense for the 5V switching section.This pin must be directly  
connected to the output voltage of the switching section.  
OUT5  
30  
31  
COMP5  
DC voltage error compensation pin for the 5V switching section.  
Device Supply Voltage pin. Connect this pin to LDO5  
V
CC  
High accuracy output voltage reference (1.237V). It can deliver 50uA. Bypass to  
SGND with a 100nF capacitor.  
32  
VREF  
7/16  
4 Electrical characteristics  
PM6685  
4
Electrical characteristics  
(V = 12V; T  
= 0°C to 85°C unless otherwise specified)  
IN  
amb  
Table 4.  
Simbol  
Supply section  
Parameter  
Test Condition  
Min.  
6
Typ.  
Max.  
Unit  
V
V
=V , LDO5 in regulation  
Input voltage range  
28  
5.5  
4.9  
V
IN  
out  
ref  
V
IC supply voltage  
4.5  
V
V
CC  
Turn-on voltage threshold  
Turn-off voltage threshold  
Hysteresis  
4.8  
4.75  
50  
V
4.6  
V
V5SW  
mV  
V
V
Maximum operating range  
5.5  
3
V5SW  
LDO5 Internal Bootstrap  
Switch Resistance  
R
V5SW >4.9V  
1.8  
1.8  
12  
DS(on)  
LDO3 Internal Bootstrap  
Switch Resistance  
VOUT3 = 3.3V  
3
OUT_ Discharge-Mode  
On-resistance  
25  
R
DS(on)  
OUT3, OUT5_ Discharge-Mode  
Synchronuos Rectifier  
0.2  
0.35  
0.5  
4
V
Turn-on level  
VOUT5>5.1V,VOUT3>3.34V  
V5SW to 5V  
Pin  
Operating Power consumption  
mW  
LDO5, LDO3 no load  
V
V
Shutdown Current  
Standby Current  
Ish  
Isb  
SHDN connected to GND,  
ENx to GND, V5SW to GND  
14  
18  
µA  
µA  
IN  
IN  
150  
250  
Table 5.  
Simbol  
Shutdown section  
Parameter  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Device ON threshold  
Device OFF threshold  
0.95  
0.8  
1.35  
0.85  
1.6  
0.9  
V
V
V
SHDN  
8/16  
PM6685  
Table 6.  
Simbol  
Electrical characteristics (continued)  
Parameter  
Test Condition  
Min.  
2
Typ.  
Max.  
6
Unit  
ms  
Soft Start Ramp time  
Input bias current limit  
I
90  
-5  
100  
110  
5
µA  
CSENSE  
V
V
- V  
Comparator offset  
mV  
mV  
CSENSE  
PGND  
PGND  
- V  
Zero Crossing Comparatot Offset  
-5  
5
PHASE  
PHASE  
Fixed Negative current limit  
Threshold  
V
- V  
-120  
mV  
ns  
PGND  
OUT5=5V  
OUT3=3.3V  
OUT5=5V  
OUT3=3.3V  
OUT5=5V  
OUT3=3.3V  
2083  
917  
FSEL to GND  
FSEL to VREF  
FSEL to LDO5  
1390  
688  
T
ON-Time duration  
ON  
1040  
550  
T
Minimum OFF-Time  
Voltage Accuracy  
Load regulation  
300  
350  
ns  
V
OFFMIN  
4.2V < V  
< 5.5V  
1.224 1.237 1.249  
LDO5  
-100µA < I  
< 100µA  
-4  
4
mV  
REF  
V
REF  
Undervoltage Lockout fault  
threshold  
Falling edge of REF  
0.95  
V
COMP  
COMP  
Over voltage clamp  
Under voltage clamp  
Line regulation  
250  
mV  
-150  
Both SMPS, 6V< V <28V  
0.004 %/V  
5.1  
IN  
6V < V < 28V,  
IN  
LDO5 linear Output Voltage  
LDO5 line regulation  
LDO5 Current limit  
4.9  
5.0  
V
0 < I  
< 50mA  
LDO5  
V
I
LDO5  
6V < V < 28V, I  
= 50mA  
LDO5  
IN  
0.004 %/V  
LDO3_SEL tied to GND  
> UVLO, I = 0A V  
OUT5  
V
LDO5  
LDO3  
300  
350  
400  
mA  
LDO5  
> 5.1V, V  
> 3.34V  
OUT3  
UVLO  
Under Voltage Lockout of LDO5  
LDO3 linear Ouput Voltage  
LDO3 Current limit  
3.94  
3.23  
130  
4
4.13  
3.37  
V
V
V
0 < I  
< 50mA  
LDO3  
3.3  
LDO3  
I
V
> UVLO  
LDO5  
200  
3
mA  
LDO3  
HGATEx high state(pullup)  
2.0  
1.8  
1.4  
0.6  
HGATE driver on-resistance  
LGATE driver on-resistance  
HGATEx low state (pulldown)  
LGATEx high state(pullup)  
LGATEx low state (pulldown)  
2.7  
2.1  
0.9  
9/16  
4 Electrical characteristics  
PM6685  
Table 6.  
Simbol  
Electrical characteristics (continued)  
Parameter  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
High side rise time  
20  
20  
40  
40  
120  
72  
113  
94  
1
HGATEx-PHASE from 1V to 4V  
CLOAD = 3.3nF  
ns  
High side fall time  
Low side rise time  
LGATEx-PGND from 1V to 4V  
CLOAD = 8.2nF  
ns  
OVP  
UVP  
Over voltage threshold  
113  
66  
116  
70  
%
%
Both SMPS sections with respect  
to VREF.  
Under voltage threshold  
Upper threshold (VFB-VREF)  
Lower threshold (VFB-VREF)  
PGOOD leakeage current  
107  
90  
110  
92  
%
PGOOD3,5  
%
I
VPGOOD3,5 forced to 5.5V  
ISink = 4mA  
µA  
PGOOD3,5  
V
Ouput Low Voltage  
Rising voltage threshold  
Falling voltage threshold  
Hytseresis  
150  
2.58  
2.55  
25  
250  
mV  
V
PGOOD3,5  
PGOOD  
LDO3  
V
mV  
I
PGOOD_LD  
O3  
V
forced to 5.5V  
PGOOD leakeage current  
Ouput Low Voltage  
1
µA  
PGOOD LDO3  
V
PGOOD_LD  
O3  
ISink = 4mA  
150  
250  
mV  
°C  
T
Shutdown Temperature  
SMPS disabled level  
SMPS enabled level  
150  
0.8  
SDN  
EN3,5  
FSEL  
V
2.4  
1.0  
Low level  
0.5  
V
LDO5  
Middle level  
Frequency selection range  
-1.5  
V
V
LDO5  
High level  
-0.8  
Always-off level  
Boostrap level  
0.5  
V
LDO5  
1.0  
3.3V Linear Regulator Selection  
Pin  
LDO3 SEL  
-1.5  
V
V
V
LDO5  
Always-on level  
-0.8  
Pulse Skip Mode  
PWM Mode  
0.5  
V
LDO5  
1.0  
SKIP  
-1.5  
V
LDO5  
Ultrasonic Mode  
-0.8  
10/16  
PM6685  
4 Electrical characteristics  
Table 6.  
Simbol  
Electrical characteristics (continued)  
Parameter  
Test Condition  
= 0 to 5V  
Min.  
Typ.  
Max.  
Unit  
V
TBV  
TBV  
TBV  
TBV  
TBV  
EN3,4  
V
= 0 to 5V  
SKIP  
I
V
V
V
= 0 to 5V  
SHDN  
Input leakage current  
µA  
LEAK  
= 0 to 5V  
FSEL  
LDO3_SEL  
= 0 to 5V  
11/16  
5 Functional & block diagram  
PM6685  
5
Functional & block diagram  
Figure 3. Block diagram  
12/16  
PM6685  
6 Package Mechanical Data  
6
Package Mechanical Data  
®
In order to meet environmental requirements, ST offers these devices in ECOPACK  
packages. These packages have a Lead-free second level interconnect . The category of  
second Level Interconnect is marked on the package and on the inner box label, in compliance  
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also  
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are  
available at: www.st.com.  
13/16  
6 Package Mechanical Data  
PM6685  
Table 7.  
Dim.  
VFQFPN 5x5x1.0 32L Pitch 0.50  
Databook (mm.)  
Drawing (mm.)  
Typ.  
Min.  
Typ.  
Max  
Min.  
Max  
A
A1  
A3  
b
0.80  
0
0.90  
0.02  
0.20  
0.25  
5.00  
1.00  
0.05  
0.80  
0
1.00  
0.05  
0.25  
5.00  
0.18  
4.85  
0.30  
5.15  
0.225  
4.90  
0.275  
5.10  
(3)  
D
(5)  
3.65  
4.85  
3.65  
3.95  
5.15  
3.95  
3.65  
4.90  
3.65  
3.95  
5.10  
3.95  
D2  
(3)  
5.00  
5.00  
0.50  
E
(5)  
E2  
e
0.50  
0.40  
L
0.30  
0.50  
0.35  
0.45  
1. – VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead.  
___Very thin: A = 1.00mm Max.  
2. – The leads size have been increased by Pb/Sn thickness in tin plating electrolytic process.  
3. – Dimensions D & E do not include mold protusion, not to exceed 0,15mm.  
4. – Package outline exclusive of metal burr dimensions.  
5. – Dimensions D2 & E2 are not in accordance with JEDEC.  
Figure 4. Scheme Drawings  
14/16  
PM6685  
7 Revision history  
7
Revision history  
Date  
23-Sep-2005  
Revision  
Changes  
1
Initial release.  
15/16  
7 Revision history  
PM6685  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics.  
All other names are the property of their respective owners  
© 2005 STMicroelectronics - All rights reserved  
STMicroelectronics group of companies  
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -  
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America  
www.st.com  
16/16  

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