ST72671N4B1/XXX [STMICROELECTRONICS]
8-BIT, MROM, 8MHz, MICROCONTROLLER, PDIP56, 0.600 INCH, SHRINK, PLASTIC, DIP-56;
| 型号： | ST72671N4B1/XXX |
| 厂家： | 
ST |
| 描述： | 8-BIT, MROM, 8MHz, MICROCONTROLLER, PDIP56, 0.600 INCH, SHRINK, PLASTIC, DIP-56 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总101页 (文件大小：608K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R
ST72671
8-BIT USB MCUs WITH 16K TO 32K ROM/OTP/EPROM,
2
512 BYTES TO 1K RAM, ADC, DAC (PWM), TIMER, I C AND SCI
PRODUCT PREVIEW
■ User Program Memory ROM/OTP/EPROM:
16K to 32K bytes
■ Data RAM: 512 bytes to 1K byte (256 bytes
stack)
■ Master Reset and Power on/off reset
■ Run, Wait, Slow, Halt and RAM Retention
modes
■
USB (Universal Serial Bus) with 2 endpoints
including:
PSDIP56
– Integrated 3.3V voltage regulator
– Integrated Transceiver
– Suspend and Resume operations
■ 32 I/O lines
– 5 programmable interrupt inputs
– 8 high sink outputs
CSDIP56
TQFP64
– 8 analog alternate inputs
– 18 alternate functions
– EMI filtering
■ Programmable Watchdog (WDG)
■
16-bit Timer, featuring:
– 2 Input Captures
– 2 Output Compares (with 1 output pin)
– PWM and Pulse Generator modes
■ 8-bit Analog to Digital Converter with 8 channels
on port B
■ Four 10-bit and one 12-bit Digital to Analog
Device Summary
Features
Converter Channels with PWM output
ST72671N4
16K
ST72671N6
32K
2
I C
■ Fast
Multi Master Interface
Program memory -bytes
RAM (stack) - bytes
USB
■ Serial Communications Interface (SCI)
■ 63 basic instructions
512 (256)
1K (256)
2 endpoints
■
17 main address modes
10-Bit D/A Converter
12-Bit D/A Converter
A/D Converter
4 channels
1 channel
■ 8x8 unsigned multiply instruction
■ True bit manipulation
8 channels
16-Bit Timer
1
■
Complete Development Support on PC/DOS-
TM
2
I C Bus
I/Os
1 multimaster
34
WINDOWS Real-Time Emulator
TM
■ Full Software Package on DOS/WINDOWS
Operating Supply
CPU Frequency
Temperature Range
Package
4.0 to 5.5 V
(C-Compiler, Cross-Assembler, Debugger)
8 MHz max (24 MHz quartz)
0°C to + 70°C
QFP64 - SDIP56
Rev. 1.1
1/101
March 1998
This is preliminary informationona newproduct in development orundergoing evaluation.Detailsare subject tochange without notice.
1
Table of Contents
ST72671 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.1.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2.4 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.2.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.3.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.4 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
101
4.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.4.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2/101
2
Table of Contents
4.4.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.5 I C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4.5.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
4.6 SERIAL COMMUNICATIONS INTERFACE (SCI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.6.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.7 PWM/BRM GENERATOR (DAC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.7.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
4.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
4.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
4.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
4.8.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6 ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.1 ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.2 RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.4 A/D CONVERTER CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.5 PWM (DAC) CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.5.1 I2C CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.2 PACKAGE MECHANICAL DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.3.1 Transfer Of Customer Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3/101
3
ST72671
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72671 HCMOS microcontroller unit is a
member of the ST7 family with an integrated USB
interface.
In addition to standard 8-bit data management the
ST7 features true bit manipulation, 8x8 unsigned
multiplication and indirect addressing modes on
the whole memory.
It is based around an industry standard 8-bit core
and offers an enhanced instruction set. The proc-
essor runs with an external clock up to 24 MHz
with a 5V supply. Due to the fully static design of
this device, operation down to DC is possible. Un-
der software control the ST72671 can be placed in
WAIT, SLOW or HALT mode thus reducing power
consumption. The enhanced instruction set and
addressing modes afford real programming poten-
tial.
The device includes an on-chip oscillator, CPU,
16K to 32K ROM/OTP/EPROM, 512 to 1K RAM,
USB, 32 I/O lines, a Timer with 2 Input Captures
and 2 Output Compares, an 8-channel A/D Con-
2
verter, an I C multimaster, an SCI Serial Commu-
nications Interface, a Watchdog Reset, four 10-bit
and one 12-bit D/A Converter channels with PWM
output.
Figure 1. ST72671 Block Diagram
PROGRAM
MEMORY
PA0-PA7
(8 Bits)
PORT A
PORT B
ADC
(16K to 32K Bytes)
PB0-PB7
(8 Bits)
RAM
(512 to 1K Bytes)
USBV
CC
USBDP
USBDM
USGGND
USB DMA
USB SIE
PORT C
CONTROL
RESET
2
I C
PC0-PC7
(8 Bits)
8-BIT CORE
ALU
SCI
WATCHDOG
Mode
ICAP1
ICAP2
TIMER
Internal
CLOCK
OSCIN
:3
OSC
Selection
PD0-PD7
(8 Bits)
PORT D
OSCOUT
V
DD
POWER SUPPLY
V
SS
DA0-DA4
PWM (DAC)
V
DDA
V
SSA
VR02120C
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4
ST72671
1.2 PIN DESCRIPTION
Figure 2. 64-Pin QFP Package Pinout
64 636261 605958575655545352515049
NU
NU
NU
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
PD6
PD5
PD4
PD3
PD2
PD1
PD0
VSS
2
3 (EI0)
4 (EI1)
5 (EI2)
6
7
8
9
10
11
12
13
14 (EI4)
15
DA4
DA3
DA2
DA1
DA0
TEST/VPP
NU
RESET
PA0
PA1
PA2
PA3
NC
(1)
ICAP2
VDD
OCMP/PC0
PC1
PC2
PC3
NC
16
17181920212223242526272829303132
(1) V on EPROM/OTP only
PP
Figure 3. 56-Pin SDIP Package Pinout
(1)
TEST
NU
RESET
PA0
PA1
PA2
PA3
PA4
PA5
PA6
/VPP
DA0
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
DA1
DA2
DA3
DA4
NU
NU
NU
NU
9
V
10
11
12
13
14
15
16
17
18
19
20
21 (EI3)
22
SSA
PA7
OSCIN
V
DDA
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
AIN3/PB3
AIN2/PB2
AIN1/PB1
AIN0/PB0
ICAP1
PD7
OSCOUT
USBV
CC
USBDP
USBDM
USBGND
PC7/TDO
PC6/RDI
PC5/SDAI
PC4/SCLI
PC3
PD6
PC2
PC1
PC0/OCMP
PD5
PD4
PD3
PD2
23 (EI0)
24 (EI1)
25 (EI2)
26
(EI4) 34
33
32
31
V
DD
30
ICAP2
PD1
27
28
29
V
PD0
SS
(1) V on EPROM/OTP only
PP
Note: Several pins of the I/O ports assume software programmable alternate functions as shown in the
pin description.
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ST72671
PIN DESCRIPTION (Cont’d)
Table 1. ST72671N Pin Description
Pin n° Pin n°
Pin Name
Type
Description
Remarks
QFP64 SDIP56
1
NC
Not Connected
Port D6
2
22
23
24
25
26
27
28
29
30
31
32
33
34
35
PD6
PD5
PD4
PD3
PD2
PD1
PD0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
3
Port D5 or Interrupt falling edge detector input
External Interrupt: EI0
External Interrupt: EI1
External Interrupt: EI2
4
Port D4 or Interrupt falling edge detector input
5
Port D3 or Interrupt falling edge detector input
6
Port D2
7
Port D1
8
Port D0
9
V
Ground
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICAP2
Timer Input Capture 2 with 256 prescaler
Main power supply
Not for general purpose I/O
External Interrupt: EI4
V
S
DD
PC0/OCMP
PC1
I/O
I/O
I/O
I/O
Port C0 or Timer Output Compare
Port C1
PC2
Port C2 or Interrupt falling edge detector input
Port C3
PC3
NC
Not Connected
NC
Not Connected
2
36
37
38
39
40
41
42
PC4/SCLI
PC5/SDAI
PC6/RDI
PC7/TDO
USBGND
USBDM
USBDP
I/O
I/O
I/O
I/O
S
Port C4 or I C Serial Clock
2
Port C5 or I C Serial Data
Port C6 or SCI Receive Data Input
Port C7 or SCI Transmit Data Output
USB ground
I/O
I/O
USB bidirectional data
USB bidirectional data
USB power supply (output, 3.3V+/- 10%). This pin requires an external 4.7µF
decoupling capacitor to ground, and can be only connected to the external
USB pull-up resistor.
25
43
USBV
S
CC
26
27
28
29
30
31
32
33
34
35
44
45
46
47
48
49
OSCOUT
OSCIN
PA7
O
I
Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or
an external source to the on-chip oscillator.
I/O
I/O
I/O
I/O
Port A7
High Sink
High Sink
High Sink
High Sink
PA6
Port A6
PA5
Port A5
PA4
Port A4
NC
Not Connected
Not Connected
Port A3
NC
50
51
PA3
I/O
I/O
High Sink
High Sink
PA2
Port A2
6/101
6
ST72671
Pin n° Pin n°
QFP64 SDIP56
Pin Name
PA1
Type
Description
Remarks
36
37
52
53
I/O
I/O
Port A1
Port A0
High Sink
High Sink
PA0
Bidirectional. Active low. Top priority non mask- Can be used to reset exter-
38
39
54
55
RESET
NU
I/O
able interrupt.
nal peripherals.
Non User Pin. Must be connected to V
CC
Test mode pin. In the EPROM programming
mode, this pin acts as the programming voltage
This pin should be tied low
in user mode
40
56
TEST/V
S
PP
input V
PP.
41
42
43
44
45
46
47
48
49
50
51
1
2
3
4
5
6
7
8
9
DA0
DA1
DA2
DA3
DA4
NU
O
O
O
O
O
12-bit D/A (PWM output)
10-bit D/A (PWM output)
For analog controls, after
external filtering
10-bit D/A (PWM output)
10-bit D/A (PWM output)
10-bit D/A (PWM output)
Non User pin. Must be left unconnected
Non User pin. Must be left unconnected
Non User pin. Must be left unconnected
Non User pin. Must be left unconnected
Not Connected
NU
NU
NU
NC
NC
Not Connected
Must be connected exter-
52
53
10
11
V
S
S
Ground for analog peripheral (ADC)
SSA
nally to V
SS
Must be connected exter-
nally to V
V
Power Supply for analog peripheral (ADC)
DDA
DD
54
55
56
57
58
59
60
61
62
63
64
12
13
14
15
16
17
18
19
20
21
PB7/AIN7
PB6/AIN6
PB5/AIN5
PB4/AIN4
PB3/AIN3
PB2/AIN2
PB1/AIN1
PB0/AIN0
ICAP1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port B7 or ADC analog input 7
Port B6 or ADC analog input 6
Port B5 or ADC analog input 5
Port B4 or ADC analog input 4
Port B3 or ADC analog input 3
Port B2 or ADC analog input 2
Port B1 or ADC analog input 1
Port B0 or ADC analog input 0
Timer Input Capture 1
Not for general purpose I/O
External Interrupt: EI3
PD7
I/O
Port D7 or Interrupt rising edge detector input
Not Connected
NC
Note: S=Supply
7/101
7
ST72671
1.3 MEMORY MAP
Figure 4. Program Memory Map
0000h
0080h
Short Addressing
RAM (zero page)
HW Registers
(see Table 3)
00FFh
0100h
007Fh
0080h
256 Bytes Stack /
16-bit
512 Bytes RAM
Addressing RAM
01FFh
0200h
16-bit Addressing
RAM
1K Bytes RAM
Reserved
027Fh
0080h
047Fh
0480h
Short Addressing
RAM (zero page)
00FFh
0100h
256 Bytes Stack /
16-bit
Addressing RAM
7FFFh
8000h
01FFh
0200h
32K Bytes ROM, OTP
or EPROM
16-bit Addressing
RAM
C000h
047Fh
16K Bytes
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 2)
FFFFh
Table 2. Interrupt Vector Map
Vector Address
Description
Remarks
FFE0-FFE1h
FFE2-FFE3h
FFE4-FFE5h
FFE6-FFE7h
USB Interrupt Vector
SCI Interrupt Vector
Internal Interrupt
“
“
“
“
“
2
I C Interrupt Vector
Timer Overflow Interrupt Vector
FFE8-FFE9h
FFEA-FFEBh
FFEC-FFEDh
FFEE-FFEFh
FFF0-FFF1h
FFF2-FFF3h
FFF4-FFF5h
FFF6-FFF7h
FFF8-FFF9h
FFFA-FFFBh
FFFC-FFFDh
FFFE-FFFFh
Timer Output Compare Interrupt Vector
Timer Input Capture Interrupt Vector
Reserved
EI4 Interrupt Vector
External Interrupt
EI0 Interrupt Vector
“
“
“
“
EI1 Interrupt Vector
EI2 Interrupt Vector
EI3 Interrupt Vector
Reserved
USB End Suspend Interrupt Vector
TRAP Interrupt Vector
RESET Vector
Internal Interrupt
Software interrupt
CPU Interrupt
8/101
8
ST72671
MEMORY MAP (Cont’d)
Table 3. Hardware Register Memory Map
Address
Block
Port A
Register Label
Register Name
Port A Data Register
Reset Status
Remarks
0000h
0001h
PADR
PADDR
00h
00h
R/W
R/W
Port A Data Direction Register
0002h
0003h
PCDR
PCDDR
Port C Data Register
Port C Data Direction Register
00h
00h
R/W
R/W
Port C
Port D
0004h
0005h
PDDR
PDDDR
Port D Data Register
Port D Data Direction Register
00h
00h
R/W
R/W
0006h
0007h
0008h
PBDR
PBDDR
PBICFGR
Port B Data Register
Port B Data Direction Register
Port B Input Pull-Up Configuration Register 00h
00h
00h
R/W
R/W
R/W
Port B
0009h
MISCR
Miscellaneous Register
00h
R/W
000Ah
000Bh
ADCDR
ADCCSR
ADC Data Register
ADC Control Status register
00h
00h
Read only
R/W
ADC
000Ch
WDG
WDGCR
ITRFRE
Watchdog Control Register
7Fh
R/W
R/W
000Dh to
000Fh
Reserved Area (3 bytes)
00010h
ITR
Interrupt Register
00h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
TIMCR2
TIMCR1
TIMSR
TIMIC1HR
TIMIC1LR
TIMOC1HR
TIMOC1LR
TIMCHR
Timer Control Register 2
Timer Control Register 1
Timer Status Register
Timer Input Capture 1 High Register
Timer Input Capture 1 Low Register
Timer Output Compare 1 High Register
Timer Output Compare 1 Low Register
Timer Counter High Register
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read only
Read only
Read only
R/W
R/W
TIM
Read only
Read only
Read only
Read only
Read only
Read only
R/W
TIMCLR
Timer Counter Low Register
TIMACHR
TIMACLR
TIMIC2HR
TIMIC2LR
TIMOC2HR
TIMOC2LR
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Input Capture 2 High Register
Timer Input Capture 2 Low Register
Timer Output Compare 2 High Register
Timer Output Compare 2 Low Register
R/W
0020h
0021h
Reserved Area (2 bytes)
0022h
0023h
PWM0
BRM0
12-BIT PWM Register
12-BIT BRM Register
80h
C0h
R/W
R/W
0024h
0025h
0026h
0027h
0028h
0029h
PWM1
BRM21
PWM2
PWM3
BRM43
PWM4
80h
00h
80h
80h
00h
80h
R/W
R/W
R/W
R/W
R/W
R/W
DAC
10-BIT PWM / BRM Registers
Reserved Area (6 bytes)
002Ah to
002Fh
9/101
ST72671
Address
Block
Register Label
Register Name
SCI Status Register
Reset Status
Remarks
0030h
0031h
0032h
0033h
0034h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
C0h
xxh
00xx xxxx
xxh
00h
Read only
R/W
R/W
R/W
R/W
SCI Data Register
SCI
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
USBPIDR
USBDMAR
USBIDR
USBISTR
USBIMR
USBCTLR
USBDADDR
USBEP0RA
USBEP0RB
USBEP1RA
USBEP1RB
USB PID Register
xx00 0000
xxh
x0h
00h
00h
06h
00h
0xh
80h
Read only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
USB DMA address Register
USB Interrupt/DMA Register
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
USB Device Address Register
USB Endpoint 0 Register A
USB Endpoint 0 Register B
USB Endpoint 1 Register A
USB Endpoint 1 Register B
USB
0xh
0xh
R/W
R/W
0040h to
0042h
Reserved Area (3 bytes)
ICAP Configuration
Warning:
the ICAP1 and ICAP2 functions.
0043h
TIM
CONFIG
I2CDR
Write 0Ch in this register to use
08h
00h
R/W
R/W
0044h to
0058h
Reserved Area (21 bytes)
2
I C Data Register
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
Reserved
2
I2COAR
I2CCCR
I2CSR2
I2CSR1
I2CCR
I C (7 Bits) Slave Address Register
00h
00h
00h
00h
00h
R/W
R/W
Read only
Read only
R/W
2
2
C
I C Clock Control Register
I
2
I C Status Register 2
2
I C Status Register 1
2
I C Control Register
0060h to
007Fh
Reserved Area (32 bytes)
10/101
ST72671
2 CENTRAL PROCESSING UNIT
2.1 Introduction
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
2.2 Main Features
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ Enable executing 63 basic instructions
■
Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
addressing mode)
■
Two 8-bit index registers
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
■
16-bit stack pointer
■ 8 MHz CPU internal frequency
■ Low power modes
Program Counter (PC)
■
Maskable hardware interrupts
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
■ Non-maskable software interrupt
2.3 CPU Registers
The 6 CPU registers shown in Figure 5 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 5. CPU Registers
7
0
0
ACCUMULATOR
RESET VALUE = XXh
7
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
0
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
C
0
1
1
1
1
H I N Z
X 1
CONDITION CODE REGISTER
RESET VALUE =
8
1
0 1
15
7
0
STACKPOINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
11/101
ST72671
CENTRAL PROCESSING UNIT(Cont’d)
Condition Code Register (CC)
Read/Write
ter it and reset by the IRET instruction at the end of
the interrupt routine. If the I bit is cleared by soft-
ware in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Reset Value: 111x1010
7
0
1
1
1
H
I
N
Z
C
N Negative.
Bit 2 =
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
th
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
This bit is accessed by the JREQ and JRNE test
instructions.
I Interrupt mask.
bit 3 =
Bit 0 = C Carry/borrow.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-
12/101
ST72671
CENTRAL PROCESSING UNIT(Cont’d)
Stack Pointer (SP)
The least significant byte of the Stack Pointer can
be directly accessed by a LD instruction.
Read/Write
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
Reset Value: 01 FFh
15
8
1
0
0
7
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 6.
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (seeFigure 6).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
Since the stack is 256 bytes deep, the most signif-
icant byte is forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 6. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
13/101
ST72671
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 General Description
Note: The tables relate to the quartz crystal only
(not ceramic resonator).
The MCU accepts either a Crystal or Ceramic res-
onator, or an external clock signal to drive the in-
ternal oscillator. The internal clock (f ) is de-
CPU
3.1.2 External Clock
rived from the external oscillator frequency (f
)
OSC .
An external clock may be applied to the OSCIN in-
put with the OSCOUT pin not connected. The t
The external Oscillator clock is first divided by 3,
and an additional division factor of 2 can be ap-
plied if Slow Mode is selected by setting the SMS
bit in the Miscellaneous Register. This reduces the
OX-
specifications does not apply when using an
OV
external clock input. The equivalent specification
of the external clock source should be used in-
stead of t
(see Electrical Characteristics).
frequency of the f ; the clock signal is also rout-
CPU
OXOV
ed to the on-chip peripherals. The CPU clock sig-
nal consists of a square wave with a duty cycle of
50%.
Figure 7. Crystal/Ceramic Resonator
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz crystal resona-
tor in the frequency range specified for f . The
osc
circuit shown in Figure 7 is recommended when
using a crystal, and Table 4 lists the recommend-
ed capacitance and feedback resistance values.
The crystal and associated components should be
mounted as close as possible to the input pins in
order to minimize output distortion and start-up
stabilisation time.
OSCIN
OSCOUT
R
P
Use of an external CMOS oscillator is recom-
mended when crystals outside the specified fre-
quency ranges are to be used.
C
C
OSCIN
OSCOUT
Table 4. Recommended Crystal Values
24 Mhz
Unit
Ohms
pf
Figure 8. Clock Prescaler Block Diagram
R
70
22
22
25
47
47
20
56
56
SMAX
C
C
L1
L2
pf
%3
%2
CPUCLK
to CPU and
Peripherals
Legend:
C , C = Maximum total capacitance on pins
OSCIN
OSCOUT
L1
L2
OSCIN and OSCOUT (the value includes the ex-
ternal capacitance tied to the pin plus the parasitic
capacitance of the board and of the device).
R
P
R
= Maximum series parasitic resistance of
SMAX
C
C
OSCIN
OSCOUT
the quartz allowed.
14/101
ST72671
3.2 RESET
3.2.1 Introduction
after exiting Halt mode, a 4096 CPU Clock cycle
delay period is initiated in order to allow the oscil-
lator to stabilise and to ensure that recovery has
taken place from the Reset state.
There are three sources of Reset:
– RESET pin (external source)
– Power-On Reset (Internal source)
– WATCHDOG (Internal Source)
During the Reset cycle, the device Reset pin acts
as an output that is pulsed low. In its high state, an
internal pull-up resistor of about 300KΩ is con-
nected to the Reset pin. This resistor can be pulled
low by external circuitry to reset the device.
The Reset Service Routine vector is located at ad-
dress FFFEh-FFFFh.
3.2.2 External Reset
3.2.4 Power-on Reset
The RESET pin is both an input and an open-drain
output with integrated pull-up resistor. When one
of the internal Reset sources is active, the Reset
pin is driven low to reset the whole application.
This circuit detects the ramping up of V , and
DD
generates a pulse that is used to reset the applica-
tion (at approximately V = 2V).
DD
Power-On Reset is designed exclusively to cope
with power-up conditions, and should not be used
in order to attempt to detect a drop in the power
supply voltage.
3.2.3 Reset Operation
The duration of the Reset condition, which is also
reflected on the output pin, is fixed at 4096 internal
CPU Clock cycles. A Reset signal originating from
an external source must have a duration of at least
1.5 internal CPU Clock cycles in order to be recog-
nised. At the end of the Power-On Reset cycle, the
MCU may be held in the Reset condition by an Ex-
ternal Reset signal. The RESET pin may thus be
Caution: to re-initialize the Power-On Reset, the
power supply must fall below approximately 0.8V
(Vtn), prior to rising above 2V. If this condition is
not respected, on subsequent power-up the Reset
pulse may not be generated. An external Reset
pulse may be required to correctly reactivate the
circuit.
used to ensure V has risen to a point where the
DD
MCU can operate correctly before the user pro-
gram is run. Following a Power-On Reset event, or
Figure 9. Reset Block Diagram
INTERNAL
RESET
OSCILLATOR
SIGNAL
TO ST7
RESET
RESET
V
DD
300K
WATCHDOG RESET
15/101
ST72671
RESET (Cont’d)
Table 5. List of sections affected by RESET, WAIT and HALT (Refer to 3.6 for Wait and Halt Modes)
Section
RESET
WAIT
HALT
CPU clock running at 4 MHz
Timer Prescaler reset to zero
Timer Counter set to FFFCh
X
X
X
X
X
X
X
X
All Timer enable bits set to 0 (disabled)
Data Direction Registers set to 0 (as Inputs)
Set Stack Pointer to 01FFh
Force Internal Address Bus to restart vector FFFEh, FFFFh
Set Interrupt Mask Bit (I-Bit, CC) to 1 (Interrupt disable)
Set Interrupt Mask Bit (I-Bit, CC) to 0 (Interrupt enable)
Reset HALT latch
X
X
X
X
X
X
X
X
X
X
Reset WAIT latch
Disable Oscillator (for 4096 cycles)
Set Timer Clock to 0
X
X
Watchdog counter reset
Watchdog register reset
Port data registers reset
Other on-chip peripherals: registers reset
Figure 10. Reset Timing Diagram
t
DDR
V
DD
OSCIN
tOXOV
f
CPU
FFFF
FFFE
PC
RESET
4096 CPU
CLOCK
CYCLES
DELAY
WATCHDOG RESET
Note:
Refer to Electrical Characteristics for values of t
and tOXOV
DDR
16/101
ST72671
3.3 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in Table 6 and a non-maskable software in-
terrupt (TRAP). The Interrupt processing flowchart
is shown in Figure 11.
Halt low power mode (refer to the “Exit from HALT“
column in Table 6).
External Interrupts
External interrupt vectors can be loaded in the PC
register if the corresponding external interrupt oc-
curred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec-
tion).
The external interrupt polarity can be selected
through the Miscellaneous register or Interrupt
register (if available) (seeSection 3.4.5).
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared on entering the interrupt service routine.
– The PC, X, A and CC registers are saved onto
the stack.
More than one input pin can be connected to the
same interrupt request (depending on the device).
In this case, all inputs configured as interrupt are
logically ORed.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
Table 6 for vector addresses).
Warning: The type of polarity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the EI source. In case of an ORed source,
a low level on an I/O pin configured as input with
interrupt, masks the interrupt request even in case
of rising-edge polarity.
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Peripheral Interrupts
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
Priority management
– The I bit of the CC register is cleared.
By default, a servicing interrupt can not be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– The corresponding enable bit is set in the control
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
In the case several interrupts are simultaneously
pending, an hardware priority defines which one
will be serviced first (seeTable 6).
Clearing an interrupt request is done by:
– writing “0” to the corresponding bit in the status
register or
Non Maskable Software Interrupts
– an access to the status register while the flag is
set followed by a read or write of an associated
register.
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 11.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
Interrupts and Low power mode
All interrupts allow the processor to leave the Wait
low power mode. Only external and specific men-
tioned interrupts allow the processor to leave the
17/101
ST72671
INTERRUPTS (Cont’d)
Figure 11. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET
Y
N
INTERRUPT
FETCH NEXT INSTRUCTION
Y
N
STACK PC, X, A, CC
SET I BIT
EXECUTE INSTRUCTION
IRET
Y
LOAD PC FROM INTERRUPT VECTOR
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
VR01172D
18/101
ST72671
INTERRUPTS (Cont’d)
Table 6. Interrupt Mapping
Exit
from
HALT
Source
Block
Register
Label
Vector
Address
Priority
Order
Description
Flag
RESET
TRAP
USB
Reset
N/A
N/A
N/A
N/A
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
Highest
Priority
Software Interrupt
End suspend
USBISTR
ESUSP
yes
NOT USED
EI3
EI2
EI1
EI0
EI4
Ext. Interrupt PD7, rising edge
Ext. Interrupt PD3, falling edge
Ext. Interrupt PD4, falling edge
Ext. Interrupt PD5, falling edge
Ext. Interrupt PC2, falling edge
NOT USED
ITRFRE
ITRFRE
ITRFRE
ITRFRE
MISCR
EI3F
EI2F
EI1F
EI0F
EI4F
yes
Input Capture 1
ICF1
ICF2
FFEAh-FFEBh
Input Capture 2
TIMER
I2C
Output Compare 1
TIMSR
OCF1
OCF2
TOF
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
Output Compare 2
Timer Overflow
I2CSR1
I2CSR2
I2C Interface Interrupt
*
no
Transmit Buffer Empty
Transmit Complete
Receive Buffer Full
Idle Line Detect
Overrun
TDRE
TC
SCI
SCISR
RDRF
IDLE
OR
FFE2h-FFE3h
FFE0h-FFE1h
Lowest
Priority
USB
USB Interrupt
USBISTR
*
* Many flags can cause an interrupt: see peripheral interrupt status register description.
19/101
ST72671
3.4 POWER SAVING MODES
3.4.1 Introduction
Figure 12. WAIT Flow Chart
There are three Power Saving modes. Slow Mode
is selected by setting the relevant bits in the Mis-
cellaneous register. Wait and Halt modes may be
entered using the WFI and HALT instructions.
WFI INSTRUCTION
3.4.2 Slow Mode
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
In Slow mode, the oscillator frequency can be di-
vided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.
ON
OFF
CLEARED
Note: On reset, Slow mode is selected by default
(F /6).
OSC
N
RESET
3.4.3 Wait Mode
Wait mode places the MCU in a low power con-
sumption mode by stopping the CPU. All peripher-
als remain active. During Wait mode, the I bit (CC
Register) is cleared, so as to enable all interrupts.
All other registers and memory remain unchanged.
The MCU will remain in Wait mode until an Inter-
rupt or Reset occurs, whereupon the Program
Counter branches to the starting address of the In-
terrupt or Reset Service Routine.
N
Y
INTERRUPT
Y
OSCILLATOR
ON
ON
ON
SET
PERIPH. CLOCK
CPU CLOCK
I-BIT
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.
Refer to Figure 12 below.
IF RESET
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
20/101
ST72671
POWER SAVING MODES(Cont’d)
3.4.4 Halt Mode
Figure 13. HALT Flow Chart
The Halt mode is the MCU lowest power con-
sumption mode. The Halt mode is entered by exe-
cuting the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals. The Halt mode cannot be used when
the watchdog is enabled, if the HALT instruction is
executed while the watchdog system is enabled, a
watchdog reset is generated thus resetting the en-
tire MCU.
HALT INSTRUCTION
WDG
Y
WATCHDOG
RESET
ENABLED?
When entering Halt mode, the I bit in the CC Reg-
ister is cleared so as to enable External Interrupts.
If an interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of
an interrupt or a reset. Refer to the Interrupt Map-
ping Table. The oscillator is then turned on and a
stabilization time is provided before releasing CPU
operation. The stabilization time is 4096 CPU clock
cycles.
N
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
OFF
OFF
OFF
CLEARED
After the start up delay, the CPU continues oper-
ation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
N
RESET
N
EXTERNAL
Y
INTERRUPT*
Y
OSCILLATOR
ON
ON
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
SET
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
* or some specific interrupts
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
21/101
ST72671
3.4.5 Register Description
INTERRUPT REGISTER (ITRFRE)
MISCELLANEOUS REGISTER (MISCR)
Read/Write
Reset Value: 0000 0000 (00h)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
7
0
EI0F
EI1F
EI2F
EI3F
EI0ITE EI1ITE EI2ITE EI3ITE
EI4F EI4ITE SMS
-
-
-
-
POC0
Bit 7:5 = EI0F, EI1F, EI2F Falling Edge Detector
Flags.
Bit 7 = EI4F Falling Edge Detector Flag.
These bits are set by hardware when a falling
edge occurs on the pins assigned to EI0, EI1 or
EI2. They are cleared by software. When any of
these bits are set, an interrupt is generated if the
corresponding ITE bit =1 and the I bit in the CC
register = 0.
This bit is set by hardware when a falling edge oc-
curs on the pin assigned to EI4. An interrupt is
generated if EI4ITE=1 It is cleared by software.
0: No falling edge detected on EI4
1: Falling edge detected on EI4
0: No falling edge detected
1: Falling edge detected
EI4ITE EI4 Interrupt Enable.
Bit 6 =
This bit is set and cleared by software.
0: EI4 interrupt disabled
1: EI4 interrupt enabled
EI3F
Bit 4 =
Rising Edge Detector Flag.
This bit is set by hardware when a rising edge oc-
curs on the pin assigned to EI3. It is cleared by
software. When EI3F is set an interrupt is generat-
ed if EI3ITE=1 and the I bit in the CC register = 0.
0: No rising edge detected on EI3
Bit 5 = SMS Slow Mode Select.
This bit is set and cleared by software. It is used to
select the slow or fast mode CPU frequency.
1: Rising edge detected on EI3
0: f
1: f
= Oscillator frequency / 6 (slow mode)
= Oscillator frequency / 3 (normal mode)
CPU
CPU
Bit 3:0 = EI0ITE, EI1ITE, EI2ITE, EI3ITEInterrupt
Enable Bits.
These bits are set and cleared by software.
0: Interrupt disabled
1: Interrupt enabled
Bit 4: 1 = Reserved
POC0 PWM/BRM Output Configuration Bi.t
This bits is set and cleared by software. They se-
lect the PWM/BRM output configuration for pins
Bit 0 =
DA1-DA4.
0: Push-pull
1: Open drain
Note. DA0 is only Push-Pull Output.
22/101
ST72671
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
4.1.1 Introduction
output the correct value as soon as the port is con-
figured as an output.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
4.1.2.2 External Interrupt Generation
An I/O can be used to generate an external Inter-
rupt request to the CPU. External Interrupts are
enabled and their polarity selected using the OR,
MISC and ITRFRE registers (where available).
– analog signal input (ADC)
– alternate signal input/output for the on-chip pe-
ripherals.
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see Interrupts sec-
tion). If more than one input pin is selected simul-
taneously as interrupt source, this is logically
ORed. For this reason if one of the interrupt pins is
tied low, it masks the other ones.
– external interrupt generation
An I/O port is composed of up to 8 pins. Each pin
can be programmed independently as digital input
(with or without interrupt generation) or digital out-
put.
4.1.2.3 Output Mode
4.1.2 Functional Description
Each port is associated to 2 main registers:
– Data Register (DR)
The pin is configured in output mode by setting the
corresponding DDR register bit.
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
– Data Direction Register (DDR)
and some of them to an optional register:
– Option Register (OR)
Note: In this mode, the interrupt function is disa-
bled.
Each I/O pin may be programmed using the corre-
sponding register bits in DDR and OR registers: bit
X corresponding to pin X of the port. The same cor-
respondence is used for the DR register.
4.1.2.4 Digital Alternate Function
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
The following description takes into account the
OR register, however some specific ports do not
provide this register. The generic I/O block dia-
gram is shown onFigure 14.
4.1.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Note:
When the on-chip peripheral uses a pin as
input and output, this pin must be configured as an
input (DDR = 0).
Notes
:
Warning:
The alternate function must not be acti-
1. All the inputs are triggered by a CMOS Schmitt
trigger.
vated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious in-
terrupts.
2. When switching from input mode to output
mode, the DR register should be written first to
23/101
ST72671
I/O PORTS (Cont’d)
4.1.2.5 Analog Alternate Function
When the pin is used as an ADC input the I/O must
be configured as input, floating. The analog multi-
plexer (controlled by the ADC registers) switches
the analog voltage present on the selected pin to
the common analog rail which is connected to the
ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Warning
: The analog input voltage level must be
within the limits stated in the Absolute Maximum
Ratings.
24/101
ST72671
I/O PORTS (Cont’d)
Figure 14. I/O Block Diagram
ALTERNATE ENABLE
1
V
ALTERNATE
OUTPUT
DD
M
U
X
P-BUFFER
0
(S
T
B
)
EE ABLE ELOW
DR
LATCH
ALTERNATE
ENABLE
PULL-UP (S
T
)
EE ABLE BELOW
PULL-UP
CONDITION
DDR
LATCH
PAD
OR
ANALOG ENABLE
(ADC)
LATCH
(S
T
)
EE ABLE BELOW
ANALOG
SWITCH
OR SEL
(S
N
)
EE OTE BELOW
DDR SEL
N-BUFFER
ALTERNATE
ENABLE
1
0
DR SEL
M
U
X
GND
ALTERNATE INPUT
OR EXTERNAL INTERRUPT REQUEST
CMOS
SCHMITT TRIGGER
Table 7. Port Mode Configuration
Configuration Mode
Floating
Pull-up
P-buffer
0
0
Pull-up
1
0
Push-pull
0
1
True Open Drain
Open Drain (logic level)
not present
not present
not present
0
Legend:
Notes:
– No OR Register on some ports (see register map).
– ADC Switch on ports with analog alternate functions.
0 -
1 -
present, not activated
present and activated
25/101
ST72671
I/O PORTS (Cont’d)
4.1.2.6 Device Specific Configurations
Table 8. Port Configuration
Input (DDR=0)
Output (DDR=1)
OR=0 OR=1
Port
Pin name
OR=0*
OR=1
Port A
PA0:PA7
floating
true open drain, high sink capability
floating
Port B
Port C
PB0:PB7
pull-up
(for analog
conversion only)
push-pull
PC0:PC1
PC2:PC5
PC6
pull-up
push-pull
open drain
floating
pull-up
pull-up
pull-up
true open drain, high sink capability
push-pull
PC7
Port D
PD0:PD7
push-pull
*Reset state.
Note:
The DA1-DA4 output pins are configurable as push pull or open drain using the POC0 Bit in the Mis-
cellaneous Register.
26/101
ST72671
I/O PORTS (Cont’d)
4.1.3 Register Description
DATA REGISTERS (DR)
DATA DIRECTION REGISTERS (DDR)
Read/Write
Reset Value: 0000 0000 (00h)
Read/Write
Reset Value: 0000 0000 (00h) (input mode)
7
0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
DD7
DD6
DD5
DD4
DD3 DD2
DD1
DD0
Bit 7:0 = DD[7:0] Data Direction Register 8 bits.
D[7:0] Data Register 8 bits.
Bit 7:0 =
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
The behaviour of the DR register depends on the
selected input/output configuration. Writing the DR
register is always taken in account even if the pin
is configured as an input. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD[7:0] Port B Digital/Analog Input Con-
figuration Bits.
Bit 7:0 =
0: The pull-up is connected and pin configured as
digital input (reset condition)
1: The pull-up is disconnected and the pin is con-
figured as analog input.
27/101
ST72671
I/O PORTS (Cont’d)
Table 9. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PADR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
Reset Value
PADDR
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0
Reset Value
PCDR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Reset Value
PCDDR
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0
Reset Value
PDDR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Reset Value
PDDDR
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0
Reset Value
PBDR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Reset Value
PBDDR
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0
Reset Value
PBOR
AD7
0
AD6
0
AD5
0
AD4
0
AD3
0
AD2
0
AD1
0
AD0
0
Reset Value
28/101
ST72671
4.2 WATCHDOG TIMER (WDG)
4.2.1 Introduction
4.2.2 Main Features
■ Programmable timer (64 increments of 49,152
CPU cycles)
■ Programmable reset
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Figure 15. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5 T0
WDGA T6
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷ 49152
29/101
ST72671
WATCHDOG TIMER(Cont’d)
4.2.3 Functional Description
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
The counter value stored in the CR register (bits
T6:T0), is decremented every 49,152 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated, the HALT instruction
will generate a Reset.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 become cleared), it initiates a
reset cycle pulling low the reset pin for typically
500ns.
4.2.4 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to stored in the
CR register must be between FFh and C0h (see
Table 10):
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
WDGA
Bit 7=
Activation bit.
– The WDGA bit is set (watchdog enabled)
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
– The T6 bit is set to prevent generating an imme-
diate reset
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
T[6:0] 7-bit timer (MSB to LSB).
Bit 6:0 =
Table 10. Watchdog Timing (f
= 8 MHz)
CPU
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
become cleared) if WDGA=1.
CR Register
initial value
WDG timeout period
(ms)
Max
Min
FFh
C0h
393.216
6.144
Notes:
Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
Table 11. WDG Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
0C
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
CR
Reset Value
30/101
ST72671
4.3 16-BIT TIMER
4.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
4.3.3 Functional Description
4.3.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The principal block of the Programmable Timer is
a 16-bit free running increasing counter and its as-
sociated 16-bit registers:
Counter Registers
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
Alternate Counter Registers
4.3.2 Main Features
– Alternate Counter High Register (ACHR) is the
most significantbyte (MSB).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
■ Programmable prescaler: fCPU divided by 2, 4or8.
■ Overflow status flag and maskable interrupt
■
External clock input (must be at least 4 times
slower than theCPUclock speed) withthe choice
of active edge
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note at the end of paragraph titled 16-bit
read sequence).
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
– 1 dedicated maskable interrupt
■
Input capture functions with
The timer clock depends on the clock control bits
of the CR2 register, as illustrated inTable 12. The
value in the counter register repeats every
131.072, 262.144 or 524.288 internal processor
clock cycles depending on the CC1 and CC0 bits.
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■
Pulse width modulation mode (PWM)
■ One pulse mode
■ 5 alternate functions on I/O ports*
The Block Diagram is shown inFigure 16.
*Note:
Some external pins are not available on all
devices. Refer to the device pin out description.
When reading an input signal which is not availa-
ble on an external pin, the value will always be ‘1’.
31/101
ST72671
16-BIT TIMER (Cont’d)
Figure 16. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
h
h
h
h
EXEDG
g
w
g
w
g
w
g
low
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
OUTPUT
COMPARE
REGISTER
1
16 BIT
FREE RUNNING
1/2
COMPARE
REGISTER
2
1/4
1/8
COUNTER
1
2
COUNTER
ALTERNATE
REGISTER
16
16
16
CC1 CC0
TIMER INTERNAL BUS
16
16
OVERFLOW
DETECT
EXTCLK
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
ICAP2
CIRCUIT
6
EDGE DETECT
CIRCUIT2
OCMP1
OCMP2
LATCH1
LATCH2
ICF1OCF1TOF ICF2OCF2 0
0
0
SR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
CR1
CR2
TIMER INTERRUPT
32/101
ST72671
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is
set.
Beginning of the sequence
2. An access (read or write) to the CLR register.
Read MSB
At t0
LSB is buffered
Notes: The TOF bit is not cleared by accesses to
ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free
running counter at random times (for example, to
measure elapsed time) without the risk of clearing
the TOF bit erroneously.
Other
instructions
Returns the buffered
LSB value at t0
Read LSB
At t0 +∆t
The timer is not affected by WAIT mode.
Sequence completed
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
The user must read the MSB first, then the LSB
value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MSB several times.
4.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LSB of the count value at the time of the
read.
The status of the EXEDG bit determines the type
of level transition on the external clock pin EXT-
CLK that will trigger the free running counter.
An overflow occurs when the counter rolls over
from FFFFh to 0000h then:
The counter is synchronised with the falling edge
of the internal CPU clock.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
At least four falling edges of the CPU clock must
occur between two consecutive active edges of
the external clock; thus the external clock frequen-
cy must be less than a quarter of the CPU clock
frequency.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
33/101
ST72671
16-BIT TIMER (Cont’d)
Figure 17. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
OVERFLOW FLAG TOF
Figure 18. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
OVERFLOW FLAG TOF
Figure 19. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
OVERFLOW FLAG TOF
34/101
ST72671
16-BIT TIMER (Cont’d)
4.3.3.3 Input Capture
When an input capture occurs:
– ICFi bit is set.
In this section, the index,i, may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 21).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
ICiHR
LS Byte
ICiLR
ICiR
ICi Rregister is a read-only register.
Clearing the Input Capture interrupt request is
done in two steps:
The active transition is software programmable
through theIEDGi bit of the Control Register (CRi).
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Timing resolution is one count of the free running
counter: (f
Procedure
/(CC1.CC0)).
CPU
Note: After reading the ICiHR register, transfer of
input capture data is inhibited until the ICiLR regis-
ter is also read.
To use the input capture function select the follow-
ing in the CR2 register:
The ICiR register always contains the free running
counter value which corresponds to the most re-
cent input capture.
– Select the timer clock (CC1-CC0) (see Table
12).
During HALT mode, if at least one valid input cap-
ture edge occurs on the ICAPi pin, the input cap-
ture detection circuitry is armed. This does not set
any timer flags, and does not “wake-up” the MCU.
If the MCU is awoken by an interrupt, the input
capture flag will become active, and data corre-
sponding to the first valid edge during HALT mode
will be present.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
35/101
ST72671
16-BIT TIMER (Cont’d)
Figure 20. Input Capture Block Diagram
ICAP1
CR1
(Control Register 1)
IEDG1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
ICAP2
(Status Register) SR
ICF1
ICF2
0
0
0
IC1R
IC2R
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
CC0 IEDG2
CC1
Figure 21. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: Active edge is rising edge.
36/101
ST72671
16-BIT TIMER (Cont’d)
4.3.3.4 Output Compare
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
In this section, the index,i, may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
Clearing the output compare interrupt request is
done by:
3. Reading the SR register while the OCFi bit is
set.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
4. An access (read or write) to the OCiLR register.
– Assigns pins with a programmable value if the
OCIE bit is set
Note: After a processor write cycle to the OCiHR
register, the output compare function is inhibited
until the OCiLR register is also written.
– Sets a flag in the status register
– Generates an interrupt if enabled
If the OCiE bit is not set, the OCMPi pin is a gen-
eral I/O port and the OLVLi bit will not appear
when match is found but an interrupt could be gen-
erated if the OCIE bit is set.
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
i
The value in the 16-bit OCR register and the OLVi
MS Byte
OCiHR
LS Byte
OCiLR
bit should be changed after each successful com-
parison in order to control an output waveform or
establish a new elapsed timeout.
OCiR
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCR value to 8000h.
i
The OCR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
i
Timing resolution is one count of the free running
∆t f
f
counter: (
).
* CPU
CPU/(CC1.CC0)
∆
OCiR =
t
Procedure
PRESC
To use the output compare function, select the fol-
lowing in the CR2 register:
Where:
∆t
= Desired output compare period (in
seconds)
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output comparei
function.
f
= Internal clock frequency
CPU
t
= Timer clock prescaler (CC1-CC0 bits,
see Table 12)
PRESC
– Select the timer clock (CC1-CC0) (see Table
12).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCR register:
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
i
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When match is found:
– OCFi bit is set.
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset and stays low
until valid compares change it to a high level).
37/101
ST72671
16-BIT TIMER (Cont’d)
Figure 22. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
CR2
(Control Register 2)
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
OLVL2
OLVL1
OCMP1
OCMP2
Latch
2
16-bit
OC1R
16-bit
OC2R
OCF1
OCF2
0
0
0
SR
(Status Register)
Figure 23. Output Compare Timing Diagram, Internal Clock Divided by 2
INTERNAL CPU CLOCK
TIMER CLOCK
FFFC FFFD FFFD FFFE
CPU writes FFFF
0000
FFFF
FFFF
COUNTER
OUTPUT COMPARE REGISTER
COMPARE REGISTER LATCH
OCFi AND OCMPi PIN (OLVLi=1)
38/101
ST72671
16-BIT TIMER (Cont’d)
4.3.3.5 Forced Compare Mode
In this section i may represent 1 or 2.
The following bits of the CR1 register are used:
– Select the timer clock CC1-CC0 (see Table
12).
One pulse mode cycle
Counter is
FOLV2 FOLV1 OLVL2
OLVL1
When
initialized
to FFFCh
event occurs
on ICAP1
When the FOLVi bit is set, the OLVLi bit is copied
to the OCMPi pin. The OLVi bit has to be toggled
in order totoggle the OCMPi pin when it is enabled
(OCiE bit=1).
OCMP1 = OLVL2
OCMP1 = OLVL1
The OCFi bit is not set, and thus no interrupt re-
quest is generated.
When
Counter
= OC1R
4.3.3.6 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin. When the value of the counter
is equal to the value of the contents of the OC1R
register, the OLVL1 bit is output on the OCMP1
pin, (See Figure 24).
Procedure
To use one pulse mode:
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in Section 4.3.3.7).
2. Select the following in the the CR1 register:
Note: The OCF1 bit cannot be set by hardware in
one pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
The ICF1 bit is set when an active edge occurs
and can generate an interrupt if the ICIE bit is set.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
– Set the OPM bit.
Figure 24. One Pulse Mode Timing
....
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note:
IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
39/101
ST72671
16-BIT TIMER (Cont’d)
4.3.3.7 Pulse Width Modulation Mode
Where:
– t = Desired output compare period (seconds)
– f = Internal clock frequency (see Miscella-
Pulse Width Modulation mode enables the gener-
ation of a signal with a frequency and pulse length
determined by the value of the OC1R and OC2R
registers.
CPU
neous register)
– t
= Timer clock prescaler (CC1-CC0
bits , see Table 12)
PRESC
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register.
The Output Compare 2 event causes the counter
to be initialized to FFFCh (SeeFigure 25).
Procedure
To use pulse width modulation mode:
Pulse Width Modulation cycle
When
1. Load the OC2R register with the value corre-
sponding to the period of the signal.
2. Load the OC1R register with the value corre-
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
Counter
= OC1R
OCMP1 = OLVL1
3. Select the following in the CR1 register:
OCMP1 = OLVL2
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
When
Counter
= OC2R
Counter is reset
to FFFCh
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
ICF1 bit is set
4. Select the following in the CR2 register:
Note:
After a write instruction to the OCiHR regis-
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
ter, the output compare function is inhibited until
the OCiLR register is also written.
– Set the PWM bit.
The ICF1 bit is set by hardware when the counter
reaches the OC2R value and can produce a timer
interrupt if the ICIE bit is set and the I bit is cleared.
– Select the timer clock (CC1-CC0) (seeTable
12).
If OLVL1=1 and OLVL2=0 the length of the pulse
is the difference between the OC2R and OC1R
registers.
Therefore the Input Capture 1 function is inhibited
but the Input Capture 2 is available.
The OCF1 and OCF2 bits cannot be set by hard-
ware in PWM mode therefore the Output Compare
interrupt is inhibited.
i
The OCR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
t * f
CPU
- 5
OCiR Value =
t
PRESC
Figure 25. Pulse Width Modulation Mode Timing
34E2 FFFC FFFD FFFE
COUNTER
2ED0 2ED1 2ED2
34E2 FFFC
OLVL2
OLVL1
OLVL2
OCMP1
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
40/101
ST72671
16-BIT TIMER (Cont’d)
4.3.4 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
FOLV1
Forced Output Compare 1.
Bit 3 =
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin.
Reset Value: 0000 0000 (00h)
7
0
Bit 2 = OLVL2 Output Level 2.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
IEDG1 Input Edge 1.
Bit 1 =
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
OCIE
Bit 6 =
Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
41/101
ST72671
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 3, 2 = CC1-CC0 Clock Control.
Reset Value: 0000 0000 (00h)
The value of the timer clock depends on these bits:
7
0
Table 12. Clock Control Bits
Timer Clock
CC1
CC0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
fCPU / 4
0
0
1
0
1
0
/ 2
fCPU
fCPU
OC1E
Bit 7 =
Output Compare 1 Enable.
/ 8
0: Output Compare 1 function is enabled, but the
External Clock (where
available)
OCMP1 pin is a general I/O.
1
1
1: Output Compare 1 function is enabled, the
OCMP1 pin is dedicated to the Output Compare
1 capability of the timer.
IEDG2 Input Edge 2.
Bit 1 =
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
OC2E
Bit 6 =
Output Compare 2 Enable.
0: Output Compare 2 function is enabled, but the
OCMP2 pin is a general I/O.
1: A rising edge triggers the capture.
1: Output Compare 2 function is enabled, the
OCMP2 pin is dedicated to the Output Compare
2 capability of the timer.
EXEDG
Bit 0 =
External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
free running counter.
0: A falling edge triggers the free running counter.
1: A rising edge triggers the free running counter.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
42/101
ST72671
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Bit 2-0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: Undefined
The three least significant bits are not used.
7
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
0
0
ICF1 OCF1 TOF ICF2 OCF2
0
0
7
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
MSB
LSB
1: An input capture has occurred or the counter
has reached the OC2R value in PWM mode. To
clear this bit, first read the SR register, then read
or write the low byte of the IC1R (IC1LR) regis-
ter.
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
7
0
MSB
LSB
TOF
Bit 5 =
Timer Overflow.
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
0: No timer overflow (reset value).
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
Note:
Reading or writing the ACLR register does
not clear TOF.
7
0
Bit 4 = ICF2 Input Capture Flag 2.
MSB
LSB
0: No input capture (reset value).
1: An input capture has occurred.To clear this bit,
first read the SR register, then read or write the
low byte of the IC2R (IC2LR) register.
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
43/101
ST72671
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
44/101
ST72671
Table 13. 16-Bit Timer Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
CR2
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
OC1E
ICIE
ICF1
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
OC2E
OCIE
OCF1
OPM
TOIE
TOF
PWM
FOLV2
ICF2
CC1
FOLV1
OCF2
CC0
OLVL2
0
IEDG2
IEDG1
0
EXEDG
OLVL1
0
CR1
SR
IC1HR
IC1LR
OC1HR
OC1LR
CHR
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
CLR
ACHR
ACLR
IC2HR
IC2LR
OC2HR
OC2LR
CONFIG
Reset Value
-
0
-
0
-
0
-
0
-
1
ICAP
0
-
0
-
0
43
Warning: Write 0Ch in the CONFIG register to
use the ICAP1 and ICAP2 pins (set bits 3 and 2).
45/101
ST72671
4.4 USB INTERFACE (USB)
4.4.1 Introduction
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http//:www.usb.org.
The USB Interface implements a low-speed func-
tion interface between the USB and the ST7 mi-
crocontroller. It is a highly integrated circuit which
includes the transceiver, 3.3 voltage regulator, SIE
and DMA. No external components are needed
apart from the external pull-up on USBDM for low
speed recognition by the USB host.
Serial Interface Engine
The SIE (Serial Interface Engine) interfaces with
the USB, via the transceiver.
The SIE processes tokens, handles data transmis-
sion/reception, and handshaking as required by
the USB standard. It also performs frame format-
ting, including CRC generation and checking.
4.4.2 Main Features
■ USB Specification Version 1.0 Compliant
■
Supports Low-Speed USB Protocol
Endpoints
■ Two or Three Endpoints (including default one)
depending on the device (see device feature list
and register map)
The Endpoint registers indicate if the microcontrol-
ler is ready to transmit/receive, and how many
bytes need to be transmitted.
■
CRC
generation/checking,
NRZI
DMA
encoding/decoding and bit-stuffing
■ USB Suspend/Resume operations
■ DMA Data transfers
When a token for a valid Endpoint is recognized by
the USB interface, the related data transfer takes
place, using DMA. At the end of the transaction, an
interrupt is generated.
■
On-Chip 3.3V Regulator
■ On-Chip USB Transceiver
Interrupts
4.4.3 Functional Description
By reading the Interrupt Status register, applica-
tion software can know which USB event has oc-
curred.
The block diagram inFigure 26, gives an overview
of the USB interface hardware.
Figure 26. USB block diagram
6 MHz
ENDPOINT
CPU
REGISTERS
USBDM
Address,
Transceiver
SIE
DMA
USBDP
data busses
and interrupts
3.3V
INTERRUPT
REGISTERS
USBVCC
USBGND
Voltage
Regulator
MEMORY
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ST72671
USB INTERFACE(Cont’d)
4.4.4 Register Description
DMA ADDRESS REGISTER (DMAR)
Read / Write
INTERRUPT/DMA REGISTER (IDR)
Read / Write
Reset Value: xxxx 0000(x0h)
Reset Value: Undefined
7
0
7
0
DA7
DA6
EP1
EP0 CNT3 CNT2 CNT1 CNT0
DA15 DA14 DA13 DA12 DA11 DA10 DA9
DA8
DA[7:6]
Bits 7:6 =
DMA address bits 7-6.
Software must reset these bits. See the descrip-
Bits 7:0=DA[15:8] DMA address bits 15-8.
tion of the DMAR register andFigure 27.
Software must write the start address of the DMA
memory area whose most significant bits are given
by DA15-DA6. The remaining 6 address bits are
set by hardware. See the description of the IDR
register and Figure 27.
EP[1:0]
Bits 5:4 =
Endpoint number (read-only).
These bits identify the endpoint which required at-
tention.
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2
When a CTR interrupt occurs (see register ISTR)
the software should read the EP bits to identify the
endpoint which has sent or received a packet.
CNT[3:0]
Bits 3:0 =
Byte count (read only).
This field shows how many data bytes have been
received during the last data reception.
Note: Not valid for data transmission.
Figure 27. DMA buffers
101111
Endpoint 2 TX
Endpoint 2 RX
101000
100111
100000
011111
Endpoint 1 TX
Endpoint 1 RX
011000
010111
010000
001111
Endpoint 0 TX
Endpoint 0 RX
001000
000111
DA15-6,000000
000000
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USB INTERFACE(Cont’d)
PID REGISTER (PIDR)
Read only
0: No over/underrun detected
1: Over/underrun detected
Reset Value: xx00 0000 (x0h)
Bit 5 = CTR Correct Transfer. This bit is set by
hardware when a correct transfer operation is per-
formed. The type of transfer can be determined by
looking at bits TP3-TP2 in register PIDR. The End-
point on which the transfer was made is identified
by bits EP1-EP0 in register IDR.
7
0
0
TP3
TP2
0
0
0
0
0
Bits 7:6 =TP3-TP2 Token PID bits 3 & 2.
USB token PIDs are encoded in four bits.
0: No Correct Transfer detected
1: Correct Transfer detected
TP3-TP2
correspond to the variable token PID bits 3 & 2.
Note: PID bits 1 & 0 have a fixed value of 01.
When a CTR interrupt occurs (see register ISTR)
the software should read the TP3 and TP2 bits to
retrieve the PID name of the token received.
The USB standard defines TP bits as:
Note: A transfer where the device sent a NAK or
STALL handshake is considered not correct (the
host only sends ACK handshakes). A transfer is
considered correct if there are no errors in the PID
and CRC fields, if the DATA0/DATA1 PID is sent
as expected, if there were no data overruns, bit
stuffing or framing errors.
TP3
0
TP2
PID Name
OUT
0
0
1
1
IN
Bit 4 = ERR Error.
1
SETUP
This bit is set by hardware whenever one of the er-
rors listed below has occurred:
0: No error detected
Bit 5:0 Reserved. Forced by hardware to 0.
1: Timeout, CRC, bit stuffing or nonstandard
framing error detected
INTERRUPT STATUS REGISTER (ISTR)
Read / Write
Bit 3 = IOVR Interrupt overrun.
Reset Value: 0000 0000 (00h)
This bit is set when hardware tries to set ERR, or
SOF before they have been cleared by software.
0: No overrun detected
7
0
1: Overrun detected
SUSP DOVR CTR ERR IOVR ESUSP RESET SOF
ESUSP End suspend mode.
Bit 2 =
When an interrupt occurs these bits are set by
hardware. Software must read them to determine
the interrupt type and clear them after servicing.
This bit is set by hardware when, during suspend
mode, activity is detected that wakes the USB in-
terface up from suspend mode.
Note:
These bits cannot be set by software.
This interrupt is serviced by a specific vector, in or-
der to wake up the ST7 from HALT mode.
0: No End Suspend detected
SUSP
Bit 7 =
Suspend mode request.
This bit is set by hardware when no SOFs have
been received for 3 ms, indicating a suspend
mode request from the USB bus. The suspend re-
quest check is active immediately after each USB
reset event and its disabled by hardware when
suspend mode is forced (FSUSP bit of CTLR reg-
ister) until the end of resume sequence.
1: End Suspend detected
Bit 1 = RESET USB reset.
This bit is set by hardware when the USB reset se-
quence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
Note: The DADDR, EP0RA, EP0RB, EP1RA,
EP1RB, EP2RA and EP2RB registers are reset by
a USB reset.
Bit 6 = DOVR DMA over/underrun.
This bit is set by hardware if the ST7 processor
can’t answer a DMA request in time.
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USB INTERFACE(Cont’d)
Bit 0 = SOF Start of frame.
This bit is set by hardware when a low-speed SOF
indication (keep-alive strobe) is seen on the USB
bus. It is also issued at the end of a resume se-
quence.
Bit 2 = PDWN Power down.
This bit is set by software to turn off the 3.3V on-
chip voltage regulator that supplies the external
pull-up resistor and the transceiver.
0: Voltage regulator on
0: No SOF signal detected
1: SOF signal detected
1: Voltage regulator off
Note: After turning on the voltage regulator, soft-
ware should allow at least 3 µs for stabilisation of
the power supply before using the USB interface.
Note: To avoid spurious clearing of some bits, it is
recommended to clear them using a load instruc-
tion where all bits which must not be altered are
set, and all bits to be cleared are reset. Avoid read-
modify-write instructions like AND , XOR..
Bit 1 = FSUSP Force suspend mode.
This bit is set by software to enter Suspend mode.
The ST7 should also be halted allowing at least
600 ns before issuing the HALT instruction.
0: Suspend mode inactive
INTERRUPT MASK REGISTER (IMR)
Read / Write
1: Suspend mode active
Reset Value: 0000 0000 (00h)
When the hardware detects USB activity, it resets
this bit (it can also be reset by software).
7
0
SUS
PM
DOV
RM
CTR
M
ERR IOVR ESU
SPM
RES
ETM
SOF
M
FRES
Bit 0 =
Force reset.
M
M
This bit is set by software to force a reset of the
USB interface, just as if a RESET sequence came
from the USB.
0: Reset not forced
1: USB interface reset forced.
Bits 7:0 = These bits are mask bits for all interrupt
condition bits included in the ISTR. Whenever one
of the IMR bits is set, if the corresponding ISTR bit
is set, and the I bit in the CC register is cleared, an
interrupt request is generated. For an explanation
of each bit, please refer to the corresponding bit
description in ISTR.
The USB is held in RESET state until software
clears this bit, at which point a “USB-RESET” in-
terrupt will be generated if enabled.
DEVICE ADDRESS REGISTER (DADDR)
Read / Write
CONTROL REGISTER (CTLR)
Read / Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0110 (06h)
7
0
0
7
0
0
ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
0
0
0
RESUME
PDWN FSUSP FRES
Bit 7 = Reserved. Forced by hardware to 0.
Bits 7:4 = Reserved. Forced by hardware to 0.
Bits 6:0 = ADD[6:0] Device address, 7 bits.
Bit 3 = RESUME Resume.
Software must write into this register the address
sent by the host during enumeration.
This bit is set by software to wake-up the Host
when the ST7 is in suspend mode.
0: Resume signal not forced
Note: This register is also reset when a USB reset
is received from the USB bus or forced through bit
FRES in the CTLR register.
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate
delay.
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USB INTERFACE(Cont’d)
ENDPOINT n REGISTER A (EPnRA)
Read / Write
hardware, at the receipt of a relevant PID. They
can be also written by software.
Bits 5:4 = STAT_TX[1:0] Status bits, for transmis-
sion transfers.
Reset Value: 0000 xxxx (0xh)
These bits contain the information about the end-
point status, which are listed below:
7
0
ST_
OUT
DTOG
_TX
STAT STAT TBC TBC TBC TBC
_TX1 _TX0
STAT_TX1 STAT_TX0 Meaning
3
2
1
0
DISABLED:
transmission
transfers cannot be executed.
STALL
0
0
: the endpoint is stalled
These registers (EP0RA, EP1RA and EP2RA) are
used for controlling data transmission. They are
also reset by the USB bus reset.
0
1
and all transmission requests
result in a STALL handshake.
NAK: the endpoint is naked
and all transmission requests
result in a NAK handshake.
Note
: Endpoint 2 and the EP2RA register are not
available on some devices (see device feature list
and register map).
1
1
0
1
VALID: this endpoint is ena-
bled for transmission.
ST_OUT
Bit 7 =
Status out.
These bits are written by software. Hardware sets
the STAT_TX bits to NAK when a correct transfer
has occurred (CTR=1) related to a IN or SETUP
transaction addressed to this endpoint; this allows
the software to prepare the next set of data to be
transmitted.
This bit is set by software to indicate that a status
out packet is expected: in this case, all nonzero
OUT data transfers on the endpoint are STALLed
instead of being ACKed. When ST_OUT is reset,
OUT transactions can have any number of bytes,
as needed.
Bits 3:0 = TBC[3:0] Transmit byte count for End-
point n.
DTOG_TX
transfers.
Bit 6 =
Data Toggle, for transmission
Before transmission, after filling the transmit buff-
er, software must write in the TBC field the trans-
mit packet size expressed in bytes (in the range 0-
8).
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware at the re-
ception of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from the USB host. DTOG_TX and also
DTOG_RX (see EPnRB) are normally updated by
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ST72671
USB INTERFACE(Cont’d)
ENDPOINT n REGISTER B (EPnRB)
Read / Write
NAK: the endpoint is na-
ked and all reception re-
quests result in a NAK
handshake.
1
1
0
1
Reset Value: 0000 xxxx (0xh)
VALID
: this endpoint is
7
0
enabled for reception.
DTOG
_RX
STAT
_RX1
STAT
_RX0
CTRL
EA3 EA2 EA1 EA0
These bits are written by software. Hardware sets
the STAT_RX bits to NAK when a correct transfer
has occurred (CTR=1) related to an OUT or SET-
UP transaction addressed to this endpoint, so the
software has the time to elaborate the received
data before acknowledging a new transaction.
These registers (EP1RB and EP2RB) are used for
controlling data reception on Endpoints 1 and 2.
They are also reset by the USB bus reset.
Note
: Endpoint 2 and the EP2RB register are not
available on some devices (see device feature list
and register map).
EA[3:0]
Bits 3:0 =
Endpoint address.
Software must write in this field the 4-bit address
used to identify the transactions directed to this
endpoint. Usually EP1RB contains “0001” and
EP2RB contains “0010”.
CTRL
This bit should be 0.
Bit 7 =
Control.
Note:
If this bit is 1, the Endpoint is a control end-
point. (Endpoint 0 is always a control Endpoint, but
it is possible to have more than one control End-
point).
ENDPOINT 0 REGISTER B (EP0RB)
Read / Write
Reset Value: 1000 0000 (80h)
Bit 6 = DTOG_RXData toggle, for reception trans-
fers.
7
1
0
0
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a control transfer (SETUP trans-
actions start always with DATA0 PID). The receiv-
er toggles DTOG_RX only if it receives a correct
data packet and the packet’s data PID matches
the receiver sequence bit.
DTOG STAT STAT
RX RX1 RX0
0
0
0
This register is used for controlling data reception
on Endpoint 0. It is also reset by the USB bus re-
set.
Bit 7 = Forced by hardware to 1.
STAT_RX [1:0]
transfers.
Bit 5:4 =
Status bits, for reception
These bits contain the information about the end-
point status, which are listed below:
Bit 6:4 = Refer to the EPnRB register for a descrip-
tion of these bits.
STAT_RX1 STAT_RX0 Meaning
DISABLED
: reception
transfers cannot be exe-
cuted.
Bit 3:0 = Forced by hardware to 0.
0
0
0
1
STALL: the endpoint is
stalled and all reception
requests result in
STALL handshake.
a
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USB INTERFACE(Cont’d)
4.4.5 Programming Considerations
When the operation is completed, they can be ac-
cessed again to enable a new operation.
In the following, the interaction between the USB
interface and the application program is described.
Apart from system reset, action is always initiated
by the USB interface, driven by one of the USB
events associated with the Interrupt Status Regis-
ter (ISTR) bits.
4.4.5.4 Interrupt Handling
Start of Frame (SOF)
The interrupt service routine may monitor the SOF
events to have a 1 ms synchronization event to the
USB bus. This interrupt is generated at the end of
a resume sequence too and can be used to detect
this event.
4.4.5.1 Initializing the Registers
At system reset, the software must initialize all reg-
isters to enable the USB interface to properly gen-
erate interrupts and DMA requests.
USB Reset (RESET)
When this event occurs, the DADDR register is re-
set, and communication is disabled in all endpoint
registers (the USB interface will not respond to any
packet). Software is responsible for reenabling
endpoint 0 within 10 ms of the end of reset. To do
this you set the STAT_RX bits in the EP0RB regis-
ter to VALID.
1. Initialize the DMAR, IDR, and IMR registers
(choice of enabled interrupts, address of DMA
buffers). Refer the paragraph titled initializing
the DMA Buffers.
2. Initialize the EP0RA and EP0RB registers to
enable accesses to address 0 and endpoint 0
to support USB enumeration. Refer to the para-
graph titled Endpoint Initialization.
Suspend (SUSP)
The CPU is warned about the lack of SOF events
for more than 3 ms, which is a suspend request.
The software should set the USB interface to sus-
pend mode and execute an ST7 HALT instruction
to meet the USB-specified power constraints.
3. When addresses are received through this
channel, update the content of the DADDR.
4. If needed, write the endpoint numbers in the EA
fields in the EP1RB and EP2RB register.
4.4.5.2 Initializing DMA buffers
End Suspend (ESUSP)
The DMA buffers are a contiguous zone of memo-
ry whose maximum size is 48 bytes. They can be
placed anywhere in the memory space, typically in
RAM, to enable the reception of messages. The
10 most significant bits of the start of this memory
area are specified by bits DA15-DA6 in registers
DMAR and IDR, the remaining bits are 0. The
memory map is shown inFigure 27.
The CPU is alerted by activity on the USB, which
causes an ESUSP interrupt. The ST7 automatical-
ly terminates HALT mode.
Correct Transfer (CTR)
1. When this event occurs, the hardware automat-
ically sets the STAT_TX or STAT_RX to NAK.
Note: Every valid endpoint is NAKed until soft-
ware clears the CTR bit in the ISTR register,
Each buffer is filled starting from the bottom (last 3
address bits=000) up.
independently
of the endpoint number
addressed by the transfer which generated the
CTR interrupt.
4.4.5.3 Endpoint Initialization
Note:
If the event triggering the CTR interrupt is
To be ready to receive:
a SETUP transaction, both STAT_TX and
STAT_RX are set to NAK.
Set STAT_RX to VALID (11b) in EP0RB to enable
reception.
2. Read the PIDR to obtain the token and the IDR
to get the endpoint number related to the last
transfer.
To be ready to transmit:
1. Write the data in the DMA transmit buffer.
Note: When a CTR interrupt occurs, the TP3-
TP2 bits in the PIDR register and EP1-EP0 bits
in the IDR register stay unchanged until the
CTR bit in the ISTR register is cleared.
2. In register EPnRA, specify the number of bytes
to be transmitted in the TBC field
3. Enable the endpoint by setting the STAT_TX
bits to VALID (11b) in EPnRA.
3. Clear the CTR bit in the ISTR register.
Note:
Once transmission and/or reception are en-
abled, registers EPnRA and/or EPnRB (respec-
tively) must not be modified by software, as the
hardware can change their value on the fly.
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ST72671
USB INTERFACE(Cont’d)
Table 14. USB Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
PIDR
TP3
x
TP2
x
0
0
0
0
0
0
0
0
0
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
Reset Value
0
0
0
DMAR
DA15
x
DA14
x
DA13
x
DA12
x
DA11
x
DA10
x
DA9
x
DA8
x
Reset Value
IDR
DA7
x
DA6
x
EP1
x
EP0
x
CNT3
0
CNT2
0
CNT1
0
CNT0
0
Reset Value
ISTR
SUSP
0
DOVR
0
CTR
0
ERR
0
IOVR
0
ESUSP
0
RESET
0
SOF
0
Reset Value
IMR
SUSPM
0
DOVRM
0
CTRM
0
ERRM
0
IOVRM ESUSPM RESETM
SOFM
0
Reset Value
0
0
0
CTLR
0
0
0
0
0
0
0
0
RESUME PDWN
FSUSP
1
FRES
0
Reset Value
0
1
DADDR
0
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
Reset Value
EP0RA
ST_OUT DTOG_TX STAT_TX1 STAT_TX0
TBC3
x
TBC2
x
TBC1
x
TBC0
x
Reset Value
0
0
0
0
EP0RB
1
1
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
0
0
0
0
0
Reset Value
0
0
0
EP1RA
ST_OUT DTOG_TX STAT_TX1 STAT_TX0
TBC3
x
TBC2
x
TBC1
x
TBC0
x
Reset Value
0
0
0
0
EP1RB
CTRL
0
DTOG_RX STAT_RX1 STAT_RX0
EA3
x
EA2
x
EA1
x
EA0
x
Reset Value
0
0
0
EP2RA
ST_OUT DTOG_TX STAT_TX1 STAT_TX0
TBC3
x
TBC2
x
TBC1
x
TBC0
x
Reset Value
0
0
0
0
EP2RB
CTRL
0
DTOG_RX STAT_RX1 STAT_RX0
EA3
x
EA2
x
EA1
x
EA0
x
Reset Value
0
0
0
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ST72671
4.5 I C BUS INTERFACE (I2C)
4.5.1 Introduction
handshake. The interrupts are enabled or disabled
2
2
by software. The interface is connected to the IC
The I C Bus Interface serves as an interface be-
tween the microcontroller and the serial IC bus. It
2
bus by a data pin (SDAI) and by a clock pin (SCLI).
2
It can be connected both with a standard IC bus
provides both multimaster and slave functions,
2
2
and a Fast I C bus. This selection is made by soft-
and controls all I C bus-specific sequencing, pro-
ware.
tocol, arbitration and timing. It supports fast I C
mode (400kHz).
Mode Selection
4.5.2 Main Features
The interface can operate in the four following mo-
des:
2
– Parallel bus/I C protocol converter
– Slave transmitter/receiver
– Multi-Master capability
– Interrupt generation
– Master transmitter/receiver
By default, it operates in slave mode.
2
2
– Standard I C mode/Fast I C mode
– 7-bit Addressing
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, this allows Multi-Master capabi-
lity.
2
■ I C Slave Mode
– Start bit detection flag
– Detection of misplaced Start or Stop condition
– Transfer problem detection
– Address Matched detection
– Default Address detection
– End of byte transmission flag
– Transmitter/Receiver flag
– Stop bit Detection
Communication Flow
In Master mode, it initiates a data transfer and ge-
nerates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recogni-
sing its own address (7-bit), and the General Call
address. The General Call address detection may
be enabled or disabled by software.
2
■ I C Master Mode
2
– I C bus busy flag
– Arbitration lost flag
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start condi-
tion is the address byte; it is always transmitted in
Master mode.
– End of byte transmission flag
– Transmitter/Receiver flag
– Clock generation
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer toFig-
ure 1.
4.5.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
2
Figure 1. I C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
VR02119B
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ST72671
I C BUS INTERFACE(Cont’d)
Acknowledge may be enabled and disabled by
software.
The SCL frequency (F ) is controlled by a pro-
SCL
grammable clock divider which depends on the
2
2
I C bus mode.
The I C interface address and/or general call ad-
2
dress can be selected by software.
When the I C cell is enabled, the SDA and SCL
2
ports must be configured as floating open-drain
output or floating input. In this case, the value of
the external pull-up resistance used depends on
the application.
The speed of the I C interface may be selected
2
between Standard (0-100KHz) and Fast IC (100-
400KHz).
2
When the I C cell is disabled, the SDA and SCL
SDA/SCL Line Control
ports revert to being standard I/O port pins.
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
2
Figure 2. I C Interface Block Diagram
DATA REGISTER (DR)
DATA SHIFT REGISTER
SDAI
DATA CONTROL
SDA
COMPARATOR
OWN ADDRESS REGISTER(OAR)
SCLI
CLOCK CONTROL
SCL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
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I C BUS INTERFACE(Cont’d)
4.5.4 Functional Description
Refer to the CR, SR1 and SR2 registers inSection
4.5.5. for the bit definitions.
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
2
SCL line low
(see Figure 3 Transfer sequencing
By default the I C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
EV3).
When the acknowledge pulse is received:
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
4.5.4.1 Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
Closing slave communication
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
Address not matched
: the interface ignores it
and waits for another Start condition.
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
Address matched
quence:
: the interface generates in se-
Then the interface waits for a read of the SR2 re-
gister (see Figure 3 Transfer sequencing EV4).
– Acknowledge pulse if the ACK bit is set.
Error Cases
– EVF and ADSL bits are set with an interrupt if the
ITE bit is set.
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards the data,
released the lines and waits for another Start
condition.
Then the interface waits for a read of the SR1 reg-
holding the SCL line low
ister,
Transfer sequencing EV1).
(see Figure 3
Next, read the DR register to determine from the
least significant bit if the slave must enter Receiver
or Transmitter mode.
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
Slave Receiver
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
Following the address reception and after SR1 re-
gister has been read, the slave receives bytes
from the SDA line into theDR registervia the inter-
nal shift register. After each byte the interface ge-
nerates in sequence:
Note: In both cases, SCL line is not held low;
however, SDA line can remain low due to possible
«0» bits transmitted last. It is then necessary to re-
lease both lines by software.
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
How to release the SDA / SCL lines
Then the interface waits for a read of the SR1 re-
gister followed by a read of the DR register,hol-
ding the SCL line low(see Figure 3 Transfer se-
quencing EV2).
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
Slave Transmitter
Following the address reception and after SR1
register has been read,the slave sends bytes from
the DR registertothe SDA line via the internal shift
register.
56/101
ST72671
I C BUS INTERFACE(Cont’d)
4.5.4.2 Master Mode
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Start condition and Transmit Slave address
Master Transmitter
Setting the START bit while the BUSY bit is clea-
red causes the interface to switch to Master mode
(M/SL bit set) and generates a Start condition.
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 3 Transfer sequencing
EV8).
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address byte, holding the SCL line low
(see Figure 3 Transfer sequencing EV5).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
Then the slave address byte is sent to the SDA
line via the internal shift register.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gene-
rate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Error Cases
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
holding the SCL line low
ple set PE bit),
gure 3 Transfer sequencing EV6).
(see Fi-
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
Next the master must enter Receiver or Transmit-
ter mode.
Master Receiver
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slavemode (the M/SL
bit is cleared).
Following the address transmission and after SR1
and CR registers have been accessed, themaster
receives bytes from the SDA line into theDR regis-
ter via the internal shift register. After each byte
the interface generates in sequence:
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmitted last. It is then neces-
sary to release both lines by software.
– Acknowledge pulse if if the ACK bit is set
– EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 re-
gister followed by a read of the DR register,hol-
ding the SCL line low(see Figure 3 Transfer se-
quencing EV7).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit clea-
red).
57/101
ST72671
I C BUS INTERFACE(Cont’d)
Figure 3. Transfer Sequencing
Slave receiver:
S
Address
A
Data1
A
Data2
EV3
A
Data2
Data2
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
Slave transmitter:
S
Address
A
Data1
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
Master receiver:
S
Address
A
Data1
A
A
DataN NA
P
EV5
EV6
EV7
A
EV7
A
EV7
A
Master transmitter:
S
Address
A
Data1
Data2
DataN
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2:
EV3:
EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, cleared by reading SR1 register.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6:
EV7:
EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
Figure 4. Event Flags and Interrupt Generation
BTF
ADSL
SB
ITE
AF
INTERRUPT
STOPF
ARLO
BERR
EVF
*
* EVF can also be set by EV6 or an error from the SR2 register.
58/101
ST72671
I C BUS INTERFACE(Cont’d)
4.5.5 Register Description
Bit 2 = ACK Acknowledge enable.
2
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
I C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
PE
ENGC START ACK STOP
ITE
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– In master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the cur-
rent byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
2
– To enable theI C interface, write the CR register
TWICE
with PE=1 as the first write only activates
the interface (only PE is set).
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac-
knowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Refer to Figure 4 for the relationship between the
events and the interrupt.
SCL is held low when the SB, BTF or ADSL flags
or an EV6 event (SeeFigure 3) is detected.
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In slave mode:
0: No start generation
1: Start generation when the bus is free
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ST72671
2
I C INTERFACE (Cont’d)
2
I C STATUS REGISTER 1 (SR1)
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
Read Only
Reset Value: 0000 0000 (00h)
7
0
EVF
0
TRA BUSY BTF ADSL M/SL
SB
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (SeeFigure 3). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described inFigure 3. It
is also cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
– BTF=1 (Byte received or transmitted)
The SCL line is held low while BTF=1.
– ADSL=1 (Address matched in Slave mode
while ACK=1)
0: Byte transfer not done
1: Byte transfer succeeded
– SB=1 (Start condition generated in Master
mode)
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
ing SR1 register or by hardware when the inter-
face is disabled (PE=0).
– AF=1 (No acknowledge received after byte
transmission if ACK=1)
– STOPF=1 (Stop condition detected in Slave
mode)
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
The SCL line is held low while ADSL=1.
– Address byte successfully transmitted in Mas-
ter mode.
0: Address mismatched or not received
1: Received address matched
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 1 = M/SL Master/Slave.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
TRA Transmitter/Receiver.
Bit 5 =
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-
tection of Stop condition (STOPF=1), loss of bus
arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
1: Master mode
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start
condition is generated (following
a
write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register.It is also
cleared by hardware when the interface is disa-
bled (PE=0).
Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. This information is still updat-
ed when the interface is disabled (PE=0).
0: No communication on the bus
0: No Start condition
1: Start condition generated
1: Communication ongoing on the bus
60/101
ST72671
2
I C INTERFACE (Cont’d)
2
I C STATUS REGISTER 2 (SR2)
es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
the interface is disabled (PE=0).
Read Only
Reset Value: 0000 0000 (00h)
7
0
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
0
0
0
AF STOPF ARLO BERR GCAL
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 1 = BERR Bus error.
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
terface is disabled (PE=0).
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
The SCL line is not held low while BERR=1.
0: No acknowledge failure
1: Acknowledge failure
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Bit 3 = STOPF Stop detection (Slave mode).
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No general call address detected on bus
1: general call address detected on bus
0: No Stop condition detected
1: Stop condition detected
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware when the interface los-
61/101
ST72671
2
I C INTERFACE (Cont’d)
2
2
I C CLOCK CONTROL REGISTER (CCR)
I C OWN ADDRESS REGISTER (OAR)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
FM/SM CC6
CC5
CC4
CC3
CC2
CC1
CC0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
2
FM/SM
C mode.
Fast/Standard I
Bit 7 =
This bit is set and cleared by software.It is not
cleared when the interface is disabled (PE=0).
Bit 7:1 = ADD7-ADD1 Interface address.
These bits define the I C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
2
2
0: Standard I C mode
2
1: Fast I C mode
Bit 6:0 = CC6-CC0 7-bit clock divider.
ADD0
Bit 0 =
Address direction bit.
These bits select the speed of the bus (F ) de-
SCL
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
2
pending on the I C mode. They are not cleared
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): F
<= 100kHz
SCL
Note: Address 01h is always ignored.
F
= f
/(2x([CC6..CC0]+2))
SCL
CPU
– Fast mode (FM/SM=1): F
> 100kHz
SCL
F
= f /(3x([CC6..CC0]+2))
CPU
SCL
Note: The programmed F
SCL and SDA lines.
assumes no load on
SCL
2
I C DATA REGISTER DR)
(
Read / Write
Reset Value: 0000 0000 (00h)
7
0
D7
D6
D5
D4
D3
D2
D1
D0
D7-D0
Bit 7:0 =
8-bit Data Register.
These bits contains the byte to be received or
transmitted on the bus.
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the next data bytes are received one by
one after reading the DR register.
62/101
ST72671
I2C INTERFACE (Cont’d)
2
Table 15. I C Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
CR
SR1
SR2
CCR
OAR
DR
5F
5E
5D
5C
5B
59
PE
ENGC
BUSY
AF
START
BTF
ACK
ADSL
ARLO
STOP
M/SL
ITE
SB
EVF
TRA
STOPF
CC6 .. CC0
BERR
GCAL
FM/SM
ADD7 .. ADD0
DR7 .. DR0
63/101
ST72671
4.6 SERIAL COMMUNICATIONS INTERFACE (SCI)
4.6.1 Introduction
4.6.3 General Description
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format.
The interface is externally connected to another
device by two pins (seeFigure 5):
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
4.6.2 Main Features
■
Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Independently programmable transmit and
receive baud rates up to 250K baud.
■ Programmable data word length (8 or 9 bits)
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
■ Receive buffer full, Transmit buffer empty and
Through this pins, serial data is transmitted and re-
ceived as frames comprising:
End of Transmission flags
■
Two receiver wake-up modes:
– An Idle Line prior to transmission or reception
– A start bit
– Address bit (MSB)
– Idle line
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
■ Muting function formultiprocessor configurations
■ Separate enable bits for Transmitter and
Receiver
■
Three error detection flags:
– Overrun error
– Noise error
– Frame error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
64/101
ST72671
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
Figure 5. SCI Block Diagram
Write
Read
(Data Register) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
CR1
R8 T8
-
-
M
WAKE
-
-
WAKE
UP
UNIT
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
CR2
SR
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE
-
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
Transmitter Rate
Control
f
CPU
/PR
/2
/16
BRR
SCP1
SCP0SCT2 SCT1 SCT0 SCR2 SCR1SCR0
Receiver Rate
Control
BAUD RATE GENERATOR
65/101
ST72671
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
4.6.4 Functional Description
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
The block diagram of the Serial Control Interface,
is shown inFigure 5. It contains 4 dedicated regis-
ters:
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– Two control registers (CR1 & CR2)
– A status register (SR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
– A baud rate register (BRR)
Refer to the register descriptions inSection 4.6.5
for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
4.6.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the CR1 register
(see Figure 5).
Figure 6. Word length programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit5
Bit6
Bit8
Bit0
Bit1
Bit3
Bit4
Bit7
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Start
Bit
Next
Start
Stop
Bit
Bit2
Bit0
Bit1
Bit3
Bit4 Bit5
Bit6
Bit7
Bit
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
66/101
ST72671
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
4.6.4.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CC register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the CR1 reg-
ister.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SR register
2. A write to the DR register
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the DR register consists of a buffer (TDR) between
the internal bus and the transmit shift register (see
Figure 5).
Note:
The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 6).
Procedure
– Select the M bit to define the word length.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
– Select the desired baud rate using the BRR reg-
ister.
– Set the TE bit to assign the TDO pin to the alter-
nate function and to send a idle frame as first
transmission.
Idle Characters
– Access the SR register and write the data to
send in the DR register (this sequence clears the
TDRE bit). Repeat this sequence for each data to
be transmitted.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SR register
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the DR.
2. A write to the DR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register
without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CC register.
When a transmission is taking place, a write in-
struction to the DR register stores the data in the
TDR register and which is copied in the shift regis-
ter at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the DR register places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.
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ST72671
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
4.6.4.3 Receiver
Overrun Error
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the CR1 reg-
ister.
Character reception
When a overrun error occurs:
– The OR bit is set.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, DR
register consists in a buffer (RDR) between the in-
ternal bus and the received shift register (seeFig-
ure 5).
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CC register.
Procedure
– Select the M bit to define the word length.
The OR bit is reset by an access to the SR register
followed by a DR register read operation.
– Select the desired baud rate using the BRR reg-
ister.
Noise Error
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CC register.
– Data is transferred from the Shift register to the
DR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
Clearing the RDRF bit is performed by the following
software sequence done by:
The NF bit is reset by a SR register read operation
followed by a DR register read operation.
1. An access to the SR register
2. A read to the DR register.
Framing Error
A framing error is detected when:
The RDRF bit mustbe cleared before the end of the
reception of the next character to avoid an overrun
error.
– The stopbit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
Break Character
– A break is received.
When a break character is received, the SCI han-
dles it as a framing error.
When the framing error is detected:
– the FE bit is set by hardware
Idle Character
– Data is transferred from the Shift register to the
DR register.
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CC register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SR register read operation
followed by a DR register read operation.
68/101
ST72671
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
4.6.4.4 Baud Rate Generation
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
The non addressed devices may be placed in
sleep mode by means of the muting function.
f
f
CPU
CPU
Setting the RWU bit by software puts the SCI in
sleep mode:
Rx =
(32 PR) RR
Tx =
(32 PR) TR
*
*
*
*
All the reception status bits can not be set.
All the receive interrupt are inhibited.
with:
PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
A muted receiver may be awakened by one of the
following two ways:
(see SCT0, SCT1 & SCT2 bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
(see SCR0,SCR1 & SCR2 bits)
All these bits are in the BRR register.
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
Example: If f
is 8 MHz and if PR=13 and
CPU
TR=RR=1, the transmit and receive baud rates are
19200 baud.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, sets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
Note:
the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
4.6.4.5 Receiver Muting and Wake-up Feature
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
69/101
ST72671
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
4.6.5 Register Description
Note:
The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs). This bit is not set by an idle line when the re-
ceiver wakes up from wake-up mode.
STATUS REGISTER (SR)
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
0
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 reg-
ister. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Overrun error
TDRE
TC
RDRF IDLE
OR
NF
FE
TDRE Transmit data register empty.
Bit 7 =
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE =1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: data will not be transferred to the shift regis-
ter as long as the TDRE bit is not reset.
This bit is set by hardware when noise is detected
on a received frame. It is cleared by hardware
when RE=0 by a software sequence (an access to
the SR register followed by a read to the DR regis-
ter).
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
FE Framing error.
Bit 1 =
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred into the DR
register. An interrupt is generated if RIE=1 in the
CR2 register. It is cleared by hardware when
RE=0 or by a software sequence (an access to the
SR register followed by a read to the DR register).
0: Data is not received
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
1: Received data is ready to be read
IDLE Idle line detect.
Bit 4 =
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the CR2 register. It is cleared by hardware when
RE=0 by a software sequence (an access to the
SR register followed by a read to the DR register).
0: No Idle Line is detected
Bit 0 = Reserved, forced by hardware to 0.
1: Idle Line is detected
70/101
ST72671
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
CONTROL REGISTER 1 (CR1)
Read/Write
0: interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
the SR register
Reset Value: Undefined
RIE
Bit 5 =
Receiver interrupt enable.
7
0
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SR register
R8
T8
0
M
WAKE
0
0
0
R8 Receive data bit 8.
Bit 7 =
This bit is used to store the 9th bit of the received
word when M=1.
ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
Bit 4 =
1: An SCI interrupt is generated whenever IDLE=1
in the SR register.
T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
Bit 6 =
TE Transmitter enable.
Bit 3 =
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
Bit 5 = Reserved, forced by hardware to 0.
0: Transmitter is disabled, the TDO pin is back to
the I/O port configuration.
1: Transmitter is enabled
M Word length.
This bit determines the data length. It is set or
cleared by software.
Bit 4 =
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note:
during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled, it resets the RDRF, IDLE,
OR, NF and FE bits of the SR register.
1: Receiver is enabled and begins searching for a
start bit.
Bit 2 =
1: Address Mark
Bit 2:0 = Reserved, forced by hardware to 0.
Bit 1 = RWU Receiver wake-up.
CONTROL REGISTER 2 (CR2)
Read/Write
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
Reset Value: 0000 0000 (00h)
7
0
0: Receiver in active mode
1: Receiver in mute mode
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 0 =
TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SR register.
Bit 7 =
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
TCIE
Bit 6 =
ble
Transmission complete interrupt ena-
This bit is set and cleared by software.
71/101
ST72671
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
DATA REGISTER (DR)
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
8
16
32
64
128
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 5).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 5).
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
BAUD RATE REGISTER (BRR)
Read/Write
RR dividing factor
SCR2
SCR1
SCR0
Reset Value: 00xx xxxx (XXh)
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
8
16
32
64
128
Bit 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
PR Prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
4
13
72/101
ST72671
SERIAL COMMUNICATIONS INTERFACE(Cont’d)
Table 16. SCI Register Map and Reset Values
Address
(Hex.)
Register Name
7
6
5
4
3
2
1
0
30
SR
TDRE
TC
1
RDRF
IDLE
OR
NF
FE
0
Reset Value
DR
1
DR7
x
0
0
DR4
x
0
0
0
0
31
32
33
34
DR6
x
DR5
DR3
DR2
DR1
DR0
Reset Value
BRR
x
x
x
x
x
SCP1
0
SCP0
0
SCT2
SCT1
x
SCT0
SCR2
SCR1
SCR0
Reset Value
CR1
x
0
x
WAKE
x
x
0
x
x
0
R8
x
T8
x
M
0
0
Reset Value
CR2
0
x
0
0
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
Reset Value
0
73/101
ST72671
4.7 PWM/BRM GENERATOR (DAC)
4.7.1 Introduction
The counter increments continuously, clocked at
internal CPU clock. Whenever the 6 least signifi-
cant bits of the counter (defined as the PWM coun-
ter) overflow, the output level for all active chan-
nels is set.
This PWM/BRM peripheral includes two types of
PWM/BRM outputs, with differing step resolutions
based on the Pulse Width Modulator (PWM) and
Binary Rate Multiplier (BRM) Generator technique
are available. It allows the digital to analog conver-
sion (DAC) when used with external filtering.
The state of the PWM counter is continuously
compared to the PWM binary weight for each
channel, as defined in the relevant PWM register,
and when a match occurs the output level for that
channel is reset.
4.7.2 Main Features
■ Fixed frequency: f /64
CPU
■ Resolution: TCPU
This Pulse Width modulated signal must be fil-
tered, using an external RC network placed as
close as possible to the associated pin. This pro-
vides an analog voltage proportional to the aver-
age charge passed to the external capacitor. Thus
for a higher mark/space ratio (High time much
greater than Low time) the average output voltage
is higher. The external components of the RC net-
work should be selected for the filtering level re-
quired for control of the system variable.
■
10-Bit PWM/BRM generator with a step of
10
VDD/2 (5mV if VDD=5V)
■ 12-bit PWM/BRM generator with step of
12
VDD/2 (1.25mV if VDD=5V).
4.7.3 Functional Description
4.7.3.1 10-bit PWM/BRM
The 10 bits of the 10-bit PWM/BRM are distributed
as 6 PWM bits and 4 BRM bits. The generator con-
sists of a 12-bit counter (common for all channels),
a comparator and the PWM/BRM generation logic.
Each output may individually have its polarity in-
verted by software, and can also be used as a log-
ical output.
PWM Generation
Figure 28. PWM Generation
COUNTER
OVERFLOW
63
OVERFLOW
OVERFLOW
COMPARE
VALUE
000
t
t
PWM OUTPUT
TCPU x 64
74/101
ST72671
PWM/BRM GENERATOR(Cont’d)
PWM/BRM Outputs
Table 17. 6-Bit PWM Ripple After Filtering
The PWM/BRM outputs are assigned to dedicated
pins.
In these pins, the PWM/BRM outputs are connect-
ed to a serial resistor which must be taken into ac-
count to calculate the RC filter (seeFigure 29).
In any case, the RC filter time must be higher than
TCPUx64.
C
(µF)
V RIPPLE (mV)
ext
0.128
1.28
12.8
78
7.8
0.78
With RC filter (R=1kW),
f
= 8 MHz
= 5V
CPU
Figure 29. Typical PWM Output Filter
V
DD
PWM Duty Cycle 50%
OUTPUT
VOLTAGE
R=Rint+Rext (Rext is optional).
1K (max)
OUTPUT
STAGE
Note: After a reset these pins are tied low by de-
fault and are not in a high impedance state.
R
R
ext
int
C
ext
Figure 30. PWM Simplified Voltage Output After Filtering
V
DD
PWMOUT
0V
V
(mV)
V
ripple
V
DD
OUTPUT
VOLTAGE
OUTAVG
0V
”CHARGE”
”DISCHARGE”
”CHARGE”
”DISCHARGE”
V
DD
PWMOUT
0V
V
DD
V
(mV)
ripple
OUTPUT
VOLTAGE
0V
V
OUTAVG
VR01956
”CHARGE”
”DISCHARGE”
”CHARGE”
”DISCHARGE”
75/101
ST72671
PWM/BRM GENERATOR(Cont’d)
BRM Generation
Note. If 00h is written to both PWM and BRM reg-
isters, the generator output will remain at “0”. Con-
versely, if both registers hold data 3Fh and 0Fh,
respectively, the output will remain at “1” for all in-
tervals #1 to #15, but it will return to zero at interval
#0 for an amount of time corresponding to the
The BRM bits allow the addition of a pulse to wid-
en a standard PWM pulse for specific PWM cy-
cles. This has the effect of “fine-tuning” the PWM
Duty cycle (without modifying the base duty cycle),
thus, with the external filtering, providing additional
fine voltage steps.
PWM resolution (T
).
CPU
An output can be set to a continuous “1” level by
clearing the PWM and BRM values and setting
POL = “1” (inverted polarity) in the PWM register.
This allows a PWM/BRM channel to be used as an
additional I/O pin if the DAC function is not re-
quired.
The incremental pulses (with duration of T ) are
CPU
added to the beginning of the original PWM pulse.
The PWM intervals which are added to are speci-
fied in the 4-bit BRM register and are encoded as
shown in the following table. The BRM values
shown may be combined together to provide a
summation of the incremental pulse intervals
specified.
Table 18. Bit BRM Added Pulse Intervals
(Interval #0 not selected).
The pulse increment corresponds to the PWM res-
olution.
BRM 4 - Bit Data
0000
Incremental Pulse Intervals
none
For example,if
– Data 18h is written to the PWM register
0001
i = 8
– Data 06h (00000110b) is written to the BRM reg-
ister
0010
i = 4,12
0100
i = 2,6,10,14
i = 1,3,5,7,9,11,13,15
– with a 8MHz internal clock (125ns resolution)
1000
Then 3.0 µs-long pulse will be output at 8µs inter-
vals, except for cycles numbered 2,4,6,10,12,14,
where the pulse is broadened to 3.125µs.
Figure 31. BRM pulse addition (PWM > 0)
m = 15
m = 0
m = 1
m = 2
TCPU x 64
TCPU x 64
TCPU x 64
TCPU x 64
T
CPU increment
76/101
ST72671
PWM/BRM GENERATOR(Cont’d)
Figure 32. Simplified Filtered Voltage Output Schematic with BRM added
=
=
=
V
DD
PWMOUT
0V
V
DD
BRM = 1
BRM = 0
OUTPUT
VOLTAGE
0V
TCPU
BRM
EXTENDED PULSE
Figure 33. Graphical Representation of 4-Bit BRM Added Pulse Positions
PWM Pulse Number (0-15)
BRM VALUE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0001 bit0=1
0001 bit0=1
0100 bit2=1
0100 bit2=1
Examples
0110
1111
77/101
ST72671
PWM/BRM GENERATOR(Cont’d)
4.7.3.2 12-Bit PWM/BRM
4.7.3.3 PWM/BRM OUTPUTS
The 12 bits of the 12-bit PWM/BRM generator are
distributed as 6 PWM bits and 6 BRM bits.
The PWM/BRM outputs are assigned to dedicated
pins.
If necessary, these pins can be used in push-pull
or open-drain modes under software control.
In these pins, the PWM/BRM outputs are connect-
ed to a serial resistor which must be taken into ac-
count to calculate the RC filter.
PWM Generation
The functionality of the PWM generation is equiva-
lent to the PWM generation of the 10-bit
PWM/BRM described in the previous paragraph
and so will not be repeated here. Please refer to
the previous paragraph for functionality, to be
used in conjunction with the Register description.
BRM Generation
A 6-bit BRM register defining the intervals where
an incremental pulse (with duration of T ) is
CPU
added to the beginning of the original PWM pulse.
BRM 6 - Bit Data
000000
Incremental Pulse Intervals
none
000001
i = 32
000010
i = 16,48
000100
i = 8,24,40,56
001000
i = 4,12,20,28,36,44,52,60
i = 2,6,10,...50,54,58,62
i = 1,3,5,7,9,...55,59,61,63
010000
100000
Figure 34. Precision for PWM/BRM Tuning for VOUTEFF (After filtering)
78/101
ST72671
PWM/BRM GENERATOR (Cont’d)
4.7.4 Register Description
4.7.4.2 12-bit PWM/BRM REGISTERS
4.7.4.1 10-bit PWM/BRM REGISTERS
The 12 bits are separated into two data registers:
On a channel basis, the 10 bits are separated into
two data registers:
– A 6-bit PWM register corresponding to the binary
weight of the PWM pulse.
– A 6-bit PWM register corresponding to the binary
weight of the PWM pulse.
– A 6-bit BRM register defining the intervals where
incremental pulses are added to the beginning of
the original PWM pulse.
– A 4-bit BRM register defining the intervals where
an incremental pulse is added to the beginning of
the original PWM pulse. Two BRM channel val-
ues share the same register.
PWM0 REGISTER
Read/ Write
Reset Value: 1000 0000 (80h)
Note: The number of PWM and BRM channels
available depends on the device. Refer to the de-
vice pin description and register map.
7
1
0
POL
P5
P4
P3
P2
P1
P0
PWM[1:8] REGISTERS
Read/Write
Reset Value 1000 0000 (80h)
Bit 7 = Reserved (read as “1”)
7
1
0
Bit 6 = POL Polarity Bit.
When POL is set, output signal polarity is inverse;
otherwise, no change occurs.
POL
P5
P4
P3
P2
P1
P0
Bit 7 = Reserved (read as “1”)
Bits 5:0 = P[5:0] PWM Pulse Binary Weight
Bit 6 = POL Polarity Bit.
When POL is set, output signal polarity is inverse;
otherwise, no change occurs.
BRM0 REGISTER
Read/ Write
Reset Value: 1100 0000 (C0h)
Bits 5:0 = P[5:0] PWM Pulse Binary Weight for
channel i .
7
1
0
1
B5
B4
B3
B2
B1
B0
BRM REGISTERS
BRM21 (Channels 2 + 1)
BRM43 (Channels 4 + 3)
BRM65 (Channels 6 + 5)
BRM87 (Channels 8 + 7)
Bits 7:6 = Unused
B[5:0] BRM Bits
Bits 5:0 =
Read/Write
Reset Value: 0000 0000 (00h)
7
0
B7
B6
B5
B4
B3
B2
B1
B0
B[7:4]
Bits 7:4 =
BRM Bits (channel i+1)
Bits 3:0 = B[3:0] BRM Bits (channel i)
79/101
ST72671
Note: From the programmer’s point of view, the PWM and BRM registers can be regarded as being com-
bined to give one data value.
For example (10-bit):
0
POL
P
P
P
P
P
P
+
B
B
B
B
Effective (with external RC filtering) DAC value
0
POL
P
P
P
P
P
P
B
B
B
B
Table 19. PWMA Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
22
23
24
25
26
27
28
29
PWM0
BRM0
PWM1
BRM21
PWM2
PWM3
BRM43
PWM4
POL
P5 ..P0
BRM Channel 0
P5 ..P0
POL
BRM Channel 2
POL
BRM Channel 1
P5 ..P0
P5 ..P0
POL
BRM Channel 4
POL
BRM Channel 3
P5 ..P0
80/101
ST72671
4.8 8-BIT A/D CONVERTER (ADC)
4.8.1 Introduction
4.8.2 Main Features
■ 8-bit conversion
■
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 8 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 8 different sources.
Up to 8 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■
Conversion complete status flag
■ On/off bit (to reduce consumption)
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
The block diagram is shown inFigure 35.
Figure 35. ADC block diagram
0
COCO
-
ADON
-
CH2 CH1 CH0
(Control Status Register) CSR
AIN0
AIN1
AIN2
AIN3
AIN4
SAMPLE
&
HOLD
ANALOG
MUX
ANALOG TO
DIGITAL
AIN5
AIN6
AIN7
CONVERTER
f
CPU
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
(Data Register) DR
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ST72671
8-BIT A/D CONVERTER (ADC)(Cont’d)
4.8.3 Functional Description
Procedure
The high level reference voltage V
must be
Refer to the CSR and SR registers Section 4.8.4
for the bit definitions.
DDA
connected externally to the V pin. The low level
DD
reference voltage V
must be connected exter-
SSA
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
nally to the V pin. In some devices (refer to de-
SS
vice pin out description) high and low level refer-
ence voltages are internally connected to the V
DD
and V pins.
SS
Conversion accuracy may therefore be degraded
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
In the CSR register:
– Select the CH2 to CH0 bits to assign the ana-
log channel to convert. Refer toTable 20.
Characteristics
– Set the ADON bit. Then the A/D converter is
enabled after a stabilization time (typically 30
µs). It then performs a continuous conversion
of the selected channel.
The conversion is monotonic meaning the result
never decreases if the analog input does not and
never increases if the analog input does not.
If input voltage is greater than or equal to V
(voltage reference high) then results = FFh (full
scale) without overflow indication.
DD
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
≤
If input voltage
V
SS
(voltage reference low) then
the results = 00h.
– The result is in the DR register.
A write to the CSR register aborts the current con-
version, resets the COCO bit and starts a new
conversion.
The conversion time is 64 CPU clock cycles in-
cluding a sampling time of 31.5 CPU clock cycles.
Notes: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
The A/D converter is linear and the digital result of
the conversion is given by the formula:
The A/D converter is not affected by WAIT mode.
255 * Input Voltage
Digital result =
When the MCU enters HALT mode with the A/D
converter enabled, the converter is disabled until
the HALT mode is exited and the start-up delay
has elapsed. A stabilisation time is also required
before accurate conversions can be performed.
Reference Voltage
Where Reference Voltage is V - V
.
SS
DD
The accuracy of the conversion is described in the
Electrical Characteristics Section.
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ST72671
8-BIT A/D CONVERTER (ADC)(Cont’d)
4.8.4 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
Bits 2-0: CH2-CH0 Channel Selection.
These bits are set and cleared by software. They
select the analog input to convert.
Reset Value: 0000 0000 (00h)
Table 20. Channel Selection
7
0
Pin*
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
CH2
0
CH1
0
CH0
0
COCO
-
ADON
0
-
CH2
CH1
CH0
0
0
1
0
1
0
Bit 7 = COCO Conversion Complete.
0
1
1
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete.
1: Conversion can be read from the DR register.
1
0
0
1
0
1
1
1
0
1
1
1
Bit 6 = Reserved. Must always be cleared.
(*The number of pins varies according to the de-
vice. Refer to the device pinout).
Bit 5 = ADON A/D converter On.
DATA REGISTER (DR)
Read Only
This bit is set and cleared by software.
0: A/D converter is switched off.
1: A/D converter is switched on.
Reset Value: 0000 0000 (00h)
Note: a typically 30µs delay time is necessary for
the ADC to stabilize when the ADON bit is set.
7
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Bit 4 = Reserved. Forced by hardware to 0.
Bit 3 = Reserved. Must always be cleared.
Bit 7:0 = AD7-AD0 Analog Converted Value.
This register contains the converted analog value
in the range 00h to FFh.
Reading this register reset the COCO flag.
Table 21. ADC Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
0B
0A
CSR
DR
COCO
-
ADON
0
-
CH2
CH1
CH0
AD7 .. AD0
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ST72671
5 INSTRUCTION SET
5.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
Indexed
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 22. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
ld A,$10
00..FF
Direct
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Direct
Indexed
Indexed
Indexed
Direct
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Direct
Short
Long
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF
00..1FE
0000..FFFF
PC+/-127
PC+/-127
00..FF
00..FF
00..FF
00..FF
Short
Long
Indexed
Indexed
Relative
Relative
Bit
Indirect
Direct
jrne [$10]
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
btjt $10,#7,skip
btjt [$10],#7,skip
Bit
Indirect
Direct
00..FF
Bit
Relative
Relative
00..FF
Bit
Indirect
00..FF
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ST72671
ST7 ADDRESSING MODES(Cont’d)
5.1.1 Inherent
5.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
SIM
5.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
RSP
LD
Indexed (No Offset)
CLR
Clear
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
CPL, NEG
MUL
Indexed (long)
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
5.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the the operand value. .
5.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
LD
Load
CP
Compare
Indirect (short)
BCP
Bit Compare
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
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ST72671
ST7 ADDRESSING MODES(Cont’d)
5.1.6 Indirect Indexed (Short, Long)
5.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two sub-modes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 23. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
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ST72671
5.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Code Condition Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four op-
codes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent probate pockets are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
opcode
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
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ST72671
INSTRUCTION GROUPS(Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
88/101
ST72671
INSTRUCTION GROUPS(Cont’d)
JRULE
LD
Jump if (C + Z = 1)
Load
Unsigned <=
dst <= src
X,A = X * A
neg $10
reg, M
A, X, Y
reg, M
M, reg
N
N
Z
MUL
NEG
NOP
OR
Multiply
X, Y, A
0
0
Negate (2’s compl)
No Operation
OR operation
Pop from the Stack
Z
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
N
N
Z
Z
POP
reg
CC
M
M
H
I
C
0
M
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
M
N
Z
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ST72671
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
Power Considerations.The average chip-junc-
tion temperature, T , in Celsius can be obtained
J
from:
T =
TA + PD x RthJA
J
Where: T =
Ambient Temperature.
A
For proper operation it is recommended that V
I
RthJA = Package thermal resistance
(junction-to ambient).
and V be higher than V and lower than V .
O
SS
DD
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (V
P =
D
P
+ P
INT PORT
DD
or V ).
SS
P
P
=
I
x V (chip internal power).
DD DD
INT
PORT
=Port power dissipation
(determined by the user).
Symbol
Parameter
Value
Unit
V
V
Supply Voltage
-0.3 to 6.0
-0.3 to 6.0
DD
V
Analog Reference Voltage
Input Voltage
V
DDA
V
V
- 0.3 to V + 0.3
V
I
SS
SS
DD
V
Output Voltage
V
- 0.3 to V + 0.3
V
O
DD
IV
IV
Total Current into V (source)
TBD
TBD
mA
mA
°C
°C
DD
DD
Total Current out of V (sink)
SS
SS
T
Junction Temperature
Storage Temperature
150
J
T
-60 to 150
STG
Note:
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
90/101
ST72671
6.2 RECOMMENDED OPERATING CONDITIONS
Value
Typ.
Symbol
Parameter
Test Conditions
1 Suffix Version
Unit
Min.
Max.
T
Operating Temperature
0
70
°C
A
f
f
= 8 MHz
= 4 MHz
4.5
4.0
5.5
5.5
CPU
CPU
V
Operating Supply Voltage
V
DD
V
V
= 4.0V
= 4.5V
0
0
12
24
DD
DD
f
Oscillator Frequency
MHz
OSC
Figure 36. Maximum Operating Frequency (Fmax) Versus Supply Voltage (V )
DD
24
FUNCTIONALITY IS
MAXIMUM
FREQUENCY
NOT GUARANTEED IN
(MHz)
12
THIS AREA
2.5
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE(V
)
DD
Note:
The shaded area is outside the recommended operating range; device functionality is not guaranteed under these
conditions.
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ST72671
6.3 DC ELECTRICAL CHARACTERISTICS
(T = 0 to +70°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
V
Min.
Max.
V x 0.3
DD
Input Low Level Voltage
All Input pins
V
V
IL
Input High Level Voltage
All Input pins
V
x 0.7
DD
V
IH
1)
Hysteresis Voltage
V
V
= 5V
TBD
V
V
HYS
DD
All Input pins
Low Level Output Voltage
All Output pins
V
V
= 5.0V; I = +10µA
= 5.0V; I = + 1.6mA
0.1
0.4
DD
DD
OL
OL
V
V
V
V
= 5.0V; I = +10µA
= 5.0V; I = +1.6mA
= 5.0V; I = +10mA
0.1
0.4
1.5
OL
DD
DD
DD
OL
Low Level Output Voltage
High Sink I/O pins
OL
OL
High Level Output Voltage
All Output pins
V
V
= 5.0V; I = -10µA
4.9
4
DD
DD
OL
V
V
OH
= 5.0V; I = 1.6mA
OL
Input Leakage Current
All Input pins but RESET
V
V
= V (No Pull-Up configured)
IN
IN
SS
0.1
-50
10
10
= V
I
DD
IL
µA
I
Input Leakage Current
RESET pin
V
V
= V
IH
IN
IN
SS
= V
DD
V
= 5.0V
= 12 MHz, f
= 24 MHz, f
DD
Supply Current in
RUN Mode
f
f
= 4 MHz
= 8 MHz
TBD
14
TBD
18
mA
mA
mA
2)
OSC
OSC
CPU
CPU
V
f
= 5.0V
= 12 MHz, f
= 24 MHz, f
DD
Supply Current in SLOW
= 2 MHz
= 4 MHz
TBD
3)
OSC
OSC
CPU
CPU
Mode
f
V
f
= 5.0V
= 12 MHz, f
= 24 MHz, f
DD
OSC
OSC
I
DD
Supply Current in WAIT
= 4 MHz
= 8 MHz
TBD
12
TBD
18
3)
CPU
CPU
Mode
f
I
= 0mA
Supply Current in HALT
Mode
LOAD
250
250
500
500
µA
µA
V
= 5.0V
DD
I
= 0mA
= 5.0V
LOAD
4)
USB Suspend Mode
V
DD
Notes:
1. Hysteresis voltage between switching levels
2. CPU running with memory access.
3. All peripherals in stand-by
4. CPU must be in Halt mode
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ST72671
6.4 A/D CONVERTER CHARACTERISTICS
(T = 0 to +70°C unless otherwise specified)
A
Value
Typ.
8
Symbol
Parameter
Resolution
Test Conditions
Unit
Min.
Max.
Res
Bit
LSB
µs
DLE
ILE
Differential linearity error
Integral linearity error
±0.3
±0.5
f
= 24 MHz
= 8 MHz
CPU
OSC
1
±
t
Conversion Time
f
8
C
Note: Noise at AV , AV <10mV
DD
SS
6.5 PWM (DAC) CHARACTERISTICS
PWM/BRM Electrical and Timings
Symbol
F
Parameter
Repetition rate
Conditions
Min
Typ
125
Max
Unit
kHz
ns
T
T
= 125ns
CPU
Res
Resolution
= 125ns
125
5
CPU
V
V
= 5V, 10 bits
= 5V, 12 bits
-
mV
DD
DD
S
Output step
Serial resistor
1.25
700
mV
R
1000
Ohms
S
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ST72671
6.5.1 I2C CHARACTERISTICS
I2C Electrical specifications
Standard mode I2C
Min Max
Fast mode I2C
Min Max
Parameter
Symbol Unit
Hysteresis of Schmitt trigger inputs
Fixed input levels
V
V
N/A
N/A
0.2
HYS
V
-related input levels
N/A
N/A
0.05 V
DD
DD
Pulse width of spikes which must be sup-
pressed by the input filter
T
T
I
ns
N/A
N/A
0 ns
50 ns
SP
Output fall time from VIH min to VIL max with
a bus capacitance from 10 pF to 400 pF
ns
OF
with up to 3 mA sink current at VOL1
with up to 6 mA sink current at VOL2
250
N/A
20+0.1Cb
20+0.1Cb
250
250
N/A
- 10
Input current each I/O pinwith an input voltage
µA
10
10
-10
10
10
between 0.4V and 0.9 V max
DD
Capacitance for each I/O pin
C
pF
N/A = Not Applicable
Cb = Capacitance of one bus in pF
I2C Bus Timings
Standard I2C
Fast I2C
Parameter
Symbol
Unit
ms
Min
Max
Min
Max
Bus free time between a STOP and START con-
dition
4.7
1.3
0.6
T
T
BUF
Hold time START condition. After this period,
the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
4.0
µs
HD:STA
4.7
4.0
4.7
1.3
0.6
0.6
T
T
T
T
T
µs
µs
µs
ns
ns
ns
ns
ns
pF
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
1)
1)
2)
0
0
0.9
Data set-up time
250
100
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
1000
300
20+0.1Cb
20+0.1Cb
0.6
300
300
TR
TF
4.0
T
SU:STO
400
400
Cb
Notes:
1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL
2. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal
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ST72671
USB ELECTRICAL CHARACTERISTICS
USB DC Electrical Characteristics
Parameter
Symbol
Conditions
AbsI((D+) - (D-))
Includes VDI range
Min.
0.2
Max.
Unit
V
Differential Input Sensitivity
Differential Common Mode Range
Single Ended Receiver Threshold
Output Levels
V
DI
V
0.8
2.5
2.0
V
CM
V
0.8
V
SE
OL
RL of 1.5K ohms to
3.6V
Static Output Low
Static Output High
V
V
0.3
V
RL of 15K ohms to
USBGND
2.8
3
3.6
3.6
V
V
OH
USBV : voltage level
USBV
V
=5V
DD
CC
Notes:
– RL is the load connected on the USB drivers.
– All the voltages are measured from the local ground potential (USBGND).
Figure 37. USB: Data signal Rise and fall time
Differential
Datas Lines
VCRS
Crossover
points
USBGND
TF
TR
USB: Low speed electrical characteristics
Parameter
Symbol
Conditions
Min
Max
Unit
Driver characteristics:
1)
CL=50 pF
75
75
ns
ns
ns
ns
%
Rise time
TR
1)
CL=350 pF
CL=50 pF
CL=350 pF
tr/tf
300
1)
1)
Fall Time
TF
300
120
Rise/ Fall Time matching
trfm
80
Output signal Crossover
Voltage
V
1.3
2.0
V
CRS
Note 1: Measured from 10% to 90% of the data signal
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ST72671
7 GENERAL INFORMATION
7.1 EPROM ERASURE
EPROM version devices are erased by exposure
to high intensity UV light admitted through the
transparent window. This exposure discharges the
floating gate to its initial state through induced
photo current.
An opaque coating (paint, tape, label, etc...)
should be placed over the package window if the
product is to be operated under these lighting con-
ditions. Covering the window also reduces I in
DD
power-saving modes due to photo-diode leakage
currents.
It is recommended that the EPROM devices be
kept out of direct sunlight, since the UV content of
sunlight can be sufficient to cause functional fail-
ure. Extended exposure to room level fluorescent
lighting may also cause erasure.
An Ultraviolet source of wave length 2537 Å yield-
2
ing a total integrated dosage of 15 Watt-sec/cm is
required to erase the device. It will be erased in 15
2
to 20 minutes if such a UV lamp with a 12mW/cm
power rating is placed 1 inch from the device win-
dow without any interposed filters.
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ST72671
7.2 PACKAGE MECHANICAL DATA
Figure 38. 56-Pin Shrink Plastic Dual In Line Package, 600-mil Width
mm
inches
Dim.
A
Min Typ Max Min Typ Max
6.35
0.250
A1 0.38
0.015
A2 3.18
4.95 0.125
0.195
b
0.41
0.89
0.016
0.035
b2
C
D
0.20
0.38 0.008
53.21 1.980
0.015
2.095
50.29
E
15.01
0.591
E1
e
12.32
2.92
14.73 0.485
0.580
1.78
0.070
0.600
eA
eB
L
15.24
17.78
0.700
0.200
5.08 0.115
PDIP56S
Number of Pins
N
56
Figure 39. 56-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width
mm
Min Typ Max Min Typ Max
4.17 0.164
inches
Dim.
A
A1 0.76
0.030
B
0.38 0.46 0.56 0.015 0.018 0.022
B1 0.76 0.89 1.02 0.030 0.035 0.040
C
D
0.23 0.25 0.38 0.009 0.010 0.015
50.04 50.80 51.56 1.970 2.000 2.030
D1
48.01
1.890
E1 14.48 14.99 15.49 0.570 0.590 0.610
e
1.78
0.070
G
14.12 14.38 14.63 0.556 0.566 0.576
G1 18.69 18.95 19.20 0.736 0.746 0.756
G2 1.14 0.045
G3 11.05 11.30 11.56 0.435 0.445 0.455
G4
L
15.11 15.37 15.62 0.595 0.605 0.615
CDIP56SW
2.92
5.08 0.115
0.200
S
1.40
0.055
Number of Pins
N
56
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ST72671
Figure 40. 64-Pin Thin Quad Flat Package
mm
inches
Dim
Min Typ Max Min Typ Max
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
B
C
0.30 0.35 0.40 0.012 0.014 0.016
D
15.80 16.00 16.20 0.622 0.630 0.638
13.95 14.00 14.05 0.549 0.551 0.553
D1
D3
E
15.80 16.00 16.20 0.622 0.630 0.638
13.95 14.00 14.05 0.549 0.551 0.553
E1
E3
e
0.80
0.031
K
0°
7°
L
0.50 0.60 0.75 0.020 0.024 0.030
L1
M
Number of Pins
N
ND
NE
64
16
16
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ST72671
7.3 ORDERING INFORMATION
Each device is available for production in user pro-
grammable version (OTP) as well as in factory
coded version (ROM). OTP devices are shipped to
customer with a default blank content FFh, while
ROM factory coded parts contain the code sent by
customer. There is one common EPROM version
for debugging and prototyping which features the
maximum memory size and peripherals of the sub-
family. Care must be taken to only use resources
available on the target device.
7.3.1 Transfer Of Customer Code
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-
ated by the development tool. All unused bytes
must be set to FFh.
The selected options are communicated to
SGS-THOMSON using the correctly completed
OPTION LIST appended.
Contact sales office for further ordering informa-
tion and availablity.
The SGS-THOMSON Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 41. ROM Factory Coded Device Types
TEMP.
PACKAGE RANGE
/ XXX
DEVICE
Code name (defined by SGS-Thomson)
1= standard 0 to +70 °C
B= Plastic DIP
T= Plastic TQFP
ST72671N4
Figure 42. OTP User Programmable Device Types
TEMP.
PACKAGE RANGE XXX
DEVICE
Special feature (defined by SGS-Thomson)
1= industrial -40 to +85 °C
B= Plastic DIP
T= Plastic TQFP
ST72T671N4
Note:
The ST72E671N4D0 (56-pin ceramic SDIP) is used as the EPROM version for the above devices.
The EPROM devices are tested for operation at 25 °C only.
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ST72671
ST72671 MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SGS-THOMSON Microelectronics references
Device:
[ ] ST72671
Package:
[ ] Dual in Line Plastic[ ] Thin Quad Flat Pack:
[ ] Standard (Stick)
[ ] Tape & Reel
Temperature Range:
Special Marking:
[ ] 0°C to + 70°C
[ ] No
[ ] Yes ”_ _ _ _ _ _ _ _ _ _ _ ”
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Maximum character count: SDIP56:
TQFP64:
11
10
Comments :
Supply Operating Range in the application:
Oscillator Frequency in the application:
Notes
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100/101
ST72671
Notes
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously
supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems
without the express written approval of SGS-THOMSON Microelectronics.
1998 SGS-THOMSONMicroelectronics - All rights reserved.
Purchase of I2C Components by SGS-THOMSONMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these
components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
SGS-THOMSON Microelectronics Group of Companies
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101/101
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