ST75C50 [STMICROELECTRONICS]
14.4kbps DATA, 14.4kbps FAX, MODEM-DATA/FAX/VOICE, PQFP160, PLASTIC, QFP-160;
| 型号： | ST75C50 |
| 厂家： | 
ST |
| 描述： | 14.4kbps DATA, 14.4kbps FAX, MODEM-DATA/FAX/VOICE, PQFP160, PLASTIC, QFP-160 电信 电信集成电路 |
| 文件： | 总55页 (文件大小：1082K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST75C50
V.32bis/V.17 HIGH SPEED MODEM DATAPUMP
ADVANCE DATA
.
.
2 AND 4 -WIRE FULL DUPLEX OPERATION
V.32BIS, V.17, V.33, V.32, V.29, V.27ter,
V.22BIS, V.22, V.21, V.23, BELL212A,103
GROUP 3 FAX AT 14400, 12000, 9600, 7200,
4800, 2400BPS
PARALLEL/SERIAL SYNCHRONOUS DATA
HANDLING
DIGITAL FAR AND NEAR END ECHO CAN-
CELLATION SUPPORTING A DELAY OF 2
SATELLITE HOPS (1.6 seconds) AND PHASE
ROLL UP TO 10Hz
.
.
.
TQFP44
(Plastic Quad Flat Pack)
.
.
.
.
.
.
.
AUTODIAL AND AUTOANSWER
COMPLETE HANDSHAKE MANAGEMENT
WIDE DYNAMIC RANGE (> 48dB)
COMPROMISE TRANSIT EQUALIZER
AUTOMATIC ADAPTIVE EQUALIZER
VOICE MODE (A LAW)
ENHANCED PROGRAMMABLE TONE DE-
TECTOR (INCLUDING DTMF)
AUTO MODE
MULTILEVEL OPERATING SOFTWARE
PQFP80
(Plastic Quad Flat Pack)
.
.
.
.
CCITT V.54 SIGNALLING
ANCILLARY CONVERTERS FOR EYE PAT-
TERN MONITORING
.
VERSATILE INTERFACES
• PARALLEL 64x8 DUAL PORT RAM
• SYNCHRONOUS SERIAL I/O
• AUXILLIARY PARALLEL I/O
.
CALLER ID DEMODULATION
PROGRAMMABLE HOST MCU INTERRUPT
RATE
SIMPLE CUSTOMISATION / EXTENSION OF
FUNCTIONALITY
LOW PROFILE TQFP PACKAGE OPTION
MONOPACKAGE DATAPUMP OPTION
.
.
PQFP160
(Plastic Quad Flat Pack)
.
.
ORDERING INFORMATION
Sales Type
Function
Package
PQFP 160
TQFP 44
PLCC 44
TQFP 80
PQFP 80
PQFP 160
PQFP 160
BOARD
ST75C50
Monopackage Datapump
ST7543 CQFP
ST7543 CNF
Mafe
Mafe
ST75C500 CQFP
ST75C500 PQFP
ST75C500 EQFP
ST18933 PQFP
ST75C50 DEMOI
STI8933 EMU-PC
Romed DSP
Romed DSP
Romed DSP with access to external additional memory
Customisable DSP
Modem
PC Software Developement Tool
PC BOARD
1/55
December 1993
This is advance information on a new product now in development or undergoing evaluation. Detailsare subject to change without notice.
ST75C50
SUMMARY
Page
I.
GENERAL DESCRIPTION................................................. ........................... ..................
4
II.
PIN CONNECTIONS......................................................... ...............................................
4
4
5
5
6
7
II.1
II.2
II.3
II.4
II.5
ST7543 TOP VIEW (PQFP44)........................... ........................................................... ...
ST75C500CQFPTOP VIEW (TQFP80)............................ ...............................................
ST75C500PQFP TOP VIEW (PQFP80)............................ ........................... ....................
ST18933 TOP VIEW (PQFP160).......................................... ........................... ................
ST75C50 TOP VIEW (PQFP160)........................................... ........................... ..............
III.
PIN DESCRIPTION..................................................................... .................................. ...
HOST INTERFACE.................................. ........................... .............................................
SERIAL INTERFACE........................................... ................................ ........................... .
ANALOG INTERFACE..................................... ........................... .....................................
EYE PATTERN INTERFACE.............................................. ........................... ..................
CLOCK INTERFACE ......................................... ........................... .................................. .
AUXILIARY INTERFACE........................... ........................... ........................... ................
MISCELLANEOUS..................................... ........................... ........................... ................
INTERCONNECTION...................................... ........................... ................................ .....
8
8
8
8
8
9
9
9
9
III.1
III.2
III.3
III.4
III.5
III.6
III.7
III.8
III.9
III.10
III.11
MEMORY INTERFACE.............................. ........................... ........................... ................ 10
BOUNDARY SCAN INTERFACE...................................... ........................... .................... 10
OPEN VERSION INTERFACE.............................................. ........................... ................ 10
IV.
ELECTRICAL SPECIFICATIONS .................................... ........................... .................... 11
MAXIMUM RATINGS (referenced to GND) ................................................... .................. 11
DC CHARACTERISTICS.................................................. ........................... .................... 11
IV.1
IV.2
IV.2.1
IV.2.2
IV.2.3
Power Supply And Common Mode Voltage............................ ........................... .............. 11
Digital Interface ............................... .................................. ........................... .................... 11
Analog Interface.......................... ........................... ................................ .......................... 11
IV.3
IV.3.1
IV.3.2
AC ELECTRICAL CHARACTERISTICS....................................... .................................. . 12
Dual Port Ram Host Read-cycle Timing.............................................. ........................... .. 12
Dual Port Ram Host Write-cycle Timing................................................... ........................ 13
V.
FUNCTIONAL DESCRIPTION ................................................. ........................... ............ 14
SYSTEM ARCHITECTURE ............................... ........................... .................................. . 14
CHIP SET INTERCONNECT CIRCUITRY.............................. ........................... .............. 14
V.1
V.2
V.3
OPERATION.............................................. ........................... ........................................... 14
Modes ........................................................ ........................... ........................... ................ 14
Transmitter Description ............................ ........................... ........................... .................. 14
Echo Canceller Description............................ ........................... ........................... ............ 14
Receiver Description..................................................................... .................................. . 14
Tone GeneratorDescription......................................................................... .................... 14
Tone Detector Description ........................... ........................... ........................... .............. 14
DTMF Detector Description............................................................................ .................. 14
Voice Mode Description ................................. .................................................... .............. 14
Analog Loop Back Test Mode ............................ ........................... .................................. . 14
V.3.1
V.3.2
V.3.3
V.3.4
V.3.5
V.3.6
V.3.7
V.3.8
V.3.9
V.3.10 Digital Loop Back Test Mode .......................................... ................................................. 14
V.3.11 Sleep Power Mode........................................................ ........................... ........................ 15
2/55
ST75C50
V.4
MODEM INTERFACE............................................ .................................. ........................ 15
Analog Interface.......................... ........................... ................................ .......................... 15
Host Interface......................................... ........................... ........................... .................... 15
Memory Interface ............................................. ........................... .................................. ... 15
Auxiliary Parallel Interface.......................... ........................... ........................... ................ 15
Auxiliary Serial Interface.............................. .................................. ........................... ........ 15
V.4.1
V.4.2
V.4.3
V.4.4
V.4.5
VI.
USER INTERFACE..................................................................... .................................. ... 15
VI.1
DUAL PORT RAM DESCRIPTION........................................................ .......................... 15
VI.1.1
Mapping .................................. .................................................... .................................. ... 15
Command Area ................................................ .................................. .......................... 15
Report Area............................................ ........................... ........................... ................ 15
Status Area.......................... ........................... ........................... ................................ ... 15
Optional Status Area ..................................................... ........................... .................... 15
Bulk Delay Exchange Area.............................................. ........................... .................. 15
Data Buffer Area..................................... .................................................... .................. 16
Interruptions ............................................. ........................... ............................................. 16
Host Interface Summary .................................. ........................... .................................. ... 16
VI.1.1.1
VI.1.1.2
VI.1.1.3
VI.1.1.4
VI.1.1.5
VI.1.1.6
VI.1.2
VI.1.3
VI.2
VI.2.1
COMMAND SET .......................................... ........................... ........................... .............. 17
Command Set Summary............................ ........................... ........................... ................ 17
OperationalControl Commands........................................ ........................................... 17
Data Communication Commands ................................. ........................... .................... 17
Digital Loop Back Commands......................................... ........................... .................. 17
Memory Handling Commands................................................... .................................. . 17
Configuration Control Commands................................. ........................... .................... 18
Mafe Control Commands .................................................... ......................................... 18
Tone Generation Commands........................... .................................. .......................... 18
Command Set Short Form................................... .................................. .......................... 19
VI.2.1.1
VI.2.1.2
VI.2.1.3
VI.2.1.4
VI.2.1.5
VI.2.1.6
VI.2.1.7
VI.2.2
VI.3
VI.3.1
VI.3.2
STATUS - REPORTS............................................. ........................... ........................... .... 19
Status....................................................... ........................... ........................... .................. 19
Reports........................................ ........................... .................................. ........................ 19
VI.4
DATA EXCHANGES............................................ .................................. .......................... 19
Synchronous Mode ...................................... .................................................... ................ 20
Transmit ................................ ........................... ................................ ........................... . 20
Receive ................................... ........................... ................................ .......................... 20
HDLC Mode ............................................... .................................................... .................. 20
Serial Exchanges ............................ ................................ ........................... ...................... 20
VI.4.1
VI.4.1.1
VI.4.1.2
VI.4.2
VI.4.3
APPENDIX
A.
B.
C.
D.
E.
F.
G.
H.
COMMAND SET DESCRIPTION.................................. ........................... ........................ 21
STATUS DESCRIPTION.................................................. ........................... ..................... 37
TYPICAL BER PERFORMANCES............................................ ........................... ............ 41
DEFAULT CALL PROGRESS TONE DETECTORS................................. ....................... 41
DEFAULT ANSWER TONE DETECTORS................................................ ...................... 42
ELECTRICAL SCHEMATICS..................................... ........................... ........................... 42
TONE DETECTOR .................................... ........................... ........................... ................ 46
BUFFER OPERATIONS .......................... ........................... ............................................. 50
PACKAGE MECHANICAL DATA .............................. ........................... ......................................... 52
3/55
ST75C50
I - GENERAL DESCRIPTION
This highly integrated modem consists of 2 chips,
the first being a dedicated DSP (ST75C500), the
second being the ST7543 MAFE. Emphasis has
been put on performance and size/power con-
sumption for portable applications.The chipset is
supplied in either single package or two package
form.
specific modes of operation can be added and
easily updated.Code development is made simple
via a slot in PC development card and is fully
supported by SGS-THOMSON (STI8933 PC-
EMU).
The voice mode allows for implementation of en-
hanced telephony functions such as answering
machines. Incoming samples from the line are
PCM-A-law coded and are writteninto the dualport
RAM. The outgoing samples are decompressed
using the same A-law and are output to the tele-
phone line.
This product gives a high performance modem
conformant to CCITT recommendations V.32bis,
V.17, V.33, V.32, V.29, V.27ter, V.22bis, V.22, V.21
and V.23. Also Bell 212Aand 103.
As a data modem the ST75C50 can operate at
14400, 12000, 9600, 7200, 4800, 2400, 1200, 300
or 75 bits per second as standard. As a fax, the
ST75C50 fully supports group 3 sendand receive
speeds of 14400, 12000, 9600, 7200, 4800 and
2400 bits per second.
The modem standard products are packaged in
either a 160 pin plastic quad flatpack or two flat-
packs for low profile applications (one 44 pin and
the other 80 pin).
For customer specific code requiring access to
external memory, a 160 pin flatpack containing the
DSP anda 44pin flatpackcontainingthe MAFE are
also available (type numbers ST18933 and
ST7543 respectively).
Programmable features allow the product to be
tailored to a wide range of high speed modem
requirements.Inaddition, to add to the flexibility of
this product,thecustomer can develop,ona similar
hardware platform to the standard product, pro-
prietry code for ROMing into the memory of the
DSP. If required, ability to access external memory
of upto 64K x 32 is given such that customer
Further information on the DSP (STI8933) and
MAFE (ST7543) can be found in the relevant
datasheets
II - PIN CONNECTIONS
II.1 - ST7543CQFPTop View (TQFP44)
44 43 42 41 40 39 38 37 36 35 3 4
1
33
32
31
30
29
28
27
26
25
24
23
TxD1
TxD0
AGNDT
VCM
2
FSX
3
AVDD
BCLKX
EYEY
4
RxA2
RxA1
AGNDR
5
6
DGND2
DVDD2
MAFE
7
V
REFP
V
REFN
EYEX
8
9
RxCLK
RxHSCLK
RxSYNC
TEST3
TEST1
NRESET
10
11
12 13 14 15 16 17 18 1 9 20 21 22
4/55
ST75C50
II.2 - ST75C500CQFPTop View (TQFP80)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SD2
SD1
VDD IN3
BCLKR2
BCLKX2
VSS OUT3
2
3
SD0
4
SA6
5
SA5
VDD
OUT3
6
SA4
DR2
7
SA3
DX2
8
SA2
P0
9
VSS ROM
VDD IN2
VSS IN2
SA1
P1
10
11
12
13
14
15
16
13
14
15
16
VDD RAM
VDD PER
VSS CLK
VDD CORE
P2
DSP
SA0
SCS
SR/W
P3
SDS
BE0
SDTACK
VSS OUT2
SINTR
HALT - NOP
BE1
BS0
RESET
VSS CORE
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
II.3 - ST75C500PQFPTop View (PQFP80)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VSS OUT1
SD3
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
BCLK1
2
VSS IN3
VDD IN3
BCLKR2
BCLKX2
VSS OUT3
VDD OUT3
DR2
SD2
3
SD1
4
SD0
5
SA6
6
SA5
7
SA4
8
SA3
9
DX2
SA2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P0
VSS ROM
VDD IN2
VSS IN2
SA1
P1
VDD RAM
VDD PER
VSS CLK
VDD CORE
P2
DSP
SA0
SCS
SR/W
SDS
P3
BE0
SDTACK
VSS OUT2
SINTR
HALT - NOP
MCI
BE1
BS0
RESET
VSS CORE
EXTAL
XTAL
RDYS
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
5/55
ST75C50
II.4 - ST18933PQFPTop View (PQFP160)
160159158157156155154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121
1
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
SA2
SA1
P3
2
P2
3
SA0
P1
4
SD7
P0
5
SD6
BE0
6
SD5
BE1
7
SD4
BS0
8
SD3
LP
9
SD2
RESET
HALT
NOP
LPACK
CS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SD1
SD0
SCS
SR/W
SDS
SDTACK
SINTR
IA15
IA14
IA13
IA12
IA11
IA10
IA9
XTAL
EXTAL
WR
RD
INCYCLE
CLKOUT
VSS OUT
VDD PER
VSS CLK
VDD CORE
VDD OUT
A15
DSP
(for Custom Option)
98
97
IA8
96
IA7
95
IA6
A14
94
IA5
A13
93
IA4
A12
92
IA3
A11
91
IA2
A10
90
IA1
A9
89
IA0
A8
88
VDD IN
VSS IN
VDD OUT
VSS OUT
ID31
ID30
ID29
ID28
A7
87
A6
86
A5
85
A4
84
A3
83
A2
82
A1
81
A0
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
6/55
ST75C50
II.5 - ST75C50 Top View (PQFP160)
160 159 158 157 156 155154 153 152 151 150 149 148 147 146 145 144143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
1
120
NC
NC
NC
NC
2
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
NC
3
XTAL11
XTAL10
XTAL2
TxSCLK
DVDD3
DGND3
TxCLK
TxHSCLK
TxSYNC
TxRCLK
RxRCLK
NC
4
NC
BCLKR2
VSS
5
6
7
VDD
VSS
8
9
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
VDD
MPMC
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SD7
SD6
SD5
SD4
SD3
SD2
NC
RxSYNC
RxHSCLK
RxCLK
EYEX
DVDD2
DGND2
EYEY
DATAPUMP MONOPACKAGE
98
BCLKX
FSX
97
96
TxDO
95
TxDI
94
SD1
SD0
DX1
DR1
FS1
BCLK1
P3
93
92
SCS
SR/W
SDS
SDTACK
SINTR
VDD
91
90
89
P2
88
P1
87
P0
86
VSS
BE0
BE1
NC
85
VDD
84
VSS
83
NC
NC
NC
82
NC
81
NC
NC
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
7/55
ST75C50
III - PIN DESCRIPTION
III.1 - Host Interface
The exchanges with the control processor proceed through a 64 Bytes DUAL port RAM shared between
the DSP and the Host. The pins associated with this interface are :
Pin Name Type
Description
SD0..SD7
I/O
System Data Bus. 8-bit data bus used for asynchronous exchanges between the DSP and the
Host through the DUAL port RAM.
SA0..SA6
SDS
I
I
System address bus. 7-bit address bus for DUAL port RAM.
System Data Strobe. Active low. Synchronizes all the exchanges.
System Read/Write
SR/W
I
SCS
I
System Chip Select. Active low
SDTACK
SINTR
O
O
System bus Data Acknowledge. Active low.
System Interrupt Request. Active low. This signal is asserted by the DSP and negated by the
Host.
RESET
I
I
Reset Active low
RING/BS0
Ring detect signal : awakens data-pump from its sleep mode.
III.2 - Serial Interface
The transmit and receive synchronous data exchanges between the DSP and microprocessor can pass
via the Simplified Synchronous Serial Interface. Two pins are allowed for the data :
Pin Name Type
Description
Description
DR2
DX2
O
I
Synchronous Data Output
Synchronous Data Input
III.3 - Analog Interface
Pin Name Type
TXA1
TXA2
RXA1
RXA2
VCM
O
O
I
Transmit Analog Output 1
Transmit Analog Output 2
Receive Analog Input 1
I
Receive Analog Input 2
I
Analog Common Voltage (nominal +2.5V)
Analog Negative Reference
Analog Positive Reference
VREFN
VREFP
O
O
III.4 - Eye Pattern Interface
A simplified dual 8-bit DAC is provided for eye pattern display.
Pin Name Type
Description
EYEX
EYEY
O
O
Analog Output for Constellation Display. (X AXIS)
Analog Output for Constellation Display. (Y AXIS)
8/55
ST75C50
III.5 - Clock Interface
A complete set of bit and baud clocks are provided to allow the implementationof all the modem functions :
Pin Name Type
Description
TxSCLK
I
Transmit Terminal Clock. This signal is used to synchronize the Transmit bit Clock with an
external Transmit bit Clock. When not used this pin must be grounded or disabled by software
TxCLK
TxRCLK
RxCLK
O
O
O
O
Transmit bit Clock
Transmit Baud Clock. (Default 2400 Hz)
Receive bit Clock
RxRCLK
Receive Baud Clock. (Default value 2400 Hz)
In FSK mode TxCLK is 7200 Hz, RxCLKis 9600 Hz.
III.6 - Auxiliary Interface
A set of auxiliary signals are provided to simplify the DAA Interface. This is made by a three line General
Purpose Parallel Input/Output.
Pin Name Type
Description
PO
P1
P2
I/O
I/O
I/O
Parallel Input/Output 0
Parallel Input/Output 1
Parallel Input/Output 2
III.7 - Miscellaneous
Pin Name Type
Description
XTAL
EXTAL
O
I
Internal oscillator Output. Left open if not used.
Internal oscillator Input, or External Clock
EXTAL Divide by 2
CLKOUT
0
Pin Name Type Description
XTAL10
XTAL11
XTAL2
I
I
MAFE oscillator input
MAFE oscillator input . Must be connected to XTAL10.
MAFE oscillator output
O
Note : The nominal external clock frequency of the DSP is 36.864MHz. The nominal external clock frequency of the MAFE is 18.432MHz
with a precision better than ±5.10-5 (and is output from the DSP on the CLKOUT Pin in the ST75C50 chipset).
When in Sleep Mode the CLKOUT clock is not available
III.8 - Interconnection
A set of signals is use for interconnection between the DSP and the Analog Front End. Refer to the
correspondingappendix for the complete Electrical Schematics.
Pin Name
Description
DSP
P3
MAFE
NRESET Reset of the Analog Front End
BCLKR Receive Serial I/O Clock
BCLK0
FS0
FSR
RXDI
RXDO
Receive Serial I/O Frame Synchro
Receive Serial I/O Input
DX0
DR0
Receive Serial I/O Output
BCLK1
FS1
BCLKX Transmit Serial I/O Clock
FSX
TXDI
TXDO
Transmit Serial I/O Frame Synchro
DX1
Transmit Serial I/O Input
Transmit Serial I/O Output
DR1
BCLKX2 RXCLK Receive Bit Clock
BCLKR2 TXCLK Transmit Bit Clock
BE0
BE1
RXRCLK Receive Baud Clock
TXRCLK Transmit Baud Clock
9/55
ST75C50
Sections III. 9, 10 and 11 relate to the ST18933 for customer specific code.
III.9 - Memory Interface
A set of Digital signals is needed if using a 8K*8 (100ns access time) for Bulk Delay.
Pin Name Type
Description
A0..A15
D0..D15
CS
O
I/O
O
Address Bus (up to 64K)
Data Bus
Chip Select, Active when the DSP Access the Bulk Delay
Write, Active low
WR
O
RD
O
Read, Active low
III.10 - Boundary Scan Interface
A set of 13 signals are dedicated for Testing the DSP. These signals can be used in a development phase,
associated with SGS-THOMSON ST18932 Boundary Scan Development Tools, to Debug the application
Hardware and Software. If not used the correspondinginput signals must be grounded.
Pin Name Type
Description
SCIN
SCCLK
SCOUT
BOS
I
I
Scan Data Input
Scan Clock
O
I
Scan Data Output
Begin of Scan Control
End of Scan
EOS
I
MC0..MC2
SBACK
MCI
I
Mode Control
O
O
O
Software Breakpoint Acknowledge
Multicycle Instruction
Ready to Scan Flag
RDYS
III.11 - Open Version Interface
The ST18933 DSP 160 pin chip allows the use of an external program memory. This memory can be a
ROM Memory (25ns access time) or a RAM Memory (25ns access time) that can be downloaded, via the
DUAL Port Ram, by the host processor (refer to the ST18933 data sheet).
Pin Name Type
Description
ID0..ID31
IA0..IA15
EPM
I/O
O
O
O
I
Instruction Data Bus
Instruction Address Bus
Extenal Memory Select, Active low
Extenal Memory Write, Active low
WPM
MP/MC
Select Internal ROM Program (MP/MC = 0) or External ROM/RAM Program (MP/MC = 1)
10/55
ST75C50
IV. - ELECTRICAL SPECIFICATIONS
Unless otherwise noted, electrical characteristics are specified over the operatingrange. Typical value are
given for VDD = +5V and Tamb = 25oC and for nominal crystal frequency of 36.864 MHz.
IV.1 - Maximum Ratings (referenced to GND)
Symbol
VDD
VI, VIN
II, IIN
IO
Parameter
Value
-0.3, +7.0
-0.3, VDD + 0.3
± 1
Unit
V
DC Supply Voltage
Digital or Analog Input Voltage
Digital or Analog Input Current
Digital Output Current
V
mA
mA
mA
oC
± 20
IOUT
TA
Analog Output Current
± 10
Operating Temperature
0, +70
Tstg
Storage Temperature (plastic)
Maximum Power Dissipation
-40, +125
oC
Ptot
mW
Stresses above those hereby listed may cause damage to the device. The ratings are stress related only and functional operation of the device
in conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Standard MOS circuits handling procedure should be used to avoid possible damage to the
device.
IV.2 - DC Characteristics
V
DD = 5V ± 5%, GND = 0V, TA = 0 to 70oC (Unless otherwise specified).
IV.2.1 POWER SUPPLY AND COMMON MODE VOLTAGE
Symbol
VDD
Parameter
Min.
Typ.
5
Max.
Unit
V
Supply Voltage
Supply Current
4.75
5.25
IDD
130
mA
mA
V
IDD-LP
VCM
Supply Current in Low Power Mode
Common Mode Voltage
VDD/2 -5%
VDD/2
VDD/2 +5%
IV.2.2 - DIGITAL INTERFACE
All digital pins except XTAL pins.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
VIL
VIH
II
Low Level Input Voltage
High Level Input Voltage
-0.3
2.2
-10
2.8
0.8
V
Input Current VI = VDD or VI = GND
High Level Output Voltage (ILOAD = 2mA)
Low Level Output Voltage (ILOAD = 2mA)
Three State Input Leakage Current (GND < VO < VDD
Input Capacitance
0
+10
µA
V
VOH
VOL
IOZ
CIN
0.4
50
V
)
-50
0
5
µA
pF
IV.2.3 - ANALOG INTERFACE
Symbol
Parameter
Min.
Typ.
2.50
200
Max.
Unit
V
VREF
Differential Reference Voltage Output = VREFP - VREFN
VREF Temperature Coefficient
2.40
-300
200
2.60
Tempco
VCMO-IN
VDIF-IN
ppm /°C
mV
Input Common Mode Offset V = (RXA1+RXA2)/2 - VCM
Differential Input Voltage RXA1 - RXA2
300
2 Vref
200
Vpp
mV
VCMO-OUT
VDIF-OUT
VOFF-OUT
Output Common Mode Voltage Offset = (TXA1+TXA2)/2 - VCM
Differential Output Voltage TXA1 - TXA2
2 Vref
100
Vpp
mV
Differential Output DC Offset (TXA1 - TXA2)
-100
11/55
ST75C50
Symbol
Rin
Parameter
Min.
Typ.
Max.
Unit
kΩ
Ω
Input resistance RXAx
Output resistance
100
Rout
TXAx
EYEx
TXAx
EYEx
TXAx
EYEx
20
50
kΩ
kΩ
MΩ
pF
pF
V
RL
CL
Load resistance
10
1
Load capacitance
Output voltage EYEx
50
50
Vout
GND
VDD
IV.3 - AC Electrical Characteristics
IV.3.1 - DUAL PORT RAM HOST READ-CYCLE TIMING
Figure 1
SAD [0 .. 6]
SR/W
Valid Address
5
1
SDS
3
6
SD [0 .. 7]
SDTACK
Valid Data
7
2
4
Number
Description
Min.
Typ.
Max.
Unit
ns
1
2
3
4
5
6
7
Address, SR/W, SCS setup time
SDTACK Acknowledge
SDTACK prepositionment time
Data Strobe delay
5
235(1)
30
ns
ns
50(2)
ns
Address Hold time
0
0
0
ns
Data Hold time
ns
SDTACK Hold time
10
ns
Notes : (1) this value is given for a DSP Cycle time of 56ns. For different Cycle Time tc this value is 4 * tc + 10 ns.
(2) if the application does not use the SDTACK signal, the minimum SDS low state must be 300ns (or 5 * tc).
12/55
ST75C50
IV.3.2 - DUAL PORT RAM HOST WRITE-CYCLE TIMING
Figure 2
SAD [0 .. 6]
Valid Address
SR/W
14
10
SDS
13
15
SD [0 .. 7]
SDTACK
SINTR
Valid Data
16
11
12
17
Number
10
Description
Min.
Typ.
Max.
Unit
ns
Address, SR/W, SCS setup time
SDTACK Acknowledge
Data Strobe Delay
5
11
235(1) ns
12
50(2)
10
0
ns
ns
ns
ns
13
Data Setup Time
14
Address Hold time
15
Data Hold time
0
16
SDTACK Hold time
SINTR Clear Delay
0
10
66(3)
ns
ns
17
0
Notes : (1) this value is given for a DSP Cycle time of 56ns. For different Cycle Time tc this value is 4 * tc + 10 ns.
(2) if the application does not use the SDTACK signal, the minimum SDS low state must be 300ns (or 5 * tc).
(3) the maximum value is tc + 10ns.
13/55
ST75C50
V - FUNCTIONAL DESCRIPTION
V.1 - System Architecture
by virtue of the MAFE architecture. The far end
echo requires either an external low cost 8kx8-
100ns memory (for the customisable product
STI8933),or the allocationof an equivalentamount
of RAM in the controller memory space. It also
sustains up to 10Hz of frequency offset on the far
end echopath without degradationof performance.
The system is based on a two-chip set. The first
chip is the ST75C500 dedicated DSP handling all
the signal processing routines for transmission,
reception and echo cancellation on modem sig-
nals. It also holds the tone generators and detec-
tors. Alternatelythe ST18933 DSP is available for
customer specific operations. The second chip is
the ST7543delta-sigmaMAFE, which performsthe
AD/DA conversions as well as the signal pre or
post-filtering, and the sampling interpolation on the
echo cancellationpath.
V.3.4 - RECEIVER DESCRIPTION
The receiver section handles complex signals and
uses a fractionally spaced complex equalizer. It is
able to cope with distant modem frequency drifts
up to 10-4 as specified in the CCITT recommenda-
tions. It also compensates for phase jitter at multi-
ple and simultaneous frequencies.
The chipset allows thedesignof acompleteV32bis
data-pump without any external component. A ver-
satile dual port RAM allows an easy interface with
most popular micro-controllers.
V.3.5 - TONE GENERATOR DESCRIPTION
Four tonescan be simultaneouslygenerated bythe
ST75C50. The tones are determined by their fre-
quencies and by the output amplitude level. A set
of specific command is also available for DTMF
generation (using two of the four generators avail-
able).
V.2 - Chip Set Interconnect Circuitry
Please refer to appendixF for a detailed schematic
of the chip set interconnect circuitry.
V.3 - Operation
V.3.1 - MODES
V.3.6 - TONE DETECTOR DESCRIPTION
16 tones can be simultaneously detected by the
ST75C50. Each of the tones to be detected is
defined by the coefficients of a 4th order program-
mable IIR. Detection thresholds are also program-
mable from -45dBm up to -10dBm.
The modemimplementationisfullycompatible with
many popular CCITT and Bell recommendations.
The modulation can be either Trellis Coded Modu-
lation (TCM) as in V.33 14400, 12000, V.32bis
14400, 12000, 9600, 7200, V.32 9600 bps rates,
Quadrature Amplitude Modulation (QAM) as in
V.32bis 4800, V.32 9600, 4800, V.22bis2400, Dif-
ferential Phase Shift Keying (DPSK) as in V.22
1200, Bell212A1200 bpsrates, or FrequencyShift
Keying (FSK) as in V.21, V.23 and Bell 103 modes.
Both the bit rate and the trellis options are deter-
mined during the initial modem handshake se-
quence. V.29, V.27ter and V.17 are also available
for FAX transmission. Other modes of operation
include tone and DTMF detection or generation
and speech mode.
V.3.7 - DTMF DETECTOR DESCRIPTION
A DTMF detector is included In the ST75C50, it
permits detection of valid DTMF digits. A valid
DTMF digit is defined as a dual tone with total
power higher than -35dBm, duration greater than
40ms and differential amplitude within 8dB (posi-
tive or negative).
V.3.8 - VOICE MODE DESCRIPTION
The ST75C50 voice mode allows the implementa-
tion of enhanced telephony functions such as an-
swering machines. Incoming samples from the line
are PCM-A-law coded and are written into the dual
port RAM. The outgoing samples are decom-
pressedusing thesame A-lawand are outputto the
telephone line.
V.3.2 - TRANSMITTER DESCRIPTION
The signal pulses are shaped in a dedicated filter
combined with a compromise transmit equalizer
suitedfor transmissionover stronglydistortedlines.
3 different compromise equalizers are available
and can be selected by software. User defined
transmit equalizers can be downloaded in the DSP
RAM.
V.3.9 - ANALOG LOOP BACK TEST MODE
In any transmission standard and any data format,
the ST75C50 can be configured for analog loop
back test.
V.3.3 - ECHO CANCELLER DESCRIPTION
V.3.10 - DIGITALLOOP BACK TEST MODE
These loop back modes comply with the test loop
2 of the CCITT V.54 recommendation for V.32 and
V.32bis. For V.22 and V.22 bis thedigital loop back
modes comply with these recommendations.
The echo cancellerconsists of a near end and a far
end echo canceller. Both are fractionally spaced
and achieve a high cancellation of the echo paths.
The receive signal reconstruction is purely digital
14/55
ST75C50
V.3.11 - SLEEP POWER MODE
- the command area,
- the report area,
- the status area,
- the bulk delay exchange area,
- the data buffer areas,
Sleep state can be entered using a host command.
Activating thereset signalor ring interruptwill wake
up the data-pump. When in sleep mode, the dual
port RAM is unavailable and the clocks are dis-
abled. When the pump wakes up it issues an
interruption IT5 when ready to operate.
VI.1.1 - MAPPING
VI.1.1.1 - Command Area
V.4 - Modem Interface
V.4.1 - ANALOG INTERFACE
The command area is located from $00 to $04.
Address $00 holds the command byte COMSYS,
and the four next locations hold the parameters
COMPAR[0..3]. The command parameters must
be entered before the command word is issued.
Once the command has been entered, the com-
mand byte is reset and an acknowledge report is
issued. A new command should not be issued
before theacknowledgecounterCOMACKisincre-
mented. The command exchangerate has a maxi-
mum of 2400 Hz.
The modem designermust provide a proper hybrid
interface to the ST75C50. An example of hybrid
design isgiven inappendix.The inputsand outputs
of the MAFE are differential, thus achieving better
noise immunity.
V.4.2 - HOST INTERFACE
The host interface is seen by the micro as a 64x8
RAM (Motorola bus), with additional registers ac-
cessible throughan 7-bit address space.This RAM
can be used for data transmission using the SE-
RIAL command.
VI.1.1.2 - Report Area
The report area is located from address $05 to
address $07. Location $05 holds the acknowledge
counter COMACK. Each time a command is ac-
knowledged, the report bytes COMREP[0..1] (if
any) are written by the ST75C50 into locations $06
and $07, and the content of COMACK is incre-
mented. This counterallows an acuratemonitoring
of the command processing by the ST75C50.
V.4.3 - MEMORY INTERFACE
In customapplication using the STI8933 an exter-
nal bus givesaccess to a 8Kx8 100nsRAM for Bulk
delay storage. External total data space is 48K.
V.4.4 - AUXILIARYPARALLEL INTERFACE
The auxiliaryparallel interface is a generalpurpose
3-bit parallel interface, which carries various sig-
nals, used by the controller and the analog part of
the modem. Each pin can be independently pro-
grammed for input or output.
VI.1.1.3 - Status Area
The statusareais located from address$08to $0A.
The error status word SYSERR is located at ad-
dress $08. This error status word is updatedeach
time an error conditionoccurs. An optionalinterrup-
tion IT0 may be triggered as well in the case of an
error condition. Location $09 and $0A holds the
general status bytes STATUS[0..1]. The meaning
of the bits depends of the mode of operation, and
is described in Appendix B. The third byte at ad-
dress $0B holds the QualityMonitor byte STAQUA.
V.4.5 - AUXILIARYSERIAL INTERFACE
The auxilliary serial interface is a serial synchro-
nous I/O, which carries the bit data flow. When
required, asynchronous serial mode can be
achieved by adding the TS7538 Async/Sync con-
verter.
V.4.6 - EXE PATTERN CONVERTERS
The output from these two D to A converters pro-
vides direct display of the constellation.
VI.1.1.4 - OptionalStatus Area
The user can program (through the DOSR com-
mand) the three locations STAOPT[0..2] of the
Optional Status Area ($0C to $0E) for the real time
monitoring of four arbitrary memory locations.
VI - USER INTERFACE
VI.1 - Dual Port Ram Description
VI.1.1.5 - Bulk Delay Exchange Area
This area is reserved for V.32 / V.32bis storage of
Far Endechocanceller symbols. Refer to Appendix
H and application note.
This area has two sub-sections :a flagging section
($0F to $13) and a bulk data area ($14 to $1B).
Location $0F holds the bulk data buffer status
SYMSTA. Locations $10 and $11 (resp. $12 and
$13) contain a pointer to the bulk data buffer SY-
The dual port RAM is the standard interface be-
tween the controller and the ST75C50, for either
commands or data. This memory is addressed
through a7-bit addressbus.Thelocationsfrom$00
to $3F are RAM locations,while locations from $40
to $50 are control registers dedicated to the inter-
rupt handling.
Several functional area are defined in the dual port
RAM ,namely :
15/55
ST75C50
MADR[0..1] (resp. SYMADT[0..1]), in the controller
space, which should receive (resp. send) the next
group of 8 delayed symbols. The ST75C50 man-
ages thus an area of 4k bytes in a circular address-
ing mode inside the controller memory space. The
buffer SYMBUF[0..7] containing the symbols re-
ceived or sent to the controller is located from $14
to $1B.
IT5 Power Down Mode : the ST75C50 has been
awakened by a low level on the BS0/RING
Pin. The host has to reset the ST75C50 by
the RESET signal.
IT6 Command Acknowledge : the ST75C50 has
read the last command entered by the host,
incremented the command counter
COMACK, and is ready for a new command.
VI.1.1.6 - Data Buffer Area
VI.1.3 - HOST INTERFACE SUMMARY
The Data Buffer Area is shared by a Data Buffer
Status Area (from $1C to $1F) and a Data Area
(from $20 to $3F). The data area is made of two
double 8-byte buffers. Each of the four buffers is
attached to a Status byte. The meaning of the
status byte depends on the selected mode.
Address
(hex)
Size
Description
Mnemonic
(Byte)
COMMAND AREA
$00
Command
1
4
COMSYS
COMPAR[0..3]
$01-$04 Command
Parameters
REPORT AREA
VI.1.2 - INTERRUPTIONS
$05
Acknowledge
Counter
1
2
COMACK
The controller can generate 7 interrupts to the
ST75C50, and the ST75C50 can generate 7 inter-
rupts for the controller. The interrupt handling is
made with a set of registers located from $40 to
$50.
$06-$07 Report
COMREP[0..1]
STATUS AREA
$08
$09
$0B
Error Status
1
2
1
3
SYSERR
General Status
Quality Monitor
STATUS[0..1]
STAQUA
The interruptionsgeneratedby the ST75C50come
from seven different sources. Once the ST75C50
rises an interrupt, a signal is sent to the controller.
The controllerhas then to process theinterrupt and
clear it. The interrupt source can be examined in
the Interrupt Source Register ITSCRC located at
$50. According to this status byte, the interrupt
source can be determined.Then, writing at one of
the memory location $40 to $46 (Reset Interrupt
Registers ITREST[0..6]) will reset the correspond-
ing interrupt (and thus acknowledge it). These
seven sources of interruptions can be masked
globally or individually using the Interrupt Mask
Register ITMASK located at $4F.
$0C-$0E Optional Report
STAOPT[0..2]
BULK DELAY AREA
$OF
Symbol Buffer
Status
1
2
2
8
SYMSTA
$10-$11 Symbol Rx
SYMADR[0..1]
SYMADT[0..1]
SYMBUF[0..7]
Buffer Pointer
$12-$13 Symbol Tx
Buffer Pointer
$14-$1B Symbol Buffer
DATA AREA
$1C
$25
$2E
$37
Data Rx Buffer 0
Status
1
1
1
1
DTRBS0
DTRBS1
DTTBS0
DTTBS1
Data Rx Buffer 1
Status
Data Tx Buffer 0
Status
The 7 series interrupt sources are :
IT0 Error/Warning: an error hasoccurred and the
error code is availablein the error status byte
SYSERR. This byte can be selectively
cleared by the CSE command.
IT1 Bulk Delay : the bulk delay buffer requires an
action from the controller, for emptying it and
for filling it with symbols.
Data Tx Buffer 1
Status
$1D-$24 Data Rx Buffer 0
$26-$2D Data Rx Buffer 1
$2F-$36 Data Tx Buffer 0
$38-$3F Data Tx Buffer 1
8
8
8
8
DTRBF0[0..7]
DTRBF1[0..7]
DTTBF0[0..7]
DTTBF1[0..7]
IT2 Tx Buffer : each time the ST75C50 frees a
buffer, this interrupt is generated.
IT3 Rx Buffer : each time the ST75C50 has filled
a buffer, this interrupt is generated.
IT4 Status Byte : the modem status byte has
changed and has to be checked by the
controller.
INTERRUPT AREA
$40-$46 Reset Interrupt
7
1
1
ITREST[0..6]
ITMASK
Register
$4F
$50
Interrupt Mask
Registe
Interrupt Source
Register
ITSRCR
16/55
ST75C50
VI.2 - Command Set
CSE
Clear Status Error. Selectively clears the
Error status byte SYSERR. Parametric
command.
The Command Set has the following attractive
features :
- user friendly with easy to remember mnemonics.
- possibility of straight forward expansion with new
commands to suit specific customer require-
ments.
SETGN Set gain. This command sets the global
gain factor, which is used for the transmit
samples. Parametric command.
STOP FAX Stop. Stop FAX half duplex
transmitter. Non parametric command.
- easy upgrade of existing software using previous
modem based SGS-THOMSON products.
SYNC FAX Synchronize. Start/Stop of FAX half
duplex receiver. Parametric command.
The command set has been designed to provide
the necessary functional control on the ST75C50.
Each command is classified accordingto its syntax
and the presence/absence of parameters. In the
case of a parametric command, parameters must
first be written into the dual port RAM before the
command is issued. Acknowledge and error report
is issued for each command entered.
VI.2.1.2 - Data Communication Commands
XMIT
Transmit data. Enable/disables the
transmission of data. After a XMIT
command, according to the selected
mode (either serial or parallel), the
ST75C50sendsthedata containedeither
in its dual port RAM or fed through the
serial I/O. Parametric command.
VI.2.1 - COMMAND SET SUMMARY
SERIAL Enables/disables the Data Serial Mode.
This command selects the data source,
i.e. either parallel or serial. The parallel
mode uses a part of the dual port RAM as
a double buffer.The serial modeuses the
serial synchronous I/O. Parametric
command.
VI.2.1.1 - Operational Control Commands
INIT
Initialize. Initialize the modem chipset. Set
all parameters to their default values and
wait for commands of the control
processor. Non parametric command.
Identify. Return the product identification
code. Non parametric command.
IDT
VI.2.1.3 - Digital Loop Back Commands
SLEEP Turn to Sleep Power Mode. The modem
engine issues a control signal to the
MAFE in order to switch to Sleep Power
Mode, then switches itself into Sleep
Power Mode. Non parametric command.
V54
V.54 Digital Loop Back. Enables/Disables
the transmission and reception of V.54
patterns. This command must be used
only in V.32 bis or V.32 mode. Parametric
command.
HSHK Handshake. Begins the handshake
sequence. The modem chipset carries all
the steps de fined in the CCITT
recommendations. A status report
indicates tothe controlprocessorthe state
of the handshakeand the final negotiated
transmission bit rate. This command only
applies to modes where a handshake
sequence is defined. A CONF command
must have been issued prior to the use of
HSHK. Non parametric command.
RTRA Retrain. Start sending the retrain
sequence as specified in the CCITT
recommendation. This command only
applies to modes where a retrain
sequence is defined. In V.32bis, this
comman d also initiates the rate
nego tiation sequence. Parametric
command.
V22L2 V.2 2/V.22 bis Digital Loop Back.
Enables/Disables the transmission and
reception of V.22 Loop 2 patterns. This
command must be used only in V.22 bis
or V.22 mode. Parametric command.
VI.2.1.4 - Memory Handling Commands
MW
Memory Write. This command is used to
write an arbitrary 16-bit value into the
writable memory location currently
specified by a parameter. Parametric
command.
MR
Memory Read. This command allows the
controller to read any of the ERAM or
CROM (internal and external DSP
memory spaces) locations without
interrupting the processor. Parametric
command.
17/55
ST75C50
CR
ComplexRead. This command allowsthe
PPS
Parallel Port Set. This command allows
the modification of the parallel port
configuration. Each of the four bits of this
port canbeprogrammedeither as an input
or an output. Parametric command.
Parallel Port Read. This command reads
the value of the 4-bit parallel port. The
value is read whetherit is an input or not.
Non parametric command.
Parallel Port Write. This command writes
a 4-bit value into the parallel port. The bits
are maskedaccording totheir input/output
status. Parametric command.
controllerto read at thesame timethereal
and imaginary part of a complex value
stored in a double ERAM or CROM
location. This feature is very interesting
for eye patternsoftware controlas well as
for equalization monitoring. This
command insures that the real and
imaginary part are sampled in the
memory at the same time (integrity).
Parametric command.
PPR
PPW
VI. 2.1.5 - ConfigurationControl Commands
CONF Configures. Thiscommand configuresthe
modem chipset for data transmission and
handshake procedures (if any) in any of
the supported modes. The transmission
parameters are set to their default values
and can be modified with the MODC
command. This command also defines
the parameters in the case of an
automatic standard recognition and the
boundaries of the speed negotiation.
Parametric command.
MODC Modify Configuration. This command
allows modification of part of the
parameters set up by the CONF
command. Parametric command.
BULK Define Symbol Bulk Management. This
command selects the dual port RAM
symbol management,allowing removal of
all external RAM directly connectedto the
DSP. Parametric command.
VI.2.1.6 - MAFE Control Commands
WMR Write MAFE register. Causes the DSP to
write a parameter into a MAFE register.
Parametric command.
VI.2.1.7 - Tone Generation Commands
TONE Select Tone. Progra ms t he tone
generator(s) for the desired default
tone(s). Additional mnemonics provide
quick programming of DTMF tones or
other currently used tones. Parametric
command.
DEFT Define Tone. Programs the tone
generator(s) for arbitrary tone synthesis.
Parametric command.
TGEN Tone Generator Control. Enables or
disables the tone generator(s).
Parametric command.
IV.2.1.8 Tone Detection Commands
DOSR Define Optional Status report. This
command allow the modification of the
optionalstatus report located in the status
area of the dual port RAM. One can thus
select a particular parameter to be
monitored during all modes of operation.
Parametric command.
TDRC Read coefficients of tone detection cell.
Parametric command.
TDWC Write coefficients of tone detection cell.
Parametric command.
TDRW Read wiring of tone detection cell.
Parametric command.
TDWW Write wiring to tone detection cell.
Parametric command.
DSIT
Define Status Interrupt. This command
allows the programmation of the status
word bit that will generate an Interrupt to
the controller. Parametric command.
TDZ
Clear the values of tone detection cell.
Parametric command.
18/55
ST75C50
VI.2.2 - COMMAND SET SHORT FORM
JSR
Call a low level Subroutine. Call an
internal subroutine with one parameter.
Mnemonic Value
planation
0X06 INITialization
0X14 IDenTify
INIT
IDT
VI.3 - Status - Reports
VI.3.1 - STATUS
SLEEP
HSHK
RTRA
CSE
0X03 SLEEP mode
0X04 HandSHaKe
The ST75C50 has a dedicated status reporting
area located in its dual port RAM. This allows a
continuous monitoring of the status variables with-
out interrupting the DSP.
0X05 ReTRAin
0X08 Clear Status Error
0X02 SET GaiN
SETGN
XMIT
SERIAL
MW
The first status byte gives the error status. Issuing
of an error status can be also flagged by a mask-
able interrupt for the controller. The signification of
the error codes is given in Annexe B.
0X01 Receive/TransMIT data
0X07 SERIAL mode
0X12 Memory Write
0X10 Memory Read
0X11 Complex Read
0X20 CONFigure
The second and third status bytes give the general
status of the modem. This two byte status can
generate, when a change occurs, an interrupt to
the controller; each bit of that two byte word can be
masked independently.
MR
CR
CONF
MODC
BULK
0X21 MODify Configuration
The fourth byte gives, in real time,a measure of the
reception quality. This information may be used by
the controllerfor retrain purpose.
0X22 Define symbol BULK
management
DOSR
DSIT
0X0A Define Optional Status Report
0X13 Define Status word InTerrupt
0X15 Parallel Port Set
Three other locations are dedicated for custom
status reporting. This status includes, for example,
the handshake phase, the negotiated data rate,
and other items described in Annexe B. The con-
troller can program the ST75C50 for a real time
monitoring of any of its internal RAM location. High
byte or low byte of any word can thusbe monitored.
PPS
PPR
0X16 Parallel Port Read
PPW
0X17 Parallel Port Write
WMR
TONE
DEFT
TGEN
TDRC
TDWC
TDRW
TDWW
TDZ
0X0B Write Mafe Register
0X0C select TONE
VI.3.2 - REPORTS
0X0E DEFine Tone
The ST75C50 features an acknowledge and report
facility. The acknowledge of a command is moni-
tored by a counter COMACK located in the dual
port RAM. Each time a command is executed from
the command area, the ST75C50 will increment
this counter. For instance, when a MR (Memory
Read) command is issued, the data is first written
in the report area, and the counter is incremented
afterwards.Thiswayof processinginsuresthe data
integrity as well as an additional synchronization
between the controller and the data pump.
0X0D Tone GENerator control
0X1A Tone Detect Read Coefficient
0X1C Tone Detect Write Coefficient
0X1B Tone Detect Read Wiring
0X1D Tone Detect Write Wiring
0X1E Tone Detect Zero cell
0X23 Enable/Disable V.54
0X24 Enable/Disable V.22 Loop2
0X25 FAX STOP Transmitter
0X26 FAX SYNChronize Receiver
V54
V22L2
STOP
SYNC
V.4 - Data Exchanges
The ST75C50 accepts two kinds of data ex-
changes : Parallel synchonous through the DUAL
RAM or SERIALsynchronous. Detailed description
of the Data Buffer Exchange modes of operationis
available in Annex G.
VI.2.2.1 - Miscellaneous Commands
(for ST18933 with Custom Code)
CALL Call a Subroutine. Call a Subroutine with
one parameter.
19/55
ST75C50
VI.4.1 - PARALLEL DATA MODE
VI.4.1.1 - Transmit
VI.4.1.2 - Receive
The controller should take care of releasing the Rx
buffers before the Data Carrier Detect goes true.
This is made by writing the correct status word in
the Rx Buffer Status 0 and 1. The ST75C50 then
fills the first buffer, and once filled sets the status
word withthe number of bits received. It then takes
control of the second buffer and operates in the
same way. The controller must check the status of
the buffersand empty them. Once the data is read,
the controllermust release the usedbuffer and wait
for the next buffer to be full. Interruptsare available
for an additionalflagging of these events.
The controller must first fill at least the first buffer
of data (Tx Buffer 0) with the bits to be transmitted.
In order to perform this operation, the controller
must first check the Tx Buffer 0 status word
DTTBS0. If this buffer is empty, the controller fills
the data buffer locations (up to 64 bits), and then
writes in DTTBS0 the number of bits contained in
the buffer. The controller can then either proceed
with the second buffer or initiate the transmission
with a XMIT command.
The ST75C50 copies the contents of the data
buffer and then clears the buffer status word in
order to make it again available.The numberof bits
specified by the status word is then queued for
transmission. The process goes on with the two
buffers until an XMIT command stops thetransmis-
sion. After the finishing XMIT command has been
issued, the last buffers are emptied by the
ST75C50.
Error occurs when both buffers are declared full,
and incoming bits still arrive from the line.
Synchronous Data Buffer Exchanges are de-
scribed in Annex H.
VI.4.3 - SERIAL EXCHANGES
The second mode of operation for data exchanges
is the Serial Synchronous Mode. In this mode, the
data I/O is made through a pair of dedicated hard-
ware pins. Asynchronous mode of operation and
full implementation of the V.14 recommendation
can be achieved with the use of the TS7538
Async/sync converter.
Error occurs when both buffersare empty while the
transmit bit queue is also empty. Error is signalled
with an interruption to the controller through the
SYSERR register.
20/55
ST75C50
APPENDIX A : COMMAND SET DESCRIPTION
Commands are presented according to the following form :
COMMAND - Command name meaning
Opcode : hexadecimal digit
X
X
X
X
X
X
X
X
Synopsis
Short description of the functions performed by the command
Parameters
Field Byte Pos. Value
Definition
Name
X
a..b
Explanation of the parameter
Default value
xx *
Field :
Byte :
Pos. :
Name of the addressed bit field.
Index (or address in the dual port RAM) of the parameter byte (from 1 to 4).
Bit field position inside the parameter byte. Can either be a single position (from 0 to 7, 0 being
LSB) or a range.
Value : Possible values for the bit (resp. bit field). range means all values are allowded. A value preceded
by a star means a default value. Values are expressed either under the form of a bit string, or
under hexadecimal format.
Command :
BULK - Enable Symbol Management
Opcode : 22
0
0
1
0
0
0
1
0
Synopsis
BULK allows the use of the DUAL RAM symbol area. This additional task into host firmware is only needed
in V.32/V.32bismode. Using this command allows the removal of all external RAM connected to the DSP
local bus. This mode of operation is mandatory with the single chip ST75C50 package and 80 pin package.
In this command the user sets the virtual memory base address and the top memory address (the base
address must be on a 8 byte boudary and the top address on a 8 byte boudary - 1 eg : 0x67FF).
Parameters
Field
Byte Pos. Value
Definition
BA_ADDR_L
BA_ADDR_H
TO_ADDR_L
TO_ADDR_H
1
2
3
4
0..7
0..7
0..7
0..7
Low byte of the base address
High byte of the base address
Low byte of the top memory address
High byte of the top memory address
21/55
ST75C50
CALL - Call a subroutine
Opcode : 19
0
0
0
1
1
0
0
1
Synopis
For use with custom code in the STI8933 only
CALL allows to execute a part of the DSP firmware with a specific argument.
Parameters
Field
Byte Pos. Value
Definition
C_ADDR_L
C_ADDR_H
C_DATA_L
C_DATA_H
1
2
3
4
0..7
0..7
0..7
0..7
Low byte of the call address
High byte of the call address
Low byte of the argument
High byte of the argument
CONF - Configure for operations
Opcode : 20
0
0
1
0
0
0
0
0
Synopsis
CONF allows the complete definition of the modem operation. It also defines the speed boundariesin the
case of a negotiated rate.
Parameters
Field
Byte Pos. Value
Definition
CONF_TX
1
1..0
00*
01
10
11
DTMF Tone
reserved
Audio : transmit speech signal
Modem : transmit data signal
CONF_RX
1
3..2
00*
01
10
11
Tone detection
DTMF detection
Audio : receive speech signal
Modem : receive data signal
CONF_ALOO P
CONF_PSTN
CONF_AO
1
1
1
4
5
6
0
1
normal mode
Analog loop back mode
0
1
PSTN
Leased line
0
1
Answer mode
Originate mode
22/55
ST75C50
Parameters (continued)
Field
Byte Pos. Value
Definition
CONF_MODE
2
5..0
0
1
2
3
4
5
6
7
8
9
A
B
C
Automode
Bell 103
Bell 212A
V.21
V.23
V.22
V.22bis
V.27ter
V.29
V.17
V.32
V.32bis
V.33
CONF_TX EQ
2
7..6
00
01
10
11
Flat Tx equalizer
TX equalizer #1
Tx equalizer #2
Reserved
(1/2 of M1020)
(1/2 of M1040)
CONF_QAM
CONF_TCM
CONF_300
3
3
3
3
3
3
3
4
4
4
0
1
2
4
5
6
7
0
1
2
0
1
QAM/DPSK only (Automode)
FSK allowed (Automode)
0
1
Trellis coding not allowed
Trellis coding allowed
0
1
300 bps speed not allowed
300 bps speed allowed
CONF_1200
CONF_2400
CONF_4800
CONF_7200
CONF_9600
CONF_12000
CONF_14400
0
1
1200 bps speed not allowed
1200 bps speed allowed
0
1
2400 bps speed not allowed
2400 bps speed allowed
0
1
4800 bps speed not allowed
4800 bps speed allowed
0
1
7200 bps speed not allowed
7200 bps speed allowed
0
1
9600 bps speed not allowed
9600 bps speed allowed
0
1
12000 bps speed not allowed
12000 bps speed allowed
0
1
14400 bps speed not allowed
14400 bps speed allowed
Notes :
1) When receiving the CONF command the modem will reset all the MODC parameters to their default values.
2) The valid combinations of CONF_TX and CONF_RX are defined in the following table, associated with the number of tone
detector cells running at the same time:
RX / TX
TONE
TONE/DTMF
MODEM
not allowed
not allowed
2
AUDIO
16
16
DTMF
4
not allowed
16
4
not allowed
16
MODEM
AUDIO
not allowed
When in modem mode the number of tone detectors allowed is set to 2 if using the SERIAL link and 0 if
using the parallel data management (either Tx or Rx).
23/55
ST75C50
CR - Complex read
Opcode : 11
0
0
0
1
0
0
0
1
Synopsis
CR allows the reading of a complex parameter. The parameter specifies the parameter address (for the
real part : the imaginary part is next location). CR returns the high byte value of both real and imaginary
part of the addressed complex parameter.
Parameters
Field
Byte Pos. Value
Definition
CR_ADDR_L
CR_ADDR_H
1
2
7..0
7..0
Low byte of the 16-bit address
High byte of the 16-bit address
CSE - Clear error status
Opcode : 08
0
0
0
0
1
0
0
0
Synopsis
CSE is used to clear the ST75C50 error status SYSERR byte. It is also used as an acknowledge to the
error condition handler.
Parameters
Field
Byte Pos. Value
0..7
Definition
ERR_MASK
1
Error mask . See report appendix for detailed meaning.
DEFT - Define arbitrary tone
Opcode : 0E
0
0
0
0
1
1
1
0
Synopsis
DEFT programs one of the fourtone generatorfor arbitrarytone generation.Theparameteristhe frequency
of the generated tone in Hertz between 0 and 3600 Hz (expressed in hexadecimal). Frequency above the
half of the transmit sampling clock will be aliased.
Parameters : Example 1000 Hz is represented by 03E8
Field
Byte Pos. Value
Definition
Index of the tone generator (0..3)
TONE_GEN_SL
TONE_FREQ_L
TONE_FREQ_H
TONE_SCALE
1
2
3
4
1..0
7..0
7..0
7..0
Low byte of the frequency
High byte of the frequency (internally masked with 0F)
Amplitude scaling factor (high byte) FF gives the Maximum Amplitude.
24/55
ST75C50
DOSR - Define optional status report
Opcode : 0A
0
0
0
0
1
0
1
0
Synopsis
DOSR specifiesthe address of the parameters to be monitored in the 3 locations STAOPT[0..2] of the dual
port RAM. It also specifies the assignment of the parameter inside the 3 locations.
Parameters
Field
Byte Pos. Value
Definition
STA_OPT_ASS
STA_OPT_ADL
STA_OPT_ADH
STA_OPT_HL
1
2
3
3
0..2
0..7
0..3
7
Index of the STAOPT array
Low byte of parameter address
High byte of parameter address
0
1
Select low byte of parameter
Select high byte of parameter
DSIT - Define status interrupt
Opcode : 13
0
0
0
1
0
0
1
1
Synopsis
DSIT specifies the bit mask used with the STATUS[0] or STATUS[1] byte to generate an interrupt IT4 to
controller. Each time a bit change will append in the general status words, assuming the corresponding bit
mask will be set, an interrupt will be generated.
Parameters
Field
Byte Pos. Value
Definition
Select status word 0 Bit Mask pattern
Select Status word 1 Bit Mask pattern
STA_IT_MSK0
STA_IT_MSK1
1
2
0..7
0..7
Note : The default IT status is 0X3F for STATUS [0] and 0XFF for STATUS [1].
HSHK - Handshake
Opcode : 04
0
0
0
0
0
1
0
0
Synopsis
HSHK is used to command the ST75C50 to begin the handshake sequence processing. The progress of
the handshakeis reported to the control processor.
Parameters : non parametric command
25/55
ST75C50
IDT - Identify
Opcode : 14
0
0
0
1
0
1
0
0
Synopsis
IDT returns the ST75C50 Harware and Software release number.
Parameters : non parametric command
Bits 15 to 12 represent the product identity number. For the 75C50 this is 0
Bits 11 to 4 represent the product software release
Bits 3 to 0 represent the software sub release
INIT - Initialization
Opcode : 06
0
0
0
0
0
1
1
0
Synopsis
INIT forces the ST75C50 to reset all parameters to their default conditions and restart operations.
Parameters : non parametric command
Note: This command makes a software reset of the ST75C50 and so cannot have the regular handshake protocol. It does not increment
the COMACK, nor generate an Interrupt.
JSR - Call a low level subroutine
(For use with custom code in the STI8933 only)
Opcode : 18
0
0
0
1
1
0
0
0
Synopsis
JSR allows execution of DSP firmware with specific argument.
Parameters
Field
Byte Pos. Value
Definition
C_ADDR_L
C_ADDR_H
C_DATA_L
C_DATA_H
1
2
3
4
0..7
0..7
0..7
0..7
Low byte of the call address
High byte of the call address
Low byte of the argument
High byte of the argument
26/55
ST75C50
MR - Memory read
Opcode : 10
0
0
0
1
0
0
0
0
Synopsis
MR allowsthe reading of a 16-bit parameter. The parameter specifies the parameter address.
Parameters
Field
Byte Pos. Value
Definition
MR_ADDR_L
MR_ADDR_H
1
2
7..0
7..0
Low byte of the 16-bit address
High byte of the 16-bit address
MODC - Modify configuration
Opcode : 21
0
0
1
0
0
0
0
1
Synopsis
MODC allows modification of the configuration for special purposes. This command can also apply when
in data mode.
Parameters
Field
Byte Pos. Value
Definition
MODC_V22G
2
3..4
00*
01
10
No guard tone
1800 Hz guard tone
550 Hz guard tone
MODC_FPT
2
2
2
2
2
2..3
4
00*
10
No echo protection tone (FAX only) V29, V27, V33, V17
Long echo protection tone (180ms)
MODC_NOT A
0*
Generate answer tone for handshake (ANSWER MODE)
Wait answer tone (ORIGINATE MODE)
4
Do not wait answer tone (ORIGINATE MODE)
Do not generate answer tone (ANSWER MODE)
1
MODC_NOSA
MODC_NOQA
6
0*
1
Cut answer tone when receiving AA (V.32b)
Continue answer tone
7
0*
1
Enable V.32 bis handshake on quality
Disable handshake on quality
27/55
ST75C50
MW - Memory write
Opcode : 12
0
0
0
1
0
0
1
0
Synopsis
MW allows the writing of a 16-bit parameter. The parameter specifies the address, as well as the value, to
be transferred.
Parameters
Field
Byte Pos. Value
Definition
MW_ADDR_L
MW_ADDR_H
MW_VALUE_L
MW_VALUE_H
1
2
3
4
7..0
7..0
7..0
7..0
Low byte of the 16-bit address
High byte of the 16-bit address
Low byte of the 16-bit value
High byte of the 16-bit value
PPR - Read parallel port
Opcode : 16
0
0
0
1
0
1
1
0
Synopsis
Read parallel port. The values of the 4-bit parallel port is read, whether the port is configured in input or in
output.
Parameters : non parametric command
PPS - Parallel port set
Opcode : 15
0
0
0
1
0
1
0
1
Synopsis
Configure parallel port. Each of the 4 pins of the parallel port can be either programmed for input or for
output.
Parameters
Field
PP_IO0
Byte Pos. Value
Definition
1
1
1
1
0
1
2
3
0*
1
Pin 0 programmed as input
Pin 0 programmed as output
PP_IO1
PP_IO2
PP_IO3
0*
1
Pin 1 programmed as input
Pin 1 programmed as output
0*
1
Pin 2 programmed as input
Pin 2 programmed as output
0
1*
Pin 3 programmed as input
Pin 3 programmed as output
Note: Pin 3 is reserved for MAFE control and therefore must be programmed as an output.
28/55
ST75C50
PPW - Parallel port write
Opcode : 17
0
0
0
1
0
1
1
1
Synopsis
Write to the parallel port. This operation will be effective only if the bits are programmed as outputs.
Parameters
Field
PP_VAL0
PP_VAL1
PP_VAL2
PP_VAL3
Byte Pos. Value
Definition
1
1
1
1
0
1
2
3
Pin 0 logical value
Pin 1 logical value
Pin 2 logical value
1
Pin 3 logical value must be set to 1
RTRA - Retrain
Opcode : 05
0
0
0
0
0
1
0
1
Synopsis
RTRAis usedto force theST75C50 toinitiatea retrain sequenceon thechannel. The parameter determines
the target speed for the retrain.
Parameters
Field
Byte Pos. Value
Definition
RTRA_NEGO
1
1
1
1
1
1
2
2
2
0
1
4
5
6
7
0
1
2
0
1
Retrain (V.22bis, V.32, V.32bis)
Rate Negotiation (V.22bis, V.32bis)
RTRA_NEGO
RTRA_1200
RTRA_2400
RTRA_4800
RTRA_7200
RTRA_9600
RTRA_12000
RTRA_14400
1
0
Trellis coding enabled
Trellis coding not enabled
0
1
1200 bps speed not allowed
1200 bps speed allowed
0
1
2400 bps speed not allowed
2400 bps speed allowed
0
1
4800 bps speed not allowed
4800 bps speed allowed
0
1
7200 bps speed not allowed
7200 bps speed allowed
0
1
9600 bps speed not allowed
9600 bps speed allowed
0
1
12000 bps speed not allowed
12000 bps speed allowed
0
1
14400 bps speed not allowed
14400 bps speed allowed
29/55
ST75C50
SERIAL - Select serial or parallel mode
Opcode : 07
0
0
0
0
0
1
1
1
Synopsis
SERIAL defines the data path, i.e. either serial or parallel.
Parameters
Field
Byte Pos. Value
Definition
TX_SDATA
1
0
0*
1
Use parallel link for Tx data
Use serial link for Tx data
RX_SDATA
1
1
0*
1
Use only serial link for Rx data
Use also parallel link for Rx data
Note : The received bits always go to output pin DX2, even when the Rx_SDATA bit is set.
SETGN - Set output gain
Opcode : 02
0
0
0
0
0
0
1
0
Synopsis
SETGN is a command which sets the scaling factor of the transmit samples. It is used for setting the output
level or for setting the level of the tone generators. The gain value is given in the form of a 2’s complement
16-bit value.
eg :
7FFF
4000
2000
0
0dB
-6dB
-12 dB
mute
Parameters
Field
GAIN_L
Byte Pos.
Value
Definition
1
2
7..0
7..0
range FF* Low byte of the 16-bit gain value
range 7F* Hight byte of the 16-bit gain value
GAIN_H
SLEEP - Turn to sleep mode
Opcode : 03
0
0
0
0
0
0
1
1
Synopsis
SLEEP is used to force the ST75C50 to turn to sleep mode.
Parameters : non parametric command
Note: When receiving this command the ST75C50 will stop processing and so cannot have the regular handshake protocol. It does not
increment the COMACK, nor generate an Interrupt. Anegative level on the RING Pin will awaken the ST75C50, generate an IT5
Power Down Interrupt and execute a Software Reset (idem init).
30/55
ST75C50
STOP - FAX stop transmitter
Opcode : 25
0
0
1
0
0
1
0
1
Synopsis
STOP is used, in FAX modes, to force the ST75C50 to turn-off the transmitter in accordance with the
corresponding CCITT V33/V17/V29/V27recommendation.
Parameters : non parametric command
Note: When receiving this command the ST75C50 will stop sending regular data. In parallel mode this command must be preceded by a
XMIT stop command. After receiving the STOP command the ST75C50 will wait until all the transmit buffers are sent commencing
with the stop sequence.
SYNC - FAX synchronize the receiver
Opcode : 26
0
0
1
0
0
1
1
0
Synopsis
SYNC is used, in FAX modes, to force the ST75C50 to start/stop the receiver in accordance with the
corresponding CCITT V33/V17/V29/V27recommendation.
As soon as the ST75C50 receives the SYNC start command it sets its receiver to detect the FAX
synchronization signal.
This commdand is the equivalentHSHK command for the receiver.
Parameters
Field
Byte Pos. Value
Definition
RX_SYNC
1
0
0*
1
Stop receiver
Start receiver synchronization
TDRC - Tone detector read coefficient
Opcode : 1A
0
0
0
1
1
0
1
0
Synopsis
TDRC read one coefficient of the selected tone detector cell.
Parameters
Field
TD_CELL
Byte Pos. Value
Definition
1
2
0..3
0..7
0..F
Tone detector cell number
TD_C_ADDR
0..B
10
20
Biquad coefficient
Energy coefficient
Static level
other Reserved
The command answer is : low byte of coefficient followed by high byte of coefficient
31/55
ST75C50
TDRW - Tone detector read wiring
Opcode : 1B
0
0
0
1
1
0
1
1
Synopsis
TDRW read wiring of the selected tone detector cell.
Parameters
Field
TD_CELL
Byte Pos. Value
Definition
1
2
0..3
0
0..F
Tone detector cell number
TD_W_ADDR
0
1
Biquad and energy input
Comparator inputs
other Reserved
The command answer is :
a) if TD_W_ADDR = 0 :
- first byte is the node number of signal connected to biquadraticfilter input,
- second byte is the node number of the signal connected to the energy estimator input.
b) if TD_W_ADDR = 1 :
- first byte is the node number of signal connected to comparator negative input,
- second byte is the node number of the signal connected to the comparator positive input.
TDWC - Tone detector write coefficient
Opcode : 1C
0
0
0
1
1
1
0
0
Synopsis
TDWC write one coefficientof the selected tone detector cell.
Parameters
Field
TD_CELL
Byte Pos. Value
Definition
1
2
0..3
0..7
0..F
Tone detector cell number
TD_C_ADDR
0..B
10
Biquad coefficient
Energy coefficient
Static level
20
TD_COEFL
TD_COEFH
3
4
0..7
0..7
Low byte of coefficient
High byte of coefficient
32/55
ST75C50
TDWW - Tone detector write wiring
Opcode : 1D
0
0
0
1
1
1
0
1
Synopsis
TDWW write wiring of the selected tone detector cell.
Parameters
Field
TD_CELL
Byte Pos. Value
Definition
1
2
0..3
0
0..F
Tone detector cell number
TD_W_ADDR
0
1
Biquad and energy input
Comparator inputs
if TD_W_ADDR = 0 (select biquad and energy inputs)
Field
TD_W_ERN
TD_W_BIQ
Byte Pos. Value
Definition
Definition
3
4
0..3F Energy estimator signal input
0..3F Biquad filter signal input
if TD_W_ADDR = 1 (select comparator inputs)
Field
TD_W_CN
TD_W_CP
Byte Pos. Value
3
4
0..3F Negative comparator signal input
0..3F Positive comparator signal input
TDZ - Tone detector clear cell
Opcode : 1E
0
0
0
1
1
1
1
0
Synopsis
TDZ clearsallinternalvariables of oneTonedetectorcellincludingfilterlocal variablesandenergyestimator.
This command must be sent after changing coefficients of a cell to avoid instability.
Parameters
Field
Byte Pos. Value
0..3 0..F
Definition
TD_CELL
1
Tone detector cell number
33/55
ST75C50
TGEN - Enable/disable tone generators
Opcode : 0D
0
0
0
0
1
1
0
1
Synopsis
TGEN causes the ST75C50 to enable or disable the four tone generators.
Parameters
Field
Byte Pos. Value
Definition
TONE_0_ENA
1
1
1
1
0
1
2
3
0*
1
Generator #0 disabled
Generator #0 enabled
TONE_1_ENA
TONE_2_ENA
TONE_3_ENA
0*
1
Generator #1 disabled
Generator #1 enabled
0*
1
Generator #2 disabled
Generator #2 enabled
0*
1
Generator #3 disabled
Generator #3 enabled
TONE - Predefined tones
Opcode : 0C
0
0
0
0
1
1
0
0
Synopsis
TONE programs the tone generatorsfor the predefinedtones. The tone generators #0 and eventually#1
are reprogrammed with this command. Eventualy the tone generator #0 and #1 are enabled. Using an
argument not in the following table will disable tone generator #0 and #1.
Parameters
Field
Byte Pos. Value
Definition
TONE_SELECT
1
5..0
0
1
DTMF 0 (941 & 1336 Hz)
DTMF 1 (697 & 1209 Hz)
DTMF 2 (697 & 1336 Hz)
DTMF 3 (697 & 1477 Hz)
DTMF 4 (770 & 1209 Hz)
DTMF 5 (770 & 1336 Hz)
DTMF 6 (770 & 1477 Hz)
DTMF 7 (852 & 1209 Hz)
DTMF 8 (852 & 1336 Hz)
DTMF 9 (852 & 1477 Hz)
DTMF A (697 & 1633 Hz)
DTMF B (770 & 1633 Hz)
DTMF C (852 & 1633 Hz)
DTMF D (941 & 1633 Hz)
DTMF * (941 & 1209 Hz)
DTMF # (941 & 1477 Hz)
Answer Tone (2100 Hz)
Answer Tone (1650 Hz)
Answer Tone (2225 Hz)
Tone (1300 Hz)
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10*
11
12
13
34/55
ST75C50
V22L2 - V22 loop 2 generator/detector
Opcode : 24
0
0
1
0
0
1
0
0
Synopsis
V22L2 selects the transmission and detection of V.22/V.22bispatternsrequired for remote digital loop back
as definedin the CCITT specification. The STA_V22L bit in the STA_LOOPoptional status word will follow
the detectionof the receiver setting. This command must only be used in V.22 or V.22bis modes.
Note that the STA_V22Abit (alternate ”1010” or ”0101”) in the STA_LOOPis always active.
Parameters
Field
Byte Pos. Value
Definition
V22L2_TX
1
0..1
00*
01
10
11
Data mode
Transmit unscrambled ”1”
Transmit scrambled ”1”
Transmit scrambled ”1010”
V22L2_RX
2
0
0*
1
Detect unscrambled ”1”
Detect scrambled ”1”
V54 - Generator/detector
Opcode : 23
0
0
1
0
0
0
1
1
Synopsis
V.54 selects thetransmission anddetectionof V.54patternsrequiredfor remote digital loop back as defined
in the CCITT specification. The STA_V54D bit in the STA_LOOP optional status word will follow the
detection of the receiver setting. This command must only be used in V.32 or V.32bis modes.
When the transmit generator completes the required pattern it will continue to send the same sequence
and set the STA_V54E bit in the STA_LOOP.
Parameters
Field
V54_TX
Byte Pos. Value
Definition
1
0..1
00*
01
10
11
Data mode
Transmit 2048 V54 scrambled ”0”
Transmit 1948 V54 scrambled ”1”
Transmit 8192 V54 scrambled ”1”
V54_RX
2
0..1
00*
01
10
11
No V54 detection
Reserved
Detect 256 V54 scrambled ”0”
Detect 256 V54 scrambled ”1”
35/55
ST75C50
XMIT - Start/stop transmission
Opcode : 01
0
0
0
0
0
0
0
1
Synopsis
XMIT enables or disables the transmission of the data according to the selected mode (serial or parallel).
Parameters
Field
Byte Pos. Value
Definition
TX_START
1
0
0
1
Stop transmission
Start transmission
WMR - Write MAFE Register
Opcode : 11
0
0
0
1
0
0
0
1
Synopsis
WMR allows the writing of a 8-bit parameter into one of the ST7543 MAFE chip register.
Parameters
Field
Byte Pos. Value
Definition
MWR_DATA
MWR_ADDR
MWR_RXTX
1
2
3
0..7
0..1
0..7
Byte od data
Byte of the 2-bit address
0
<> 0
Acess Tx Register
Access Rx Register
This command must be used to lock the Transmit clock on an external clock or the received clock :
WMR D8 02 00
WMR F8 02 00
WMR C0 02 00
Tx Clock locked on TxSCLK input Pin.
Tx Clock locked on Rx Clock.
Tx Clock free running
36/55
ST75C50
APPENDIX B : STATUS DESCRIPTION
This appendixis dedicated to the ST75C50 report-
ing features.In the followingsections are explained
the commandacknowledge process and the report
and status definitions.
nary part. The CR command insures that the real
and imaginary parts of the desired complex value
are sampled internally at the same time. The ad-
dress given in the parameter field of CR is the
address of the real part.
I - COMMAND ACKNOWLEDGE AND REPORT
I.1 - Command Acknowledge Process
The ST75C50 features an acknowledge process
based on a counter COMACK. On power-on reset,
this counter’s value is set to 0. Each time a com-
mand is executed, the acknowledge counter CO-
MACK is incremented. This allows a precise
monitoring of the command entered and avoids
command collision.
I.2.2 - MR/TDRC/IDT COMMAND/IDT
The report issued by the MR/TDRC command is
followings the same rules as the CR. The report
meaning is :
D7
D6
D5
D4
D3
D2
D1
D0 COMREP[0]
D15 D14 D13 D12 D11 D10 D9
D8 OMREP[1]
D15..D0 is the 16-bit value required by the
MR/TDRC command.
The acknowledge counter is incremented as soon
as the command has been properly executed. Fur-
thermore, the ST75C50 resets the value of the
COMSYS register. The interruption IT6 is raised
just after the counter is incremented.
I.2.3 - PPR COMMAND
The PPR command issues the following report :
0
0
0
0
PP3 PP2 PP1 PP0 COMREP[0]
PP0..PP3 are the values read on the 4 pins of the
parallel port. The result doesn’t take into acccount
the fact that those pins are input or output pins.
In the case of a memory reading command (CR,
MR or PPR), the process is slightly different. The
command entered is executed, the report area is
then filled and the acknowledge counter is incre-
mented afterwards. This insures that the controller
reads the value corresponding to its request. Fig-
ure B1 gives a flowchart of the command acknow-
ledge process.
II - ERROR STATUS
The error status is changed each time an error
occurs or an important change in the data pump
state occurs. Several events are flagged by the
SYSERR byte. They can only be cleared by the
CSE command.
I.2 - Reports Specification
The report section of the Dual Port RAM is dedi-
cated to memoryreading. In responseto a CR,MR,
IDT or PPR command, the value to be read is
transferred to the Report registers COMREP[0..1].
The meaning of the SYSERR byte is :
SYSERR
Field
Pos.
Meaning when set
ERR_TX
0
Tx buffer underflow or improper
buffer status
I.2.1 - CR COMMAND
Issuing a CR command causes the ST75C50 to
dump a specificmemory location in complex mode.
This instruction is particularly useful for equalizer
state analysis or for software eye-pattern display.
The report area has this meaning :
ERR_RX
1
2
RX buffer overflow or improper
buffer status
ERR_SYM
Symbol buffer synchronization
error
ERR_IOCD
ERR_IPRM
3
4
Incorrect opcode
Incorrect parameter for current
command
RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0 COMREP[0]
IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 COMREP[1]
Reserved
Reserved
ERR_RTK
5
6
7
Reserved for future use
Reserved for future use
Real time kernel error
RP7..RP0 is the MSB part of the 16-bit value of the
real part and IP7..IP0 is the MSB part of the imagi-
37/55
ST75C50
III - GENERAL STATUS
The general status is made of two bytes. The first is dedicated to the CCITT circuit monitoring, as well as
some line-side information. The second byte is dedicated to the pump state.
Each status word, when changing, can generatean IT4 interrupt. Usingthe DSIT commandallows the user
to selectively mask the relevant bits. The default values for the mask are 0X3F for STATUS [0] and 0XFF
for STATUS [1].
STATUS[0]
Field
Pos.
Meaning when set
STA_109
0
CCITT circuit 109 on / DCD : when set indicates that valid data are received, when reset the
data are clamped to constant mark.
STA_107
STA_106
1
2
CCITT circuit 107 on / DSR
CCITT circuit 106 on / CTS : when set indicates that the training sequence has been
completed and that any data at TxD (serial Mode) or in the Tx Buffer (paralle Mode) will be
transmitted.
STA_RING
3
Ring detected : when set a ring signal (from 15Hz to 68Hz) is present at the RING Pin. Note
that the precise frequency can be read in the DSP RAM.
STA_CPT0
STA_CPT1
STA_CPT10
STA_109F
4
5
6
7
Call progress tone detector #0 triggered
Call progress tone detector #1 triggered
Band 0 higher in level then band 1
(Low Pass)
(Hi Pass)
(Low > Hi)
Fast Carrier Detect : this signal reflect the carrier energy received on the line according with
the carrier detect threshold and hysteresis
STATUS[1]
Field
Pos.
Value
Meaning
STA_H
1..0
00
01
10
Not in handshake mode
Handshake in progress
Handshake timeout
STA_AT
3..2
4
00
10
11
No answer tone detected
Bell answer tone detected
CCITT answer tone detected/or AA detected
STA_RTRN
0
1
No remote retrain detected V.32/V.22b
Remote retrain detected
STA_SYNC
STA_RNEG
4
5
1
FAX : synchronization in Progress
0
1
No remote rate negotiation detected (V.32b)
Remote rate negotiation detected
STA_CLR
6
7
0
1
No cleardown detected
Cleardown detected
STA_DTMF
0
1
DTMF digit not detected (DTMF Rx mode)
DTMF digit detected
IV - QUALITY STATUS
The STAQUA byte monitors an evaluation of the line quality. It is updated once per baud and its value
ranges from 127 (perfect quality) to 0 (terrible quality). This provides valuable information about the safety
of the transmission (error sensitivity). The Quality Indicator is LSB adjusted.
STAQUA
Field
STA_Q
Pos.
6..0
7
Value
Meaning
0..127 Quality index
Reserved
Reserved for future use
38/55
ST75C50
V - OPTIONAL STATUS
The ST75C50 allows the host to monitor 3 memory locations inside the memory spaces of the DSP. Those
locations are updated once per baud. On Power-on Reset, default locations are preprogrammed for the
STAOPT[0..2] bytes. The meaning of this default setting is :
STAOPT[0..2]
Field
Byte Pos.
Meaning
NEG_MODE
LOOP_STA
HDSK_PHA
0
1
2
7..0 Negotiated speed mode (see below)
7..0 Test loops status (see below)
7..0 Handshake phase (range 0..255)
After configurating the ST75C50 in a Modem mode, by sending a CONF command the default STAOPT
are preprogrammed to :
Default STAOPT[0..2] after a CONF Modem Command
Field
Byte Pos.
Meaning
NEG_MODE
LOOP_STA
HDSK_PHA
0
1
2
0..7 Negotiated speed mode (see below)
0..7 Test loops status (see below)
0..7 Handshake phase (range 0..255)
The NEG_MODEbyte indicates the issue of the rate negotiation. Its meaning is :
NEG_MODE
Field
Pos.
Value
Definition
NEG_PRG
0
0
1
Negotiation in progress
Negotiation completed
NEG_SPEED
4..1
0
1
2
3
4
5
6
7
8
F
Negotiated speed is 300bps
Reserved
Negotiated speed is 1200bps
Negotiated speed is 2400bps
Negotiated speed is 4800bps
Negotiated speed is 7200bps
Negotiated speed is 9600bps
Negotiated speed is 12000bps
Negotiated speed is 14400bps
Negotiation failed
NEG_TREL
NEG_MODU
NEG_STD
5
6
7
0
1
Negotiated mode is not trellis coded
Negotiated mode is trellis coded
1
0
Negotiated mode is FSK
Negotiated mode is QAM/DPSK
0
1
CCITT Std.
Bell Std. (103 or 212A)
The loop status byte provides valuable information about the loop status, for V.22 and V.54 loops. This
status byte must be used in accordance with the V22L2 or V54 commands. Its meaning is :
STA_LOOP
Field
Pos.
0
Meaning when set
V.54 pattern detected : when set, a 256 bit V.54 pattern has been received.
V.54 pattern completed : when set, the transmit V.54 pattern is completed.
V.22bis alternate ”0101” or ”1010” detected (typically 53ms)
V.22bis loop pattern detected (typically 13ms)
STA_V54D
STA_V54E
STA_V22A
STA_V22L
Reserved
1
2
3
7..4
Reserved for future use
39/55
ST75C50
Figure B1
BEGIN
Yes
No
COMSYS = 0
Yes
No
COMMAND
EXIST
CLEAR ANSWER
Invalid Parameter
EXECUTE
COMMANDE
COPY ANSWER
INTO COMREP
SET SYSERR
ERR_IPRM
SET SYSERR
ERR_IOCD
ASSERT
INTERRUPT IT0
ASSERT
INTERRUPT IT0
INCREMENT
COMACK
CLEAR COMSYS
ASSERT
INTERRUPT IT6
END
40/55
ST75C50
APPENDIX C : TYPICAL BER PERFORMANCES
This appendix shows the typical Bit Error Rate curves obtained on lines Flat and US3002, using a TAS
Series II equipmentand a V.56 AGC. Samplesize is 107 bit.
Figure C1 : Typical V32bis BER performances
BER
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
10
13
15
17
19
21
23
25
27
29
SNR
APPENDIX D : DEFAULT CALL PROGRESS TONE DETECTORS
Figure D1 : Call Progress Tone Detector Band 0
Figure D2 : Call Progress Tone Detector Band 1
10
10
0
0
Always On
Always On
Always Off
-10
Always Off
-10
d
d
-20
-20
B
B
m
m
-30
-30
-40
-40
-50
-50
300 400 500
600 700
800 900 1000
300 400 500 600 700 800 900 1000
Hz
Hz
41/55
ST75C50
APPENDIX E : DEFAULT ANSWER TONE DETECTORS
Figure E1 : 2100HzAnswer Tone Detector
10
0
-10
d
B
-20
m
Always On
Always Off
-30
-40
-50
1950
2050
2150
2250
2350
Hz
APPENDIX F : ELECTRICAL SCHEMATICS
This appendix contains the following schematics :
- example of hybrid line design
- chip interconnect circuitry required in the case of
- interconnect circuitry required for the use of the
serial link (TS7538) as well as a bulk delay
memory.
the minimal configuration
- emulation using external program memory
Figure F1 : Typical line interface
22kΩ
100pF
2 x R
5
1.2kΩ
7
13.2kΩ
22kΩ
4
8
RxA2
2
3
1
TxA1
VCM
TxA2
6
R1
300Ω
2.2nF
(note c)
R
R2
VCM
680pF
2.2nF
(note c)
R
5
6
300Ω
7
R1
4
8
2
3
1
RxA1
13.2kΩ
22kΩ
Ω
1.2k
2 x R
TIP
100pF
RING
22kΩ
Notes : a) All resistors are 1% tolerance
b) The receive gain is defined by : G = (1 + R1/R2)
c) Capacitor close to RxA1 and RxA2
42/55
ST75C50
Figure F2
R x C
S C R x H
Y N R x S
2 L A X T
1 1 L X T A
0 1 L X T A
T E S E N R
3 T S T E
C
C
R x R
T x C
C
T x H S
2 T S T E
C N Y T x S
T x R C
T x S
1 T S T E
C
0
T X D
T X D
1
1
D R
D X
A 0
A 1
A 2
I
X K L B C
F S
1 K L B C
X
1
F S
A 3
A 4
A 5
A 6
A 7
D 0 R X
D I R X
0
0
0
D R
D X
R L K B C
C B L K
F S
F S R
0
A 8
A 9
T
S E R E
0
1
2
3
4
5
A 1
A 1
A 1
A 1
A 1
A 1
L P
K C A L P
N O P
43/55
ST75C50
Figure F3
R x C
X T A L 2
L 1 1 X T A
L 1 0 X T A
S E T N R E
T E S T
C
R x H S
R x S Y N
R x R C
C
C T x
3
2
1
C S H T x
N C x S T Y
C R T x
x S T C
T E S T
T E S T
T X D 0
T X D I
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 9
D R 1
D X 1
A 0
A 1
A 2
A 3
A 4
K X B C L
F S X
B C L K 1
F S 1
R X D 0
D R 0
D X
R X D I
C B L K R
F S R
A 5
A 6
A 7
0
0
B C L K
F S 0
A 8
A 9
R E S E T
A 1 0
A 1 0
L P
A 1 1
A 1 2
A 1 3
A 1 4
A 1 5
A 1 1
L P A C K
A 1 2
A 1 3
A 1 4
A 1 5
N O P
44/55
ST75C50
Figure F4
O E
W E
C S
C S
2
1
A 1 2
A 1 1
1 2 I A
1 1 I A
A 1 0
A 9
1 0 I A
9
8
I A
I A
A 8
A 7
7
6
I D
I D
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
7
6
5
4
3
2
1
0
I A
I A
I A
I A
I A
I A
I A
I A
A 6
A 5
I D 5
I D 4
I D
A 4
A 3
3
1
I D 2
I D
A 2
A 1
A 0
I D 0
O E
W E
C S
C S
O E
W E
C S
C S
2
1
2
1
2 1 I A
1 1 I A
2
1
A 1
A 1
0 1 I A
A 1 2
A 1 1
0
A 1
A 9
1 2 I A
1 1 I A
9 I A
8 I A
A 1 0
A 9
A 8
A 7
7 I A
6 I A
5 I A
4 I A
I D 7
I D 6
1 0 I A
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
9
8
I A
I A
A 8
A 7
A 6
A 5
7
6
I D
I D
I D 5
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
7
6
5
I A
I A
I A
I D 4
I D 3
A 6
A 5
A 4
A 3
I D 5
I D 4
I D
3 I A
2 I A
1 I A
0 I A
I D 2
I D 1
A 4
A 3
A 2
A 1
A 0
3
1
4
I A
I D 2
I D
3
2
1
0
I A
I A
I A
I A
I D 0
A 2
A 1
A 0
I D 0
O E
W E
C S
C S
2
1
2 1 I A
1 1 I A
2
1
A 1
A 1
0 1 I A
9 I A
8 I A
0
A 1
A 9
A 8
A 7
I D 7
I D 6
7 I A
6 I A
5 I A
4 I A
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
A 6
A 5
I D 5
I D 4
I D 3
A 4
A 3
3 I A
2 I A
1 I A
0 I A
1 0 I D
I D 0 1
I D 2
I D 2
I D 1
I D 0
A 2
A 1
A 0
2
I D
I D
3
4
I D 3
4
5
I D
5
6
I D
6
7
I D
I D
I D
I D 7
O E
W E
C S
C S
8
9
I D
I D
8
9
I D
I D
1 0 I D
2
1
1 0 I D
1 1 I D
1 2 I D
I D 1 1
1 2 I D
1 3 I D
1 3 I D
2 1 I A
1 1 I A
1 4 I D
1 5 I D
2
1
A 1
A 1
I D 1 4
1 5 I D
0 1 I A
1 6 I D
0
A 1
A 9
I D 1 6
I D 1 7
9 I A
8 I A
1 7 I D
1 8 I D
A 8
A 7
1 8 I D
7 I A
6 I A
5 I A
4 I A
I D 7
I D 6
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
1 9 I D
2 0 I D
I D 1 9
A 6
A 5
2 0 I D
2 1 I D
I D 5
I D 4
I D 3
2 1 I D
2 2 I D
2 3 I D
A 4
A 3
I D 2 2
3 I A
2 I A
1 I A
0 I A
2 3 I D
I D 2
I D 1
2 4 I D
A 2
A 1
A 0
2 4 I D
2 5 I D
2 6 I D
I D 2 5
2 6 I D
I D 2 7
I D 2 8
2 9 I D
I D 0
2 7 I D
A 0
A 0
2 8 I D
2 9 I D
A 1
A 1
3 0 I D
3 1 I D
O E
W E
C S
C S
A 2
I D 3 0
I D 3 1
A 2
A 3
A 3
A 4
A 4
A 5
A 5
A 6
A 6
A 7
A 7
D R 1
D X 1
B C L K 1
2
1
F S 1
D R 0
2 1 I A
1 1 I A
2
1
A 1
A 1
A 8
A 8
D X 0
0 1 I A
A 9
A 9
0
A 1
A 9
B C L K 0
F S 0
R E S E T
9 I A
8 I A
A 1 0
0
1
2
3
4
5
A 1
A 1
A 1
A 1
A 1
A 1
A 8
A 7
A 1 1
A 1 2
A 1 3
A 1 4
A 1 5
7 I A
6 I A
5 I A
4 I A
I D 7
I D 6
D 7
D 6
D 5
D 4
D 3
D 2
A 6
A 5
L P
I D 5
I D 4
I D 3
L P A C K
A 4
A 3
3 I A
2 I A
1 I A
0 I A
I D 2
I D 1
I D 0
N O P
A 2
A 1
A 0
D 1
D 0
45/55
ST75C50
APPENDIX G
I - TONE DETECTORS
I.1 - Overview
mand.
While in FAX half duplex receive IDLE mode a set
of 8 cells allows to implement customized hand-
shake short sequences.
The general purpose TS75C50/51/52 tone detec-
tor block is a powerful module that covers a lot of
applications :
- Call progress tone detection, fully programmable
for all different countries
- DTMF detection
- High level handshake for all main modem stand-
I.2.1 - BIQUADRATIC FILTERS (see Figure G1)
Each biquadratic filter is a double regular section
that can perform any transfer function with 4 poles
and 4 zeros. This routine is run on a sample basis.
The corresponding transfer function is :
ards
C5 + 2 C3 z−1 + 2 C4 z−2
- FAX, voice, data automaticdetection
- Call waitingdetection,whileinvoice or datamode
Out
Input
= C0
1 − 2 C1 z−1 − 2 C2 z−2
CB + 2 C9 z−1 + 2 CA z−2
z−1
I.2 - Description
C6
−1
1 − 2 C7 z − 2 C8 z−2
The tonedetectorblockis a set of 16 identicalcells.
Each cell is composedof a doublebiquadraticfilter,
a powerestimator section, a static level and a level
comparator.
Note : All coefficients are coded on 16 bits 2’s complement in the
range +1, -1 (Q15). To avoid the possibility of overflow the
user must check that the internal node must not be higher
that 0.5 (in Q15 representation).
Each biquadratic filter, power estimator and static
level can be programmed using a complete set of
commands (TDRC, TDRW, TDWC, TDWW, TDZ).
I.2.2 - POWER ESTIMATION (see Figure G2)
The power estimation cell is needed to measure
the amplitude of the different tones. It is run on a
sample basis.
The wiring between the different cells can be de-
fined by the user using the command allowing a
wide range of applications.
The corresponding transfer function is :
P1
Out = | Input | z-1
The 16 comparator outputs give, on a baud basis,
the information into a two 8 bits word TONEDET0
(for cells number 0 to 7) and TONEDET1 (for cells
number 8 to F). These TONEDET variables can be
accessed using a MR command or, more easily,
monitored on a baud basis using the DOSR com-
1 − (1 − P1) z−1
Note : To deal with the high dynamic range of the analog front end,
the computation loop of the power estimation is run with 32
bits accuracy. The output and input of that cell are however
16 bit words (Q15).
Figure G1 : Biquadratic IIR Filter
-1
IN
C0
C5
C6
CB
OUT
Z
2
2
-1
-1
Z
Z
Z
Z
C1
C2
C3
C7
C8
C9
-1
-1
C4
CA
46/55
ST75C50
Figure G2 : Power Estimator
The user specifies the inputs of the filters, power
and comparators. At least one input must come
from the RxSig (node 01, 02 or 03). It is mandatory
to connect all unused cell input to the groundsignal
(node 00).
OUT
IN
+
-1
ABS(.)
P1
Z
-1
Z
III - EXAMPLE (see Figure G5)
Hereunder is an example of programming a single
tone detector (using cell #3) and a complex differ-
ential tone detector (using cell #4 and #5).
I.2.3 - STATIC LEVEL
Asingle thresholdlevel is associated with eachcell.
It can be use to compare the output of a power
estimation with an absolute value.
The bit 3 of the TONEDET variable willbe triggered
each time the energy of that filtered signal is higher
than static level number 3.
I.2.4 - COMPARATOR
The bit 4 of the TONEDET variable will be on each
time a receive signal has energy higher than the
static level number 4. The bit 5 will be ononly when
the filtered (filter section 4 and5) received signal is
higher than the energy of the wideband signal
number 4 ; this prevents triggering on noise.
The comparator computes on a baud basis, the
difference of the signal on its positive input and its
negative input. If the result is higher that zero it set
the corresponding bit in the TONEDET[0..1] word
if not it clears this bit.
I.2.5 - WIRING
Program cell #3 :
The user must specify the connection(wiring) be-
tween the input/output of the filter, the input/output
of the power estimator, the output of the static
levels and the two inputs of the comparators.
TDWW
03
00
13
01
Connect received signal to filter and filter to
energy
TDWW
03
01
33
23
The outputs signal have an absolute address :
Connect level to comparator negative input
and energy to positive input
Node Address
Signal
Address
Description
Name
Program cell #4 and #5 :
Ground
00
01
Signal always equal to 0000
TDWW
Connect received signal to filter and energy
TDWW 04 01 34 24
Connect level to comparator negative input
and energy to positive input
04
00
01
01
RxSig
Receive signal from the
analog front end, (after echo-
substraction in V.32 mode)
RxSig2
RxSig4
02
Receive signal multiplied by 2
Receive signal multiplied by 4
Reserved
03
TDWW
05
00
15
14
04..0F
10..1F
Connect filter #4 output to filter and filter to
energy
Filter [0..F]
Biquadratic filter outputs
Power estimator outputs
Static levels
TDWW
05
01
24
25
Power [0..F] 20..2F
Level [0..F] 30..3F
Connect wideband energy to negative input
and energy to positive input
47/55
ST75C50
Figure G3 : Tone Detector Wiring Address (first half)
BIQUADRATIC
FILTER
#0
@10
@20
@30
POWER
#0
COMP.
#0
LEVEL #0
BIQUADRATIC @11
@21
@31
POWER
#1
FILTER
#1
COMP.
#1
LEVEL #1
BIQUADRATIC @12
@22
@32
POWER
#2
FILTER
#2
COMP.
#2
LEVEL #2
@00
D0
D1
D2
D3
D4
BIQUADRATIC
FILTER
#3
@13
@14
@15
@16
@17
@23
@33
GROUND
POWER
#3
COMP.
#3
LEVEL #3
@01
@02
@03
RX SIGNAL
BIQUADRATIC
@24
@34
POWER
#4
FILTER
#4
COMP.
#4
D5
D6
D7
2
2
LEVEL #4
BIQUADRATIC
@25
@35
POWER
#5
TONEDET0
FILTER
#5
COMP.
#5
LEVEL #5
BIQUADRATIC
@26
@36
POWER
#6
FILTER
#6
COMP.
#6
LEVEL #6
BIQUADRATIC
@27
@37
POWER
#7
FILTER
#7
COMP.
#7
LEVEL #7
48/55
ST75C50
Figure G4 : Tone Detector Wiring Address (second half)
BIQUADRATIC
FILTER
@18
@28
@38
POWER
#8
#18
COMP.
#8
LEVEL #8
BIQUADRATIC @19
@29
@39
POWER
#9
FILTER
#19
COMP.
#9
LEVEL #9
BIQUADRATIC
FILTER
@1A
@1B
@2A
@3A
POWER
#A
#A
COMP.
#A
LEVEL #A
D0
D1
D2
D3
D4
D5
D6
D7
BIQUADRATIC
FILTER
#B
@2B
@3B
POWER
#B
COMP.
#B
LEVEL #B
BIQUADRATIC @1C
@2C
@3C
POWER
#C
FILTER
#C
COMP.
#C
LEVEL #C
BIQUADRATIC @1D
@2D
@3D
POWER
#D
TONEDET1
FILTER
#D
COMP.
#D
LEVEL #D
BIQUADRATIC @1E
@2E
@3E
POWER
#E
FILTER
#E
COMP.
#E
LEVEL #E
BIQUADRATIC
FILTER
#F
@1F
@2F
@3F
POWER
#F
COMP.
#F
LEVEL #F
Figure G5 : Wiring Example
@00
@13
@14
@15
BIQUADRATIC
FILTER
#3
@23
POWER
#3
GROUND
COMP.
#3
@33
LEVEL #3
@01
RX SIGNAL
@24
@34
BIQUADRATIC
FILTER
#4
POWER
#4
D3
D4
@02
@03
COMP.
#4
2
2
LEVEL #4
D5
@25
@35
BIQUADRATIC
FILTER
#5
TONEDET0
POWER
#5
COMP.
#5
LEVEL #5
49/55
ST75C50
APPENDIX H : BUFFER OPERATIONS
I - INTRODUCTION
number of valid bytes to be transmitted (up to 8 per
buffer).
This appendixis dedicatedto the buffer operations,
either the data buffers, used either in data ex-
changes or the symbol buffer operationsdedicated
to bulk delay management.
The first part is oriented towards a functional de-
scription of the buffer operations, while the second
section is more oriented towards the management
of the buffers.
Each time the transmit expander has emptied a
buffer, the IT2 interrupt is raised.
Figure H2 : Tx Buffer Schematics
IT2
ERR_Tx
TRANSMITTER
STATUS DATA
clear
TO TRANSMITTER
II - RECEIVE OPERATIONS OVERVIEW
Tx_BUFF_STATUS
Figure H1 describes the receive data flow.
TRANSMIT
EXPANDER
Figure H1 : Rx Buffer Schematics
Tx_BUFF_DATA
IT3
RECEIVER
STATUS
ERR_Rx
TRANSMIT FORMAT
RECEIVE
Rx_BUFF_STATUS
Rx_BUFF_DATA
DATA TO
TRANSMITTER
TxD
SERIALIN
MUX
RECEIVE
COMPANDER
DATA FROM
RECEIVER
TxCLK
IV - BUFFER STATUS AND FORMAT
DESCRIPTION
RECEIVE FORMAT
SERIAL OUT
RxD
RxCLK
The following section describes the meaning and
use of the buffer status words.
The ST75C50 uses parallel synchronous data.
8 bit words are synchronously available in the
receive buffers. The buffer status holds the num-
bers of valid bytes received.
Each time the receive compander has filled up a
new buffer, it sets the corresponding flag with the
proper status then generatesthe IT3 interrupt. The
availability of the buffers is tested just before start-
ing to fill them. This means that the host must not
perform any buffer operation on the data part while
the statusremains 0.
IV.1 - Transmit buffer
The transmit buffer status words are DTTBS0 and
DTTBS1 (see the Host Interface Summary section
in the main document) and are more likely to be
seen as control words. These flags must be set by
the host and are reset by the ST75C50. The data
buffer exchanges being synchronized through
these status words, an improper setting will trigger
the error Err_Tx in the error status SYSERR. A
value of 0 for DTTBS0 or DTTBS1 means that the
corresponding buffers are empty : this value is
written by the ST75C50. The unused bits of
DTTBSx must be set to 0 by the host.
III - TRANSMIT OPERATIONS OVERVIEW
Figure H2 describes the transmit data flow.
Field
BUFF_LENG 3..0
Pos. Val.
8..1
Description
Number of valid bytes
in the buffer
The ST75C50 uses parallel synchronous data.
8 bit words are synchronously read from the trans-
mit buffers. The transmit status buffer holds the
50/55
ST75C50
IV.2 - Receive buffer
symbols needed are 1.5 2400 (3600 bytes). If we
say that the base address is, for example,
0x4230 the top address must be 0x503F
(= 0x4230 + 3600 - 1).
According to the current round trip delay, the
ST75C50 computes the address of the symbols
required for the far end echo computation. This
address is computed (as the previous one) accord-
ing to a circular addressing scheme inside the
base .. top address space.
The symbol bufferstatus SYSSTAis then set to FF
and theIT1 interrupt israised. The hostshould then
perform the following operations in sequence :
1) read the address SYMADR[0..1] of the target
location for the symbols,
The receive buffer status words are DTRBS0 and
DTRBS1 (see the Host Interface Summary section
in the main document). These flags are set by the
ST75C50 and must be reset by the host. The data
buffer exchanges being synchronized through
these status words, an improper resetting will trig-
ger theerror Err_Rx in the error status SYSERR. A
value of 0 for DTRBS0 or DTRBS1 means that the
corresponding buffers are empty : this value must
be written by the host.
Field
Pos. Val.
Description
8..1 Number of valid bytes
in the buffer
BUFF_LENG
3..0
2) read SYMBU[0..7], the corresponding
symbols, and store them at the addressed
lolcation (8 symbols),
3) read the addressSYMADT[0..1] ofthe symbols
required by the ST75C50,
V - DATA BUFFER MANAGEMENT
In the transmit path, the data buffer exchanges
should always begin with the filling of buffer 0, then
with the update of the buffer 0 status word. The
initiation ofthedata exchangesis initiatedthen with
the XMIT command.
4) fetch the required 8 symbols and store them in
the SYMBUF[0..7] array,
5) write the proper status word (00) in SYMSTA.
VI - BULK DELAY MANAGEMENT
The ST75C50 meanwhilepools for the status word
to be 00, then stores the symbols inside its own
memory space for processing and sets the status
word to its idle value FF.
The processing of the bulk delay uses a simplified
buffer exchange scheme. Each time the ST75C50
has internally buffered enough symbols, it writes
them inside the symbol buffer area, then computes
the address inside the host space where these
symbols should be written. This address is a rela-
tive address inside the host data space, allowing
thus the host to dispose this area themost conven-
ient way. The target address is located in the SY-
MADR[0..1] registers under a 16-bit form.
These addresses must be defined by the user
using the BULK command. It can be any valid 16
bit number assuming th e base addre ss
(BA_ADDR) is on a 8 byte boudary and the top
address (TO_ADDR) is higher and on a 8 byte
boundary minus 1.
VI.1 - Status Word
The status word SYSSTA can have the following
values :
Field
Pos.
Val.
Description
SYSTA
7..0
00
Symbol buffer owned by
the DSP
Symbol buffer owned by
the host
FF
VI.2 - Interrupt
Each time a symbol buffer is processed by the
ST75C50 an IT1 interrupt is generated. The host
has an 8 symbols time (3.3ms) to process this
interrupt otherwise an error occurs that will be
signaled into the SYSERR bit 2 ERR_SYM.
Eg : if we want to be able to cancel a 2 satellites
Round trip delay we must have a bulk delay bigger
than 2 times 560ms, lets say 1.5 seconds. The
51/55
ST75C50
PACKAGE MECHANICAL DATA
44 PINS - PLASTIC QUAD FLAT PACK (THIN)
A
A2
A1
e
11
1
12
44
22
34
23
33
C
E2
E1
E
K
Millimeters
Typ.
Inches
Typ.
Dimensions
Min.
Max.
Min.
Max.
A
A1
A2
B
1.60
0.063
0.25
1.40
0.01
1.35
0.35
1.45
0.50
0.053
0.014
0.055
0.057
0.020
0.007
0.640
0.555
C
0.17
D
15.75
13.90
16.00
14.00
10.00
1.00
16.25
14.10
0.620
0.547
0.630
0.551
0.394
0.039
0.630
0.551
0.394
0.063
D1
D2
e
E
15.75
13.90
16.00
14.00
10.00
1.60
16.25
14.10
0.620
0.547
0.640
0.555
E1
E2
F
K
0o (min.), 7o (max.)
0.75 0.018
L
0.45
0.60
0.024
0.030
52/55
ST75C50
PACKAGE MECHANICAL DATA (continued)
80 PINS - PLASTIC QUAD FLAT PACK (THIN)
A
A2
A1
B
PIN 1
80
61
IDENTIFICATION
1
60
20
41
C
21
40
E3
E1
E
Gage plane
0.25 mm
K
mm
inches
Typ
Dim.
Min
Typ
Max
Min
Max
A
A1
A2
B
1.60
0.15
1.45
0.38
0.20
0.063
0.006
0.057
0.014
0.008
0.05
1.35
0.22
0.09
0.002
0.053
0.010
0.004
1.40
0.32
0.055
0.012
C
D
16.00
14.00
12.35
0.80
0.630
0.551
0.486
0.0314
0.630
0.551
0.486
0.024
0.039
D1
D3
e
E
16.00
14.00
12.35
0.60
E1
E3
L
0.45
0.75
0.020
0.030
L1
K
1.00
0o (min.), 7o (max.)
53/55
ST75C50
PACKAGE MECHANICAL DATA (continued)
80 PINS - PLASTIC QUAD FLAT PACK
A
A2
B
A1
PIN 1
80
65
IDENTIFICATION
1
61
24
41
C
25
40
E3
E1
E
Gage plane
0.25 mm
K
mm
inches
Typ
Dim.
Min
Typ
Max
Min
Max
A
A1
A2
B
3.40
0.134
0.25
2.55
0.010
0.100
0.011
0.005
0.903
0.785
2.80
3.05
0.45
0.110
0.120
0.018
0.009
0.923
0.789
0.30
C
0.13
0.23
D
22.95
19.90
23.20
20.00
18.40
0.80
23.45
20.10
0.913
0.787
0.724
0.0314
0.677
0.551
0.472
0.031
0.063
D1
D3
e
E
16.95
13.90
17.20
14.00
12.00
0.80
17.45
14.10
0.667
0.547
0.687
0.555
E1
E3
L
0.65
0.95
0.026
0.037
L1
K
1.60
0o (min.), 7o (max.)
54/55
ST75C50
PACKAGE MECHANICAL DATA (continued)
160 PINS - PLASTIC QUAD FLAT PACK
mm
inches
Typ
Dim.
Min
Typ
Max
Min
Max
A
A1
A2
B
4.07
0.160
0.25
3.17
0.010
0.125
0.008
1.218
1.098
3.42
3.67
0.38
0.135
0.145
0.015
1.238
1.106
0.22
D
30.95
27.90
31.20
28.00
25.35
0.65
31.45
28.10
1.228
1.102
0.998
0.0256
1.228
1.102
0.998
0.031
0.063
D1
D3
e
E
30.95
27.90
31.20
28.00
25.35
0.80
31.45
28.10
1.218
1.098
1.238
1.106
E1
E3
L
0.65
0.95
0.026
0.037
L1
K
1.60
0o (min.), 7o (max.)
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of suchinformation nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwiseunder anypatent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
1993 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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55/55
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