STA020D [STMICROELECTRONICS]
96kHz DIGITAL AUDIO INTERFACE TRANSMITTER; 96kHz的数字音频接口发射器
| 型号： | STA020D |
| 厂家： | 
ST |
| 描述： | 96kHz DIGITAL AUDIO INTERFACE TRANSMITTER |
| 文件： | 总12页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA020
96kHz DIGITAL AUDIO INTERFACE TRANSMITTER
PRODUCT PREVIEW
MONOLITHIC DIGITAL AUDIO INTERFACE
TRANSMITTER
3.3V SUPPLY VOLTAGE
SUPPORTS:
- AES/EBU,IEC 958,
- S/PDIF, & EIAJ CP-340
- Professional and Consumer Formats
PARITY BITS AND CRC CODES GENERATED
TRANSPARENT MODE ALLOWS DIRECT
CONNECTION OF STA020 AND STA120
SDIP24
SO24
ORDERING NUMBERS:
DESCRIPTION
STA020
STA020D
The STA020 is a monolithic CMOS device which
encodes and transmits audio data according to
the AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340
interface standards. It supports 96kHz sample
rate operation
The STA020 accepts audio and digital data which
is then multiplexed, encoded and driven onto a
cable.
pable of supportinga wide variety of formats.
The STA020 multiplexes the channel, user, and
validity data directly from serial input pins with
dedicated input pins for the most important chan-
nel statusbits.
The audio serial port is double buffered and ca-
BLOCK DIAGRAM
M0
M1
M2
VD+
19
GND
18
MCK
RST
16
23
22
21
5
6
7
8
SCK
FSYNC
SDATA
AUDIO
SERIAL PORT
REGISTERS
20
17
TXP
TXN
MUX
DIFFERENTIAL
10
11
9
C
U
V
7
15
24
TRNPT
D97AU599A
DEDICATED CHANNEL CBL
STATUS BUS
October 1999
1/12
This is preliminary information on a new product now in development. Details are subject to change without notice.
STA020
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
4
Unit
V
VD+
VIND
Tamb
Tstg
DC Power Supply
Digital Input Voltage
-0.3 to VD+ 0.3
-20 to +85
-40 to 150
V
Ambient Operating Temperature (power applied)
Storage Temperature
°C
°C
RECOMMNDED OPERATING CONDITIONS (GND = 0V; all voltageswith respect to ground)
Symbol
VD+
Parameter
DC Voltage
Ambient Operating Temp.
Test Condition
Min.
Typ.
3.3
Max.
3.6
Unit
V
3
0
Tamb
25
70
°C
PIN CONNECTION
C7/C3
PRO
1
24
23
22
21
20
19
18
17
16
15
14
13
TRNPT/FC1
2
M0
C1/FC0
C6/C2
MCK
3
M1
4
M2
5
TXP
SCK
6
VD+
FSYNC
SDATA
V
7
GND
TXN
8
9
RST
C/SBF
U
10
11
12
CBL/SBC
EM0/C9
EM1/C8
C9/C15
D97AU608A
PINS DESCRIPTION
N.
Name
Function
Power Supply Connections
18
19
GND
VD+
Ground.
Positive Digital Power. Nominally +3.3V.
Audio Input Interface
6
SCK
Serial Clock.
Serial clock for SDATA pin which can be configured (via the M0, M1 and M2 pins) as an input
or output and can sample data on the rising or falling edge.As an output, SCK will contain 32
clocks for every audio sample.
7
FSYNC
Frame Sync.
Delineates the serial data and may indicate the particular channel, left or right and may be an
input or output. The format is based on M0, M1 and M2 pins.
2/12
STA020
PINS DESCRIPTION (continued)
N.
Name
Function
8
SDATA
Serial Data.
Audio data serial input pin.
21,
22,23
M0, M1, M2 Serial Port Mode Select.
Selects the format of FSYNC and the sample edge of SCK with respect to SDATA.
Control Pins
1
C7/C3
Channel Status Bit 7/Channel Status Bit 3.
In professional mode, C7 is the inverse of channel status bit 7. In consumer mode, C3 is the
inverse of channel status bit 3, C7/C3 are ignored in Transparent Mode.
2
PRO
Professional/Consumer Select.
Selects between professional mode (PRO low) and consumer mode (PRO high). This pin
defines the functionality of the channel status parallel pins. PRO is ignored in Transparent
Mode.
3
C1/FC0
Channel Status Bit 1/Frequency Control 0.
In professional mode, C1 is the inverse of channel status bit 1. In consumer mode, FC0 and
FC1 are encoded versions of channel status bits 24 and 25 (bits 0 and 1 of byte 3). When
FC0 and FC1 are both high, CD mode is selected. C1/FC0 are ignored in Transparent Mode.
4
9
C6/C2
V
Channel Status Bit 6/Channel Status Bit 2.
In professional mode, C6 is the inverse of channel status bit 6. In consumer mode, C2 is the
inverse of channel status bit 2. C6/C2 are ignored in Transparent Mode.
Validity.
Validity bit serial input port. This bit is defined as per the digital audio standards wherein V = 0
signifies the audio signal is suitable for conversion to analog. V = 1 signifies the audio signal is
not suitable for conversion to analog, i.e. invalid.
10
C/SBF
Channel Status Serial Input/Subcode Frame Clock.
In professional and consumer modes this pin is the channel status serial input port. In CD
mode this pin inputs the CD subcode frame clock.
11
12
U
User Bit.
User bit serial input port.
C9/C15
Channel Status Bit 9/Channel Status Bit 15.
In professional mode, C9 is the inverse of channel status bit 9 (bit 1 of byte 1). In consumer
mode, C15 is the inverse of channel status bit 15 (bit 7 of byte 1). C9/C15 are ignored in
Transparent Mode.
13
14
15
EM1/C8
EM0/C9
Emphasis 1/Channel Status Bit 8.
In professional mode, EM0 and EM1 encode channel status bits 2, 3 and 4. In consumer
mode, C8 is the inverse of channel status bit 8 (bit 0 of byte 1). EM1/C8 are ignored in
Transparent Mode.
Emphasis 0/Channel Status Bit 9.
In professional mode, EM0 and EM1 encode channel status bits 2, 3 and 4. In consumer
mode, C9 is the inverse of channel status bit 9 (bit 1 of byte 1). EM0/C9 are ignored in
Transparent Mode.
CBL/SBC
RST
Channel Status Block Output/Subcode Bit Clock.
In professional and consumer modes, the channel status block output is high for the first 15
bytes of channel status. In CD mode, this pin outputs the subcode bitclock.
16
24
Master Reset.
When low, all internal counters are reset.
TRNPT/FC1 Transparent Mode/Frequency Control 1.
In professional mode, setting TRNPT low selects normal operation & CBL is an output. Setting
TRNPT high, allows the STA020 to be connected directly to an STA120. In transparent mode,
CBL is an input & MCK must be at 256 Fs. In consumer mode, FC0 and FC1 are encoded
versions of channel status bits 24 and 25. When FC0 and FC1 are both high, CD mode is
selected.
Transmitter Interface
5
MCK
Master Clock. Clock input at 128x the sample frequency which defines the transmit timing. In
trasparent mode MCK must be 256 Fs.
20, 17 TXP, TXN
Differential Line Drivers.
3/12
STA020
DIGITAL CHARACTERISTICS (Tamb = 25°C; VD+ = 3.3V ±10%)
Symbol
VIH
Parameter
Test Condition
Min.
2.0
Typ.
Max.
VDD+0.3
+0.8
Unit
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
Master Clock frequency
Master Clock Duty Cycle
VIL
-0.3
V
VOH
VOL
Iin
IO = 200µA
VDD-1.0
V
IO = 3.2mA
0.4
10
26
60
V
1.0
µA
MHz
%
MCK
(Note 1)
(high time/cycle time)
40
Note 1: MCK must be 128x the input word rate, except in Transparent Mode where MCK is 256x the input word rate.
Figure 1. STA020 Professional & Consumer Modes Typical Connection Diagram.
EXTERNAL
CLOCK
+3.3V
MCK
VD+
0.1µF
FSYNC
SCK
GND
5
19
7
6
8
18
24
TRNPT
AUDIO
DATA
PROCESSOR
SDATA
M0
M1
M2
23
22
21
CBL
C
SERIAL PORT
MODE SELECT
15
10
11
9
STA020
µCONTROLLER
or
U
V
UNUSED
TXP
TXN
20
17
RST
16
TRANSMITTER
CIRCUIT
CHANNEL
STATUS BITS
CONTROL
8 DEDICATED C.S. BITS
D97AU600A
Figure 2. STA020 Typical Connection Diagram.
EXTERNAL
CLOCK
+5V
MCK
VD+
18
0.1µF
FSYNC
SCK
7
6
8
GND
5
19
AUDIO
DATA
PROCESSOR
SDATA
V
SBF
U
M0
M1
M2
9
23
22
21
SERIAL PORT
MODE SELECT
DECODER
SUBCODE
PORT
10
11
15
SBC
STA020
TXP
TXN
20
17
RST
RESET
CONTROL
16
TRANSMITTER
CIRCUIT
See Appendix B
CHANNEL
STATUS BITS
CONTROL
8 DEDICATED C.S. BITS
D99AU989A
4/12
STA020
GENERAL DESCRIPTION
Audio Serial Port
The STA020 is a monolithic CMOS circuit that en-
codes and transmits audio and digital data ac-
cording to the AES/EBU, IEC 958, S/PDIF, and
EIAJ CP-340 interface standards. The chip ac-
cepts audio and control data separately; multiplex
and biphase-mark encode the data internally and
drive it, directly or through a transformer, to a
transmission line.
The audio serial port is used to enter audio data
and consists of three pins: SCK, SDATA and
FSYNC, SCK clocks in SDATA, which is double
buffered, while FSYNC delineates the audio sam-
ples and may indicate the particular channel, left
or right. To support many differentinterfaces, M2,
M1 and M0 select one of seven different formats
for the serial port. The coding is shown in Table 3
while the formats are shown in Figure 3.
Format 0 and 1 are designed to interface with
Crystal ADCs. Format 2 communicates with Mo-
torola and TI DSPs. Format 3 is reserved. Format
4 is compatible with the I2S standard. Formats 5
and 6 make the STA020 look similar to existing
16- and 18-bit DACs and interpolationfilters. For-
mat 7 is an MSB-last format and is conducive to
serial arithmetic. SCK and FSYNC are outputs in
Format 0 and inputs in all other formats. In For-
mat 2, the rising edge of FSYNC delineates sam-
ples and the falling edge must occur a minimum
of one bit period before or after the rising edge.
The STA020 has dedicated pins for the most im-
portant control bits and a serial input port for the
C, U and V bits.
Line Drivers
The differential line drivers for STA020 are low
skew, low impedance,differential outputs capable
of driving 110Ohm transmission lines. (RS422
line driver compatible).
They can also be disabled by resetting the device
(RST = low).
In all formats except 2, FSYNC contains left/right
information requiring both edges of FSYNC to de-
lineate samples. Formats 5 and 6 require a mini-
mum of 16- or 18-bit audio words respectively. In
all formats other than 5 and 6, the STA020 can
accept any word length from 16 to 24 bits by add-
ing leading zeros in format 7 and trailing zeros in
the other formats, or by restricting the number of
SCK periods between active edges of FSYNC to
the sample word length.
FSYNC must be derived from MCK, either
through a DSP using the same clock or using
counters. If SFYNC moves (jitters) with respect to
MCK by four MCK periods, the internal counters
and CBLmay be reset.
STA020 DESCRIPTION
The STA020 accepts 16 to 24-bit audio samples
through a serial port configured in one of seven
formats; provides several pins dedicated to par-
ticular channel status bits and allows all channel
status, user and validity bits to be serially input
through port pins. This data is multiplexed, the
parity bit is generated and the bit stream is
biphase-mark encoded and driven through an
RS422 line driver.
The STA020 operates as a professional or con-
sumer interface transmitter selectable by pin 2,
PRO. As a professional interface device, the
dedicated channel status input pins are defined
according to the professional standard, and the
CRC code (C.S. byte 23) can be internally gener-
ated.
Table 1. Audio Port Modes
As a consumer device, the dedicated channel
status input pins are defined according to the
consumer standard. A submode provided under
the consumer mode is compact disk, CD, mode.
When transmitting data from a compact disk, the
CD subcode port can accept CD subcode data,
extract channel status information from it, and
transmit it as user data.
The master clock , MCK, controls timing for the
entire chip and must be 128xFs. As an example,
if stereo data is input to the STA020 at 44.1kHz,
MCK input must be 128 times that or 5.6448MHz.
M2
0
M1
0
M0
0
Format
0 - FSYNC & SCK Output
1 - Left/Right, 16-24 Bits
2 - Word Sync, 16-24 Bits
3 - Reserved
4 - Left/Right, I2S Compatible
5 - LSB Justified, 16 Bits
6 - LSB Justified, 18 Bits
7 - MSB Last, 16-24 Bits
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
5/12
STA020
Figure 3. Audio Serial Port Formats.
FORMAT 0:
FSYNC(out)
LEFT
LEFT
LEFT
RIGHT
RIGHT
RIGHT
SCK(out)
SDATA(in)
FORMAT 1:
MSB
MSB
MSB
LSB
LSB
LSB
MSB
MSB
MSB
LSB
LSB
LSB
MSB
MSB
MSB
FSYNC(in)
SCK(in)
SDATA(in)
FORMAT 2:
FSYNC(in)
SCK(in)
SDATA(in)
FORMAT 3:
(RESERVED)
FORMAT 4:
FSYNC(in)
LEFT
RIGHT
SCK(in)
SDATA(in)
FORMAT 5:
MSB
LSB
MSB
LSB
MSB
FSYNC(in)
LEFT
RIGHT
SCK(in)
SDATA(in)
LSB
LSB
MSB
MSB
LSB
LSB
MSB
MSB
LSB
16 Bits
16 Bits
FORMAT 6:
FSYNC(in)
LEFT
RIGHT
MSB
SCK(in)
SDATA(in)
MSB
LSB
18 Bits
18 Bits
FORMAT 7:
FSYNC(in)
LEFT
RIGHT
SCK(in)
SDATA(in)
LSB
LSB
MSB
D97AU604
zero to indicate the audio data is suitable for con-
version to analog. Therefore, when the audio
data is errored, or the data is not audio, the V bit
should be set high. The channel status serial in-
put pin (C) is not available in consumer mode
when the CD subcode port is enabled (FC1 =
FC0 = high). Any channel status data entered
through the channel status serial input (C) is logi-
cally OR’ed with the data entered through the
dedicated pins or internally generated.
C, U, V Serial Port
The serial input pins for channel status (C), user
(U), and validity (V) are sampled during the first
bit period after the active edge of FSYNC for all
formats except Format 4. Format 4 is sampled
during the second bit period (coincident with the
MSB). In Figure 3, the arrows on SCK indicate
when the C, U, and V bits are sampled. The C, U,
and V bits are transmitted with the audio sample
entered before FSYNC edge that sampled it. The
V bit, as defined in the audio standards, is set to
6/12
STA020
(starting with preamble Z). The C, U, and V input
ports only need to be valid for a short period after
FSYNC changes. A sub-frame includes one
audio sample while a frame includes a stereo
pair. A channel status (C.S.) block contains 24
bytes of channel status and 384 audio samples
(or 192 stereo pairs, or frames, of samples).
RST and CBL (TRNPT is low)
When RST goes low, the differential line drivers
are set to ground. In order to properly synchro-
nize the ST020 to the audio serial port, the trans-
mit timing counters, which include CBL, are not
enabled after RST goes high until eight and one
half SCK periods after reset is exited) of FSYNC.
When FSYNC is configured as a left/right signal
(all defined formats except 2), the counters and
CBL are not enabled until the right sample is be-
ing transmitted). This guarantees that channel A
is left and channel B is right as per the digital
audio interface specs.
Figure 4 shows the CUV ports as having left and
right bits (e.g. CUV0L, CUV0R). Since the C.S.
block is defined as 192 bits, or one bit per frame,
there are actually 2 C.S. blocks, one for channel
A (left) and one for channel B (right). When input-
ting stereo audio data, both blocks normally con-
tain the same information, so C0L and C0R from
the input port pin are both channel status bit 0 of
byte 0, which is defined as professional/con-
sumer. These first two bits from the port, C0L and
C0R, are logically OR’ed with the inverse PRO,
since PRO is a dedicated channel status pin de-
fined as C.S. bit 0.
As shown in Figure 4, channel block start output
(CBL), can assist in serially inputtingthe C, U and
V bits as CBL goes high one bit period before the
first bit of the preamble of the first sub-frame of
the channel status block is transmitted. This sub-
frame contains channel status byte 0, bit 0. CBL
returns low one bit period before the start of the
frame that contains bit 0 of channel status byte
16. CBL is not available when the CD subcode
port is enabled.
Figure 4 illustrates timing for stereo data input on
the audio port. Notice how CBL rises while the
right channel data (Right 0) is input, but the pre-
vious left channel (Left 0) is being transmitted as
the first sub-frame of the channel status block
Also, if in professional mode, C1, C6, C7 and C9
are dedicatedC.S. pins. The inverse of C1 is logi-
cally OR’ed with channel status input ports bits
C1L and C1R. In similar fashion, C6, C7 and C9
are OR’ed with their respective input bits. Also,
the C bits in CUV128L and CUV128R are both
channel status block bit 128, which is bit 0 of
channel status byte 16.
Figure 4. CBL and Transmitter Timing.
TRNPT high
CBL
TRNPT low
LEFT 0
RIGHT 0
LEFT 1
LEFT 128
RIGHT 128
LEFT 0
RIGHT 0
SDATA
FSYNC
C BITS FROM CPIN
CUV0R
CUV0L
CUV1L
CUV0R
CUV1R
CUV1L
CUV128R
CUV128L
CUV0L
CUV0R
CUV0L
TRNPT high
C,U,V
TRNPT low
CUV191R
CUV0L
CUV191R
C BITS OR’ed
w/PRO pin
C BITS OR’ed
w/C1 pin
BITS 0 of C.S.
BLOCK BYTE 16
TXP
TXN
LEFT
RIGHT
128
RIGHT 191
VUCP191R
LEFT 0
RIGHT 0
128
Preamble Y
VUCP0L
Preamble Z
VUCP0R
Preamble Y
VUCP128L
VUCP127R Preamble X Preamble Y
bit
0
3
4
7 8
27 28 29 30 31
Preamble Z Aux Data LSB
Left 0 - Audio Data
SUB-FRAME
MSB V0 U0 C0 P0
D99AU990
7/12
STA020
are input at the C pin.
Transparent Mode
In certain applications it is desirable to receive digi-
tal audio data with the STA120 and retransmit it
with the STA020. In this case, channelstatus, user
and validity information must pass through unal-
tered. For studio environments, AES recommends
that signal timing synchronization be maintained
throughout the studio. Frame synchronization of
digital audio signals input to and output from a
pieceof equipmentmust be within +/-5%.
The transparent mode of the STA020 is selected
by setting TRNPT, pin 24, high. In this mode, the
CBL pin becomes an input, allowing direct con-
nection of the outputs of the STA120 to the inputs
of the STA020 as shown in Figure 18. The trans-
mitter and receiver are synchronized by the
FSYNC signal. CBL specifies the start of a new
channel status block boundry, allowing the trans-
mit block structure to be slaved to the block struc-
ture of the receiver.
Consumer Mode
Setting PRO high places the STA020 in consumer
mode which redefines the pins as shown in Figure
7. In consumer mode, channel statusbit 0 is trans-
mitted as a zero and channel status bits 2, 3, 8, 9,
15, 24 and 25 are controlledvia dedicatedpins.
The pins are actually the inverse of the bit so if
pin C2 is tied high, channel status bit 2 will be
transmitted as a zero. Also, FC0 and FC1 are en-
coded versions of channel status bits 24 and 25,
which define the sample frequency.
When FC0 and FC1 are both high, the part is
placed in a CD submode which activates the CD
subcode port. This submode is described in detail
in the next section. Table 3 describes the encod-
ing of C24 and C25 through the FC1 and FC0
pins. According to AES/EBU standards, C2 is
copy prohibit/permit. C3 specifies pre-emphasis,
C8 and C9 define the category code and C15
identifies the generation status of the transmitted
material (i.e. first generation, second generation).
In the transparent mode, C, U and V are now
transmitted with the current audio sample as
shown in Figure 5 (TRNPT high) and the dedi-
cated channel status pins are ignored.
When FSYNC is a word clock (Format 2), CBL is
sampled when left C, U, V are sampled. When
FSYNC is Left/Right, CBL is sampled when left
C, U, V are sampled. The channel status block
boundry is reset when CBL transitions from low to
high (based on two successive samples of CBL).
MCK for the STA020 is normally expected to be
128 times the sample frequency, in the trasparent
mode MCK must be 256 Fs.
Table 2. Emphasis Encoding
EM1
EM0
C2
1
C3
1
C4
1
0
0
1
1
0
1
0
1
1
1
0
1
0
0
0
0
0
Table 3. Sample Frequency Encoding
Professional Mode
FC1
FC0
C24
0
C25
0
Comments
44.1kHz
Setting PRO low places the STA020 in profes-
sional mode as shown in Figure 6. In professional
mode, channel status bit 0 is transmitted as a one
and bits 1, 2, 3, 4, 6, 7 and 9 can be controlled
via dedicated pins. The pins are actually the in-
verse of the identifiedbit.
0
0
1
1
0
1
0
1
0
1
48kHz
32kHz
1
1
0
0
44.1kHz, CD Mode
For example, tying the C1 pin low places a one in
channel status bit 1. As shown in the application
Note, Overview of AES/EBU Digital Audio Inter-
face Data Structures, C1 indicates audio/non-
audio; C6 and C7 determine the sample fre-
quency and C9 allows the encoded channel
mode to be stereophonic. EM1 and EM0 deter-
mine emphasis and encode C2, C3, C4 as shown
in Table 2. Thededicated channel status pins are
read at the appropriate time and are logically
OR’ed with datainput on thechannelstatusport, C.
Figure 5. TransparentMode Interface.
V+
MCK
CBL
TRNPT
TXP
C
RXP
RXN
U
V
FSYNC
SCK
SDATA
TXN
In Transparent Mode, these dedicated channel
status pins are ignored and channel status bits
STA120
STA020
DATA
PROCESSING
D97AU605
8/12
STA020
Figure 6. Block Diagram - Professional Mode
M0
M1
M2
23
22
21
8
6
7
SDATA
SCK
AUDIO
AUX
SERIAL
PORT
LOGIC
FSYNC
20
TXP
TXN
BIPHASE
MARK
ENCODER
C Bits
LINE
DRIVER
17
16
CRC
U Bits
10
11
9
MUX
C
U
V
REGISTERS
VALIDITY
PREAMBLE
PARITY
TIMING
RST
MUX
24
2
14
13
3
4
1
12
15
5
TRNPT
D97AU607B
PRO
EM0 EM1 C1 C6 C7 C9
CBL MCK
Figure 7. Block Diagram - Consumer Mode
M0
M1
M2
23
22
21
8
6
7
SDATA
SCK
AUDIO
AUX
SERIAL
PORT
LOGIC
20
FSYNC
TXP
TXN
BIPHASE
MARK
ENCODER
LINE
DRIVER
C Bits
17
16
10
11
9
C
U
V
MUX
U Bits
VALIDITY
PREAMBLE
PARITY
REGISTERS
TIMING
RST
MUX
2
3
24
4
1
13
14 12
15
5
D97AU606A
PRO
FC0 FC1 C2 C3 C8 C9 C15
CBL MCK
+3.3V
9/12
STA020
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A
A1
A2
B
2.35
0.10
2.65 0.093
0.30 0.004
2.55
0.104
0.012
0.100
0.0200
0.013
0.614
0.299
0.33
0.23
0.51 0.013
0.32 0.009
15.60 0.598
7.60 0.291
C
D
E
15.20
7.40
e
1.27
0,050
H
h
10.0
0.25
10.65 0.394
0.75 0.010
0.419
0.030
k
0° (min.), 8° (max.)
1.27 0.016
SO24
L
0.40
0.050
h x 45°
A1
K
B
D
e
A1
C
0.10mm
.004
L
H
Seating Plane
24
1
13
12
SO24
10/12
STA020
mm
MIN. TYP. MAX. MIN. TYP. MAX.
5.08 0.20
inch
DIM.
OUTLINE AND
MECHANICAL DATA
A
A1
A2
B
0.51
3.05
0.36
0.76
0.23
0.020
3.30
0.46
1.02
0.25
4.57 0.120 0.130 0.180
0.56 0.0142 0.0181 0.0220
1.14 0.030 0.040 0.045
0.38 0.009 0.0098 0.0150
B1
c
D
22.61 22.86 23.11 0.890 0.90 0.910
E
7.62
6.10
8.64
0.30
0.340
E1
e
6.40
1.778
7.62
6.86 0.240 0.252 0.270
0.070
0.30
e1
e2
e3
L
10.92
1.52
3.81
0.430
0.060
SDIP24 (0.300”)
2.54
3.30
0.10 0.130 0.150
E
E1
Stand-off
B
B1
e
e1
e2
c
D
E
24
1
13
12
.015
0,38
Gage Plane
e3
e2
SDIP24
11/12
STA020
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