STA505 [STMICROELECTRONICS]
40V 3.5A QUAD POWER HALF BRIDGE; 40V 3.5A四路电源半桥
| 型号： | STA505 |
| 厂家： | 
ST |
| 描述： | 40V 3.5A QUAD POWER HALF BRIDGE |
| 文件： | 总9页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA505
40V 3.5A QUAD POWER HALF BRIDGE
■ MINIMUM INPUT OUTPUT PULSE WIDTH
DISTORTION
■ 200mΩ R
MULTIPOWER BCD TECHNOLOGY
COMPLEMENTARY DMOS
dsON
OUTPUT STAGE
■ CMOS COMPATIBLE LOGIC INPUTS
■ THERMAL PROTECTION
■ THERMAL WARNING OUTPUT
■ UNDER VOLTAGE PROTECTION
PowerSO36
ORDERING NUMBER: STA505
DESCRIPTION
put stage of a stereo All-Digital High Efficiency
(DDX™) amplifier capable to deliver 50 + 50W @
STA505 is a monolithic quad half bridge stage in Mul-
tipower BCD Technology. The device can be used as
dual bridge or reconfigured, by connecting CONFIG
pin to Vdd pin, as single bridge with double current
capability, and as half bridge (Binary mode) with half
current capability.
THD = 10% at V 30V output power on 8
Ω
load and
cc
80W @ THD = 10% at V 36V on 8
Ω load in single
cc
BTL configuration.
The input pins have threshold proportional to Ibias
pin voltage.
The device is particularly designed to make the out-
AUDIO APPLICATION CIRCUIT (Dual BTL)
+VCC
VCC1A
15
17
16
C30
1µF
C55
1000µF
IN1A
29
M3
M2
M5
M4
IN1A
L18 22µH
C20
IBIAS
23
24
+3.3V
OUT1A
CONFIG
100nF
OUT1A
GND1A
C52
PWRDN
PWRDN
FAULT
25
C99
100nF
14
12
R98
6
330pF
PROTECTIONS
R57
10K
R59
10K
27
26
&
C23
470nF
LOGIC
V
CC1B
R63 R100
C101
100nF
TRI-STATE
20
6
C58
100nF
C31
1µF
11
10
C21
100nF
TH_WAR
IN1B
28
30
OUT1B
OUT1B
GND1B
TH_WAR
L19 22µH
IN1B
VDD
VDD
VSS
VSS
21
22
33
34
13
7
REGULATORS
VCC2A
C32
1µF
M17
M15
M16
M14
C58
100nF
C53
100nF
L113 22µH
VCCSIGN
8
9
35
OUT2A
C60
100nF
C110
100nF
VCCSIGN
36
31
20
19
OUT2A
GND2A
C109
C107
100nF
6
4
R103
6
330pF
IN2A
IN2B
IN2A
C108
470nF
GND-Reg
VCC2B
R104
20
R102
6
C106
100nF
GND-Clean
C33
1µF
3
2
C111
100nF
OUT2B
OUT2B
GND2B
IN2B
32
1
L112 22µH
GNDSUB
5
D00AU1148B
July 2003
1/9
STA505
PIN FUNCTION
N°
1
Pin
Description
GND-SUB
Vcc Sign
Vcc1A
Vcc1B
Vcc2A
Vcc2B
GND1A
GND1B
GND2A
GND2B
OUT1A
OUT1B
OUT2A
OUT2B
IN1A
Substrate ground
35 ; 36
15
Signal Positive Supply
Positive Supply
12
Positive Supply
7
Positive Supply
4
Positive Supply
14
Negative Supply
13
Negative Supply
6
Negative Supply
5
Negative Supply
16 ; 17
10 ; 11
8 ; 9
2 ; 3
29
Output half bridge 1A
Output half bridge 1B
Output half bridge 2A
Output half bridge 2B
Input of half bridge 1A
Input of half bridge 1B
Input of half bridge 2A
Input of half bridge 2B
5V Regulator referred to ground
5V Regulator referred to +Vcc
Stand-by pin
30
IN1B
31
IN2A
32
IN2B
21 ; 22
33 ; 34
25
Vdd
Vss
PWRDN
26
TRI-STATE Hi-Z pin
27
FAULT
CONFIG
TH-WAR
Fault pin advisor
24
Configuration pin
28
Thermal warning advisor
19
GND-clean Logical ground
23
IBIAS
NC
High logical state setting voltage
18
Not connected
20
GND-Reg
Ground for regulator Vdd
2/9
STA505
FUNCTIONAL PIN STATUS
PIN NAME
Logical value
IC -STATUS
FAULT
0
1
Fault detected (Short circuit, or Thermal ..)
Normal Operation
(*)
FAULT
TRI-STATE
TRI-STATE
PWRDN
0
1
0
1
0
1
All powers in Hi-Z state
Normal operation
Low absorpion
PWRDN
Normal operation
THWAR
Temperature of the IC =130C
Normal operation
(*)
THWAR
CONFIG
0
1
Normal Operation
(**)
OUT1A=OUT1B ; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)
CONFIG
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
(**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
PIN CONNECTION
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
V
CCSign
GND-SUB
OUT2B
OUT2B
VCC2B
VCCSign
VSS
3
4
VSS
5
IN2B
GND2B
GND2A
6
IN2A
7
IN1B
VCC2A
8
IN1A
OUT2A
OUT2A
OUT1B
OUT1B
9
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
IBIAS
10
11
12
13
14
15
16
17
18
V
CC1B
GND1B
GND1A
V
V
VCC1A
DD
DD
OUT1A
OUT1A
N.C.
GND-Reg
GND-Clean
D01AU1273
3/9
STA505
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
40
Unit
V
V
CE
DC Supply Voltage (Pin 4,7,12,15)
V
Maximum Voltage on pins 23 to 32
Operating Temperature Range
Storage and Junction Temperature
5.5
V
max
T
0 to 70
-40 to 150
°C
°C
op
T
, T
j
stg
THERMAL DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
°C/W
°C
T
Thermal Resistance Junction to Case (thermal pad)
Thermal shut-down junction temperature
Thermal warning temperature
2.5
j-case
T
150
130
25
jSD
T
°C
warn
hSD
t
Thermal shut-down hysteresis
°C
ELECTRICAL CHARACTERISTCS (Ibias = 3.3V; Vcc = 30V; T = 25°C unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
R
Power Pchannel/Nchannel
MOSFET RdsON
Id=1A;
200
270
mΩ
dsON
I
Power Pchannel/Nchannel
leakage Idss
Vcc=35V
50
µA
%
dss
g
Power Pchannel RdsON
Matching
Id=1A
95
95
N
P
g
Power Nchannel RdsON
Matching
Id=1A
%
Dt_s
Dt_d
Low current Dead Time (static)
see test circuit no.1; see fig. 1
10
20
50
ns
ns
High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω
Id=3.5A; see fig. 3
t
Turn-on delay time
Turn-off delay time
Rise time
Resistive load
100
100
25
ns
ns
ns
ns
V
d ON
t
Resistive load
d OFF
t
Resistive load; as fig.1;
Resistive load; as fig. 1;
r
t
Fall time
25
f
V
Supply voltage operating voltage
High level input voltage
9
36
CC
V
Ibias/2
+300mV
V
IN-H
V
Low level input voltage
Ibias/2
V
IN-L
-300mV
I
Hi level Input current
Low level input current
Pin voltage = Ibias
Pin voltage = 0.3V
1
1
µA
µA
IN-H
I
IN-L
4/9
STA505
ELECTRICAL CHARACTERISTCS (continued)
Symbol Parameter
Test conditions
Min.
Typ.
Max.
Unit
µA
V
I
Hi level PWRDN pin input current Ibias = 3.3V
35
PWRDN-H
V
Low logical state voltage VL (pin
PWRDN, TRISTATE) (note 1)
Ibias = 3.3V
0.8
L
V
High logical state voltage VH (pin Ibias = 3.3V
PWRDN, TRISTATE) (note 1)
1.7
3
V
H
I
Supply current from Vcc in Power PWRDN = 0
Down
mA
VCC-
PWRDN
I
Output Current pins
FAULT
FAULT -TH-WARN when
FAULT CONDITIONS
Vpin = 3.3V
Tri-state=0
1
mA
mA
mA
I
Supply current from Vcc in Tri-
state
22
80
VCC-hiz
I
Supply current from Vcc in
operation
both channel switching)
Input pulse width = 50% Duty;
Switching Frequency = 384Khz;
No LC filters;
VCC
I
Isc (short circuit current limit)
(note 2)
3.5
70
6
7
8
A
VCC-q
I
Undervoltage protection threshold
Output minimum pulse width
V
OUT-SH
V
OV
No Load
150
ns
Notes: 1. The following table explains the VL, VH variation with Ibias
Ibias
2.7
3.3
5
VLmin
0.7
VHmax
1.5
Unit
V
0.8
1.7
V
0.85
1.85
V
Note 2: If used in single BTL configuration, the device may be not short circuit protected
LOGIC TRUTH TABLE (see fig. 2)
OUTPUT
MODE
TRI-STATE
INxA
INxB
Q1
Q2
Q3
Q4
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
ON
Hi-Z
DUMP
ON
OFF
ON
NEGATIVE
POSITIVE
Not used
OFF
ON
OFF
OFF
ON
OFF
5/9
STA505
Figure 1. Test Circuit.
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
DTf
Duty cycle = 50%
INxY
M58
M57
OUTxY
R 8Ω
+
-
V67 =
vdc = Vcc/2
gnd
D03AU1458
Figure 2.
+VCC
Q1
Q2
OUTxA
OUTxB
INxA
INxB
Q3
Q4
GND
D00AU1134
Figure 3.
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
M57
M64
M63
Q1
OUTxA
Iout=3.5A
Q2
Q4
DTin(A)
DTout(B)
DTin(B)
INxB
Rload=8Ω
OUTxB
INxA
L67 22µ
L68 22µ
Iout=3.5A
Q3
C69
470nF
C70
470nF
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 3.5A in the direction shown in figure
D00AU1162
6/9
STA505
Figure 4. Typical Single BTL Configuration to obtain 80W @ THD 10%, R = 8Ω, V = 36V (note 1)
L
CC
IBIAS
+3.3V
23
18
N.C.
22µH
100nF
GND-Clean
GND-Reg
17
16
OUT1A
OUT1A
19
20
100nF
FILM
11
10
100nF
X7R
10K
100nF
X7R
470nF
FILM
100nF
OUT1B
OUT1B
OUT2A
OUT2A
22Ω
1/2W
6.2
1/2W
VDD
VDD
21
22
24
8Ω
6.2
1/2W
CONFIG
9
8
330pF
X7R
TH_WAR
PWRDN
FAULT
TH_WAR
OUT2B
OUT2B
28
25
100nF
FILM
3
2
nPWRDN
22µH
10K
VCC1A
27
26
+36V
15
TRI-STATE
IN1A
1µF
X7R
2200µF
63V
100nF
VCC1B
VCC2A
29
30
31
32
12
7
IN1B
IN1A
IN1B
IN2A
+36V
IN2B
1µF
X7R
VSS
VSS
VCC2B
33
34
4
14
13
GND1A
GND1B
100nF
X7R
VCCSIGN
35
100nF
X7R
V
CCSIGN
GND2A
GND2B
36
1
6
5
Add.
GNDSUB
D01AU1274
Note: 1. "A PWM modulator as driver is needed . In particular, this result is performed using the STA30X+STA50X demo board".
Figure 5. Typical Quad Half bridge Configuration
+VCC
VCC1P
15
17
16
C21
2200µF
IN1A
29
M3
M2
M5
M4
R61
5K
IN1A
C31 820µF
L11 22µH
IBIAS
23
24
+3.3V
OUTPL
C71
100nF
CONFIG
R41
20
C91
1µF
OUTPL
PWRDN
PWRDN
FAULT
25
C81
100nF
14
12
PGND1P
R51
6
R62
5K
C41
330pF
PROTECTIONS
R57
10K
R59
10K
27
26
&
LOGIC
VCC1N
TRI-STATE
C58
100nF
C51
1µF
C61
100nF
11
10
R63
5K
TH_WAR
IN1B
28
30
OUTNL
OUTNL
PGND1N
C32 820µF
L12 22µH
TH_WAR
C72
100nF
R42
20
IN1B
C92
1µF
VDD
VDD
VSS
VSS
21
22
33
34
13
7
C82
100nF
R52
6
R64
5K
C42
330pF
REGULATORS
VCC2P
M17
M15
M16
M14
R65
5K
C58
100nF
C53
100nF
C33 820µF
L13 22µH
VCCSIGN
8
9
35
OUTPR
C60
100nF
C73
100nF
R43
20
V
CCSIGN
IN2A
C93
1µF
36
31
20
19
OUTPR
C83
100nF
6
4
PGND2P
R53
6
R66
5K
IN2A
IN2B
C43
330pF
GND-Reg
V
CC2N
GND-Clean
C52
1µF
C62
100nF
3
2
R67
5K
OUTNR
OUTNR
PGND2N
C34 820µF
L14 22µH
IN2B
32
1
C74
100nF
R44
20
GNDSUB
C94
1µF
5
C84
100nF
R54
6
R68
5K
C44
330pF
D03AU1474
For more information refer to the application notes AN1456 and AN1661
7/9
STA505
mm
inch
DIM.
MIN.
TYP. MAX. MIN.
TYP. MAX.
0.138
0.13
OUTLINE AND
MECHANICAL DATA
A
A2
A4
A5
a1
b
3.25
3.5
3.3
1
0.128
0.031
0
0.8
0.039
0.008
0.003
0.015
0.012
0.630
0.38
0.2
0
0.075
0.22
0.23
15.8
9.4
0.38 0.008
0.32 0.009
c
D
16
0.622
0.37
D1
D2
E
9.8
1
0.039
0.57
13.9
10.9
14.5 0.547
11.1 0.429
2.9
E1
E2
E3
E4
e
0.437
0.114
0.244
1.259
0.026
0.435
0.003
0.625
0.043
0.043
5.8
2.9
6.2
3.2
0.228
0.114
0.65
e3
G
H
h
11.05
0
0.075
15.9
1.1
0
15.5
0.61
L
0.8
1.1
0.031
N
s
10˚ (max)
8˚ (max)
PowerSO36 (SLUG UP)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
7183931
8/9
STA505
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved
DDX is a trademark of Apogee tecnology inc.
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9/9
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