STA516B_10_技术文档

STA516B

65-volt, 7.5-amp, quad power half bridge

Features

! Low input/output pulse-width distortion

! 200 mΩ R

complementary DMOS output

dsON

stage

! CMOS-compatible logic inputs

! Thermal protection

! Thermal warning output

! Undervoltage protection

PowerSO36 package

with exposed pad up

Description

STA516B is a monolithic quad half-bridge stage in

Multipower BCD Technology. The device can be

used as dual bridge or reconfigured, by

connecting pin CONFIG to pins VDD, as a single

bridge with double-current capability or as a half

bridge (binary mode) with half-current capability.

The input pins have a threshold proportional to

the voltage on pin VL.

The STA516B is aimed at audio amplifiers in Hi-Fi

applications, such as home theatre systems,

active speakers and docking stations.

The device is intended for the output stage of a

stereo all-digital high-efficiency amplifier. It is

capable of delivering 200 W + 200 W into 6-Ω

It comes in a 36-pin PowerSO package with

exposed pad up (EPU).

loads with THD = 10% at V = 51 V or, in single

CC

BTL configuration, 400 W into a 3-Ω load with

THD = 10% at V = 52 V.

CC

Table 1.

Order code

STA516B

STA516B13TR

Device summary

Temperature range

0 to 90 °C

Package

Packaging

PowerSO36 EPU

Tube

Tape and reel

November 2010

Doc ID 13183 Rev 4

1/17

www.st.com

17

Introduction

STA516B

1

Introduction

The STA516B is a high performance quad half-bridge amplifier with the capability to drive up

(a)

to 220 W

stereo into 3- to 8-ohm speakers from a single 50 V supply.

It offers the highest flexibility since it can be configured as a stereo-BTL, as a mono-BTL or

as four channels of single-ended outputs to fit different application requirements.

It provides remarkably high levels of efficiency when driven by the FFX-patented 3-state

pulse-width modulator embedded in STMs digital audio processors .

The device is self-protected by design. Overcurrent, overtemperature, under- and

overvoltage protection are provided with an automatic recovery feature to safeguard the

device and speakers against fault conditions that could damage the overall system.

a. The achievable output power depends on the thermal configuration of the final application.

A high performance thermal interface material between the package exposed pad and the heat sink should be

used in order to maximize output power levels

2/17

Doc ID 13183 Rev 4

STA516B

Pin description

2

Pin description

Figure 1.

Pin out

VCC_SIGN

VSS

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

SUB_GND

OUT2B

VCC2B

GND2B

GND2A

VCC2A

OUT2A

OUT1B

VCC1B

GND1B

GND1A

VCC1A

OUT1A

N.C.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

VSS

IN2B

IN2A

IN1B

STA516B

IN1A

TH_WARN

FAULT

TRISTATE

PWRDN

CONFIG

VL

VDD

GND_REG

GND_CLEAN

Table 2.

Pin function

Name

Type

Description

1

GND_SUB

OUT2B

VCC2B

GND2B

GND2A

VCC2A

OUT2A

PWR

O

Substrate ground

Output half bridge 2B

Positive supply

2, 3

4

PWR

O

5

Negative supply

Positive supply

6

7

8, 9

Output half bridge 2A

Output half bridge 1B

Positive supply

10, 11 OUT1B

O

12

13

14

15

VCC1B

GND1B

GND1A

VCC1A

PWR

O

Negative supply

Positive supply

16, 17 OUT1A

Output half bridge 1A

No internal connection

Logical ground

18

19

20

N.C.

-

GND_CLEAN

GND_REG

PWR

Ground for regulator V_DD

5-V regulator referred to ground

21, 22 VDD

23 VL

High logical state setting voltage, V_L

Doc ID 13183 Rev 4

3/17

Pin description

STA516B

Table 2.

Pin function (continued)

Name Type

Description

Configuration pin:

0: normal operation

1: bridges in parallel (OUT1A = OUT1B, OUT2A = OUT2B (If

IN1A = IN1B, IN2A = IN2B))

24

CONFIG

I

Standby pin:

25

26

27

PWRDN

TRISTATE

FAULT

I

0: low-power mode

1: normal operation

Hi-Z pin:

0: all power amplifier outputs in high impedance state

1: normal operation

Fault pin advisor (open-drain device, needs pull-up resistor):

O

0: fault detected (short circuit or thermal, for example)

1: normal operation

Thermal warning advisor (open-drain device, needs pull-up

resistor):

28

TH_WARN

0: temperature of the IC >130 °C

1: normal operation

29

30

31

32

IN1A

IN1B

IN2A

IN2B

I

Input of half bridge 1A

Input of half bridge 1B

Input of half bridge 2A

Input of half bridge 2B

5-V regulator referred to +V_CC

Signal positive supply

I

33, 34 VSS

PWR

35, 36 VCC_SIGN

4/17

Doc ID 13183 Rev 4

STA516B

Electrical specifications

3

Electrical specifications

Table 3.

Symbol

Absolute maximum ratings

Parameter

Value

Unit

V_{CC_MAX}DC supply voltage (pins 4, 7, 12, 15)

65

V

V_max

T_{j_MAX}

T_stg

Maximum voltage on pins 23 to 32

Operating junction temperature

Storage temperature

5.5

V

0 to 150

°C

-40 to 150

Warning: Stresses beyond those listed under “Absolute maximum

ratings” may cause permanent damage to the device. These

are stress ratings only, and functional operation of the device

at these or any other conditions beyond those indicated

under “Recommended operating condition” are not implied.

Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability. In the real

application, power supplies with nominal values rated within

the recommended operating conditions, may experience

some rising beyond the maximum operating conditions for a

short time when no or very low current is being drawn

(amplifier in mute state, for instance). In this case the

reliability of the device is guaranteed, provided that the

absolute maximum rating is not exceeded.

Table 4.

Thermal data

Symbol

Parameter

Min

Typ

Max

2.5

Unit

T_j-case

T_warn

T_jSD

Thermal resistance junction to case (thermal pad)

Thermal warning temperature

-

1

°C/W

°C

130

150

25

-

Thermal shut-down junction temperature

Thermal shut-down hysteresis

°C

t_hSD

°C

Table 5.

Symbol

Recommended operating conditions

Parameter

Min

Typ

Max

Unit

V_CC

Supply voltage for pins PVCCA, PVCCB

Ambient operating temperature

10

0

-

58

90

V

T_amb

°C

Doc ID 13183 Rev 4

5/17

Electrical specifications

STA516B

Unless otherwise stated, the test conditions for Table 6 below are V = 3.3 V, V = 50 V

L

CC

and T

= 25 °C

amb

Table 6.

Symbol

Electrical characteristics

Parameter

Test conditions

I_dd= 1 A

Min

Typ

200

Max

240

Unit

Power P-channel/N-channel

MOSFET R_dsON

R_dsON

I_dss

-

mΩ

Power P-channel/N-channel

leakage Idss

-

50

-

µA

%

Power P-channel R_dsON

matching

g_N

I_dd= 1 A

95

Power N-channel R_dsON

matching

g_P

95

-

%

Dt_s

Low current dead time (static) see Figure 2

10

20

ns

L = 22 µH, C = 470 nF

R_L= 8 Ω, I_dd= 4.5 A

see Figure 3

High current dead time

(dynamic)

Dt_d

-

50

ns

t_{d ON}

Turn-on delay time

Turn-off delay time

Resistive load

-

100

ns

t_{d OFF}

Resistive load

see Figure 2

t_r

t_f

Rise time

Fall time

-

25

ns

V

Resistive load

see Figure 2

V_L/ 2 +

300 mV

V_IN-HighHigh level input voltage

-

V_L/ 2

300 mV

-

V_IN-Low

Low level input voltage

-

V

I_IN-H

I_IN-L

High level input current

Low level input current

V_IN= V_L

-

1

-

µA

V_IN= 0.3 V

High level PWRDN pin input

current

I_PWRDN-H

V_L= 3.3 V

-

35

-

µA

V

Low logical state voltage

(pins PWRDN, TRISTATE)

(seeTable 7)

V_Low

0.8

High logical state voltage

(pins PWRDN, TRISTATE)

(seeTable 7)

V_High

V_L= 3.3 V

-

1.7

2.4

-

V

I_VCC-

Supply current from V_CCin

power down

V_PWRDN= 0 V

V_pin= 3.3 V

-

mA

PWRDN

Output current on pins

FAULT, TH_WARN with fault

condition

I_FAULT

1

22

Supply current from V_CCin

3-state

I_VCC-HiZ

V_TRISTATE= 0 V

-

6/17

Doc ID 13183 Rev 4

STA516B

Electrical specifications

Table 6.

Symbol

Electrical characteristics (continued)

Parameter

Test conditions

Min

Typ

Max

Unit

Input pulse width

= 50% duty,

Supply current from V_CCin

operation, both channels

switching)

I_VCC

switching frequency

= 384 kHz,

-

70

-

mA

no LC filters

Overcurrent protection

threshold Isc (short-circuit

current limit) ⁽¹⁾

I_OCP

-

7.5

-

8.5

7

10

-

A

V

Undervoltage protection

threshold

V_UVP

-

Overvoltage protection

threshold

V_OVP

-

61

50

62.5

-

V

t_{pw_min}

Output minimum pulse width

No load

110

ns

1. See application note AN1994

Table 7.

Threshold switching voltage variation with voltage on pin VL

Voltage on pin VL, V_L

V_LOWmax

V_HIGHmin

Unit

2.7

3.3

5.0

1.05

1.4

1.65

1.95

2.8

V

2.2

Table 8.

Logic truth table

Inputs as per Figure 3

Transistors as per Figure 3

Q1 Q2 Q3 Q4

TRISTATE

Output mode

INxA

INxB

0

1

x

0

1

x

0

1

0

1

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

Hi Z

Dump

Negative

Positive

Not used

Doc ID 13183 Rev 4

7/17

Electrical specifications

STA516B

3.1

Test circuits

Figure 2.

Test circuit

OUTxY

Vcc

(3/4)Vcc

Low current dead time = MAX(DTr,DTf)

(1/2)Vcc

(1/4)Vcc

+Vcc

t

DTr

DTf

Duty cycle = 50%

INxY

M58

M57

OUTxY

R 8Ω

+

-

V67 =

vdc = Vcc/2

gnd

D03AU1458

Figure 3.

Current dead-time test circuit

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

+V_CC

Duty cycle=A

Duty cycle=B

DTout(A)

M58

M57

M64

M63

Q1

OUTxA

Iout=4.5A

Q2

Q4

DTin(A)

INxA

DTout(B)

DTin(B)

INxB

Rload=8Ω

OUTxB

L67 22µ

L68 22µ

Iout=4.5A

Q3

C69

470nF

C70

470nF

C71 470nF

Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure

D00AU1162

8/17

Doc ID 13183 Rev 4

STA516B

Power supply and control sequencing

4

Power supply and control sequencing

To guarantee correct operation and reliability, the recommended power-on/off sequence as

shown in Figure 4 should be followed

Figure 4.

Suggested power-on/off sequence

V

V_cc

V_L

V_cc> V_L

t

PWRDN

IN

t

V

should be turned on before V . This prevents uncontrolled current flowing through the

L

CC

internal protection diode connected between V (logic supply) and V (high power supply).

L

CC

which could result in damage to the device.

PWRDN must be released after V is switched on. An input signal can then be sent to the

L

power stage.

Doc ID 13183 Rev 4

9/17

Applications information

STA516B

5

Applications information

The STA516B is a dual channel H-bridge that is able to deliver 200 W per channel (into

R = 6 Ω with THD = 10% and V = 51V) of audio output power very efficiently. It operates

L

CC

in conjunction with a pulse-width modulator driver such as the STA321 or STA309A.

The STA516B converts ternary, phase-shift or binary-controlled PWM signals into audio

power at the load. It includes a logic interface, integrated bridge drivers, high efficiency

MOSFET outputs and thermal and short-circuit protection circuitry.

In differential mode (ternary, phase-shift or binary differential), two logic level signals per

channel are used to control high-speed MOSFET switches to connect the speaker load to

the input supply or to ground in a bridge configuration, according to the damped ternary

modulation operation.

In binary mode, both full bridge and half bridge modes are supported. The STA516B

includes overcurrent and thermal protection as well as an undervoltage lockout with

automatic recovery. A thermal warning status is also provided.

®

Figure 5.

Block diagram of full-bridge FFX or binary mode

INL[1,2]

INR[1,2]

VL

PWRDN

Logic

interface

and

OUTPL

OUTNL

Left

H-bridge

decode

TRISTATE

OUTPR

OUTNR

FAULT

Protection

Regulators

Right

H-bridge

THWARN

Figure 6.

Block diagram of binary half-bridge mode

INL[1,2]

LeftA

Logic

OUTPL

OUTNL

INR[1,2]

VL

½-bridge

interface

and

PWRDN

TRISTATE

LeftB

decode

½-bridge

RightA

OUTPR

OUTNR

FAULT

½-bridge

Protection

Regulators

THWARN

RightB

½-bridge

5.1

Logic interface and decode

The STA516B power outputs are controlled using one or two logic-level timing signals. In

order to provide a proper logic interface, the VL input must operate at the same voltage as

®

the FFX control logic supply.

10/17

Doc ID 13183 Rev 4

STA516B

Applications information

5.2

Protection circuitry

The STA516B includes protection circuitry for overcurrent and thermal overload conditions.

A thermal warning pin (THWARN, pin 28, open drain MOSFET) is activated low when the IC

temperature exceeds 130 °C, just in advance of thermal shutdown. When a fault condition is

detected an internal fault signal immediately disables the output power MOSFETs, placing

both H-bridges in a high-impedance state. At the same time the open-drain MOSFET of pin

FAULT (pin 27) is switched on.

There are two possible modes subsequent to activating a fault.

"

Shutdown mode: with pins FAULT (with pull-up resistor) and TRISTATE separate, an

activated fault disables the device, signalling a low at pin FAULT output.

The device may subsequently be reset to normal operation by toggling pin TRISTATE

from high to low to high using an external logic signal.

"

Automatic recovery mode: This is shown in the applications circuits below where pins

FAULT and TRISTATE are connected together to a time-constant circuit (R59 and C58).

An activated fault forces a reset on pin TRISTATE causing normal operation to resume

following a delay determined by the time constant of the circuit.

If the fault condition persists, the circuit operation repeats until the fault condition is

cleared.

An increase in the time constant of the circuit produces a longer recovery interval. Care

must be taken in the overall system design not to exceed the protection thresholds

under normal operation.

5.3

5.4

Power outputs

The STA516B power and output pins are duplicated to provide a low-impedance path for the

device bridged outputs. All duplicate power, ground and output pins must be connected for

proper operation.

The PWRDN or TRISTATE pin should be used to set all power MOSFETs to the

high-impedance state during power-up until the logic power supply, V , has settled.

L

Parallel output / high current operation

®

When using the FFX mode output, the STA516B outputs can be connected in parallel to

increase the output current capability to the load. In this configuration the STA516B can

provide up to 400 W into a 3-Ω load.

This mode of operation is enabled with pin CONFIG (pin 24) connected to pin VDD. The

inputs are joined so that IN1A = IN1B, IN2A = IN2B and similarly the outputs

OUT1A = OUT1B, OUT2A = OUT2B as shown in Figure 8.

5.5

Output filtering

A passive 2nd-order filter is used on the STA516B power outputs to reconstruct the analog

audio signal. System performance can be significantly affected by the output filter design

and choice of passive components. Filter designs for 3- and 6-Ω loads are shown in the

applications circuits of Figure 7, Figure 8 and Figure 9.

Doc ID 13183 Rev 4

11/17

Applications information

STA516B

5.6

Applications circuits

Figure 7.

Typical stereo-BTL configuration for 200 W per channel

+V_CC

V_CC1A

15

17

16

C30

1µF

C55

1000µF

IN1A

29

M3

M2

M5

M4

IN1A

L18 22µH

C20

V^L

23

24

+3.3V

OUT1A

CONFIG

100nF

OUT1A

GND1A

C52

330pF

PWRDN

FAULT

25

C99

100nF

14

12

R98

6

PROTECTIONS

R57

10K

R59

10K

27

26

&

C23

470nF

68ΩΩ

LOGIC

V_CC1B

R63 R100

C101

100nF

TRI-STATE

20

6

C58

100nF

C31

1µF

11

10

C21

100nF

TH_WAR

IN1B

28

30

OUT1B

GND1B

TH_WAR

L19 22µH

IN1B

V_DD

V_SS

21

22

33

34

13

7

REGULATORS

V

_CC2A

C32

1µF

M17

M15

M16

M14

C58

100nF

C53

100nF

L113 22µH

V_CCSIGN

8

9

35

OUT2A

C60

100nF

C110

100nF

36

31

20

19

OUT2A

GND2A

C109

330pF

C107

100nF

6

4

R103

6

IN2A

IN2B

IN2A

6 Ω

8Ω

C108

470nF

GND-Reg

V

_CC2B

R104

20

R102

6

C106

100nF

GND-Clean

C33

1µF

3

2

C111

100nF

OUT2B

GND2B

IN2B

32

1

L112 22µH

GNDSUB

5

D00AU1148B

Figure 8 below shows a single-BLT configuration capable of giving 400 W into a 3-Ω load at

10% THD with V = 52 V. This result was obtained using the STA30X+STA50X demo

CC

board. Note that a PWM modulator as driver is required.

Figure 8.

Typical single-BTL configuration for 400 W

V

L

+3.3V

23

18

N.C.

12µH

100nF

GND-Clean

GND-Reg

17

16

OUT1A

19

20

100nF

FILM

11

10

100nF

X7R

10K

100nF

X7R

680nF

FILM

100nF

X7R

OUT1B

OUT2A

22Ω

6.2

1/2W

V_DD

1/2W

21

22

24

3 Ω

4Ω

6.2

1/2W

CONFIG

9

8

330pF

TH_WAR

PWRDN

FAULT

TH_WAR

OUT2B

28

25

100nF

FILM

3

2

nPWRDN

12µH

10K

V

_CC1A

_CC1B

27

26

V

+36V

15

CC

TRI-STATE

IN1A

1µF

2200µF

63V

100nF

X7R

V

29

30

31

32

12

7

IN1B

IN1A

IN1B

V_CC2A

IN2A

+

V3_C6V_C

IN2B

1µF

X7R

V_SS

V_CC2B

33

34

4

14

13

GND1A

GND1B

100nF

X7R

V_CCSIGN

35

100nF

X7R

V_CCSIGN

GNDSUB

GND2A

GND2B

36

1

6

5

Add.

D04AU1545

12/17

Doc ID 13183 Rev 4

STA516B

Applications information

Typical quad half-bridge configuration for 100 W per channel

Figure 9.

+V_CC

V_CC1P

15

17

16

C21

2200µF

IN1A

29

M3

M2

M5

M4

R61

5K

IN1A

C31 820µF

L11 22µH

V

23

24

L

+3.3V

OUTPL

C71

100nF

CONFIG

PWRDN

FAULT

R41

20

C91

1µF

4Ω 3 Ω

OUTPL

PWRDN

25

C81

100nF

14

12

PGND1P

R51

6

R62

5K

C41

330pF

PROTECTIONS

R57

10K

R59

10K

27

26

&

LOGIC

V_CC1N

TRI-STATE

C58

100nF

C51

1µF

C61

100nF

11

10

R63

5K

TH_WAR

IN1B

28

30

OUTNL

PGND1N

C32 820µF

L12 22µH

TH_WAR

C72

100nF

R42

20

IN1B

C92

1µF

4Ω

3 Ω

V_DD

V_SS

21

22

33

34

13

7

C82

100nF

R52

6

R64

5K

C42

330pF

REGULATORS

V_CC2P

M17

M15

M16

M14

R65

5K

C58

100nF

C53

100nF

C33 820µF

L13 22µH

V_CCSIGN

8

9

35

OUTPR

C60

100nF

C73

100nF

R43

20

V_CCSIGN

C93

1µF

4Ω

3 Ω

36

31

20

19

OUTPR

C83

100nF

6

4

PGND2P

R53

6

R66

5K

IN2A

IN2B

C43

330pF

IN2A

GND-Reg

V_CC2N

GND-Clean

C52

1µF

C62

100nF

3

2

R67

5K

OUTNR

PGND2N

C34 820µF

L14 22µH

IN2B

32

1

C74

100nF

R44

20

GNDSUB

3 Ω

4Ω

C94

1µF

5

C84

100nF

R54

6

R68

5K

C44

330pF

D03AU1474

For more information, refer to the applications note AN1994.

Doc ID 13183 Rev 4

13/17

Package mechanical data

STA516B

14/17

Doc ID 13183 Rev 4

STA516B

Package mechanical data

Dimensions in inch

Table 9.

Symbol

PowerSO36 exposed pad up dimensions

Dimensions in mm

Min

Typ

Max

Min

0.128

Typ

Max

0.135

A

3.25

3.10

0.80

-

3.43

3.20

1.00

-

A2

A4

A5

a1

b

-

0.122

0.126

0.039

-

0.031

0.20

-

0.008

0.03

0.22

0.23

-

-0.04

0.38

0.32

16.00

9.80

-

0.001

-

-0.002

0.015

0.013

0.630

0.386

-

0.009

-

c

-

0.009

-

D

15.80

-

0.622

-

D1

D2

E

9.40

-

0.370

-

1.00

-

0.039

13.90

-

14.50

11.10

2.90

6.20

3.20

-

0.547

-

0.571

0.437

0.114

0.244

0.126

-

E1

E2

E3

E4

e

10.90

-

0.429

-

5.80

-

0.228

-

2.90

-

0.114

-

0.65

-

0.026

e3

G

-

11.05

-

0.435

-

0

-

0.08

15.90

1.10

2.60

10 degrees

-

0

-

0.003

0.626

0.043

0.102

10 degrees

-

H

15.50

-

0.610

-

h

-

L

0.80

-

0.031

-

M

N

2.25

-

0.089

-

R

0.6

-

0.024

-

s

8 degrees

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Doc ID 13183 Rev 4

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Revision history

STA516B

7

Revision history

Table 10. Document revision history

Date

Revision

Changes

01-Feb-2007

19-Mar-2007

11-Aug-2009

1

2

3

Initial release.

Update to reflect product maturity

Updated section Description on cover page.

Modified presentation

16-Nov-2010

4

Updated Chapter 3: Electrical specifications on page 5

Added Chapter 5: Applications information on page 10

16/17

Doc ID 13183 Rev 4

STA516B

Please Read Carefully:

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Doc ID 13183 Rev 4

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型号：	STA516B_10
厂家：	ST
描述：	65-volt, 7.5-amp, quad power half bridge 65伏， 7.5安培，四电源半桥
文件：	总17页 (文件大小：212K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STA516B_10 [STMICROELECTRONICS]

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