STD2NB60T4 [STMICROELECTRONICS]
N-CHANNEL 600V - 3.3OHM - 2.6A DPAK/IPAK PowerMESHTM MOSFET; N沟道600V - 3.3OHM - 2.6A DPAK / IPAK PowerMESHTM MOSFET
| 型号： | STD2NB60T4 |
| 厂家： | 
ST |
| 描述： | N-CHANNEL 600V - 3.3OHM - 2.6A DPAK/IPAK PowerMESHTM MOSFET |
| 文件： | 总11页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STD2NB60
STD2NB60-1
N-CHANNEL 600V - 3.3 Ω - 2.6A DPAK/IPAK
PowerMESH™ MOSFET
Table 1. General Features
Figure 1. Package
V
R
I
D
Type
DSS
DS(on)
STD2NB60
STD2NB60-1
600 V
600 V
< 3.6 Ω
< 3.6 Ω
2.6 A
2.6 A
FEATURES SUMMARY
■ TYPICAL R = 3.3 Ω
DS(on)
■ EXTREMELY HIGH dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
3
3
2
1
1
■ VERY LOW INTRINSIC CAPACITANCES
■ GATE CHARGE MINIMIZED
IPAK
TO-251
DPAK
TO-252
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an ad-
vanced family of power MOSFETs with outstand-
ing performances. The new patent pending strip
layout coupled with the Company’s proprietary
edge termination structure, gives the lowest
RDS(on) per area, exceptional avalanche and dv/
dt capabilities and unrivalled gate charge and
switching characteristics.
Figure 2. Internal Schematic Diagram
APPLICATIONS
■ SWITCH MODE POWER SUPPLIES (SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
Table 2. Order Codes
Part Number
STD2NB60T4
STD2NB60-1
Marking
D2NB60
D2NB60
Package
DPAK
Packaging
TAPE & REEL
TUBE
IPAK
REV. 2
April 2004
1/11
STD2NB60/STD2NB60-1
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Value
600
600
30
Unit
V
V
Drain-source Voltage (V = 0)
DS
GS
V
Drain- gate Voltage (R = 20 kΩ)
V
DGR
GS
V
GS
Gate-source Voltage
V
I
D
Drain Current (cont.) at T = 25 °C
2.6
A
C
I
D
Drain Current (cont.) at T = 100 °C
1.6
A
C
(1)
Drain Current (pulsed)
10.4
A
I
DM
P
Total Dissipation at T = 25 °C
50
0.4
4.5
W
tot
C
Derating Factor
W°/C
V/ns
(2)
Peak Diode Recovery voltage slope
dv/dt
T
Storage Temperature
-65 to 150
150
°C
°C
stg
T
Max. Operating Junction Temperature
j
Note: 1. Pulse width limited by safe operating area
2. I ≤ 2.6A, di/dt ≤ 200 A/µs, V ≤ V(
, T ≤ T
BR)DSS j JMAX
SD
DD
Table 4. Thermal Data
Symbol
Parameter
Value
2.5
Unit
°C/W
°C/W
°C
R
Thermal Resistance Junction-case
Max
thj-case
R
Thermal Resistance Junction-ambient Max
100
thj-amb
T
Maximum Lead Temperature For Soldering Purpose
275
l
Table 5. Avalanche Characteristics
Symbol
Parameter
Max Value
Unit
I
Avalanche Current, Repetitive or Not-Repetitive
2.6
A
AR
(pulse width limited by T max, δ < 1%)
j
E
Single Pulse Avalanche Energy
80
mJ
AS
(starting T = 25 °C; I = I ; V = 50 V)
j
D
AR
DD
2/11
STD2NB60/STD2NB60-1
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise specified)
case
Table 6. Off
Symbol
Parameter
Test Conditions
= 250 µA V = 0
Min.
Typ.
Max.
Unit
V
Drain-source
I
600
V
(BR)DSS
D
GS
Breakdown Voltage
Zero Gate Voltage
I
V
DS
V
DS
V
GS
= Max Rating
1
µA
µA
nA
DSS
Drain Current (V = 0)
= Max Rating Tc = 125 °C
50
100
GS
I
Gate-body Leakage
=
30 V
GSS
Current (V = 0)
DS
(1)
Table 7. On
Symbol
Parameter
Test Conditions
= V ; I = 250 µA
Min.
Typ.
4
Max.
5
Unit
V
V
GS(th)
Gate Threshold Voltage
V
V
3
DS
GS
D
R
Static Drain-source On
Resistance
= 10V; I = 1.6 A
3.3
3.6
Ω
DS(on)
GS
D
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
Table 8. Dynamic
Symbol
Parameter
Test Conditions
x R ; I = 1.6 A
Min.
Typ.
Max.
Unit
(1)
Forward
V
V
> I
D(on)
1.2
2
S
DS
DS
DS(on)max
D
g
fs
Transconductance
Input Capacitance
Output Capacitance
C
= 25 V; f = 1 MHz; V = 0
400
57
7
520
77
9
pF
pF
pF
iss
GS
C
oss
C
Reverse Transfer
Capacitance
rss
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
Table 9. Switching On
Symbol
td(on)
tr
Parameter
Turn-on Time
Test Conditions
= 300 V; I = 1.6 A; R = 4.7 Ω
Min.
Typ.
11
Max.
17
Unit
ns
V
V
DD
D
G
Rise Time
V
GS
DD
= 10 V (see test circuit, Figure 16)
7
11
ns
Q
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 480 V; I = 3.3 A; V = 10 V
15
22
nC
nC
nC
g
D
GS
Q
gs
Q
gd
6.2
5.6
Table 10. Switching Off
Symbol
Parameter
Test Conditions
= 480 V; I = 3.3 A; R = 4.7 Ω
Min.
Typ.
11
Max.
16
Unit
ns
t
Off-voltage Rise Time
Fall Time
V
r(Voff)
DD
D
G
t
V
= 10 V (see test circuit, Figure 18)
13
18
ns
f
GS
t
Cross-over Time
18
25
ns
c
3/11
STD2NB60/STD2NB60-1
Table 11. Source Drain Diode
Symbol
Parameter
Test Conditions
Min. Typ.
Max.
3.3
Unit
A
I
Source-drain Current
SD
(1)
Source-drain Current
(pulsed)
13.2
A
I
SDM
(2)
Forward On Voltage
I
I
= 3.3 A; V = 0
1.6
V
SD
GS
V
SD
t
Reverse Recovery Time
Reverse RecoveryCharge
Reverse RecoveryCharge
= 3.3 A; di/dt = 100 A/µs
500
2.1
8.5
ns
µC
A
rr
SD
V
= 100 V; T = 150 °C
DD
j
Q
rr
(see test circuit, Figure 18)
I
RRAM
Note: 1. Pulse width limited by safe operating area
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
Figure 3. Safe Operating Area
Figure 4. Thermal Impedance
Figure 5. Output Characteristics
Figure 6. Transfer Characteristics
4/11
STD2NB60/STD2NB60-1
Figure 7. Transconductance
Figure 8. Gate Charge vs Gate-source Voltage
Figure 9. Static Drain-source On Resistance
Figure 10. Capacitance Variations
Figure 11. Normalized Gate Thresold Voltage
vs Temperature
Figure 12. Normalized On Resistance vs
Temperature
5/11
STD2NB60/STD2NB60-1
Figure 13. Source-drain Diode Forward
Characteristics
6/11
STD2NB60/STD2NB60-1
Figure 14. Unclamped Inductive Load Test
Circuit
Figure 15. Unclamped Inductive Waveforms
Figure 16. Switching Times Test Circuits For
Resistive Load
Figure 17. Gate Charge Test Circuit
Figure 18. Test Circuit For Inductive Load
Switching And Diode Recovery Times
7/11
STD2NB60/STD2NB60-1
PACKAGE MECHANICAL
Table 12. DPAK Mechanical Data
millimeters
inches
Typ
Symbol
Min
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
6.40
4.40
9.35
Typ
Max
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
6.60
4.60
10.10
Min
Max
A
A1
A2
B
0.087
0.035
0.001
0.025
0.204
0.018
0.019
0.236
0.252
0.173
0.368
0.094
0.043
0.009
0.035
0.213
B2
C
0.024
0.031
C2
D
0.024
0.244
0.260
0.181
0.398
E
G
H
L2
L4
V2
0.8
0.60
0°
1.00
8°
0.024
0°
0.039
0°
Figure 19. DPAK Package Dimensions
P032P_B
Note: Drawing is not to scale.
8/11
STD2NB60/STD2NB60-1
Table 13. IPAK Mechanical Data
millimeters
inches
Symbol
Min
2.2
Typ
Max
2.4
Min
Typ
Max
A
A1
A3
B
0.086
0.035
0.027
0.025
0.204
0.094
0.043
0.051
0.031
0.212
0.033
0.9
1.1
0.7
1.3
0.64
5.2
0.9
B2
B3
B5
B6
C
5.4
0.85
0.63
0.012
0.95
0.6
0.6
6.2
6.6
4.6
16.3
9.4
1.2
1
0.037
0.023
0.023
0.244
0.260
0.181
0.641
0.370
0.047
0.039
0.45
0.48
6
0.017
0.019
0.236
0.252
0.173
0.626
0.354
0.031
C2
D
E
6.4
4.4
15.9
9
G
H
L
L1
L2
0.8
0.8
0.031
Figure 20. IPAK Package Dimensions
H
L
D
L2
L1
0068771-E
Note: Drawing is not to scale.
9/11
STD2NB60/STD2NB60-1
REVISION HISTORY
Table 14. Revision History
Date
Revision
Description of Changes
March-1998
14-Apr-2004
1
2
First Issue
Stylesheet update. No content change.
10/11
STD2NB60/STD2NB60-1
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
11/11
相关型号：
©2020 ICPDF网 联系我们和版权申明