STD90N02L_07 [STMICROELECTRONICS]
N-channel 25V - 0.0052Ω - 60A - DPAK - IPAK STripFET™ III Power MOSFET; N沟道25V - 0.0052Ω - 60A - DPAK - IPAK的STripFET ™III功率MOSFET
| 型号： | STD90N02L_07 |
| 厂家： | 
ST |
| 描述： | N-channel 25V - 0.0052Ω - 60A - DPAK - IPAK STripFET™ III Power MOSFET |
| 文件： | 总17页 (文件大小：366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STD90N02L
STD90N02L-1
N-channel 25V - 0.0052Ω - 60A - DPAK - IPAK
STripFET™ III Power MOSFET
Features
RDS(on)
Max
Type
VDSS
ID
STD90N02L
25V
25V
<0.006Ω
<0.006Ω
60A
60A
STD90N02L-1
3
3
2
■ R
* Qg industry’s benchmark
1
DS(ON)
1
■ Conduction losses reduced
■ Switching losses reduced
■ Low threshold device
DPAK
IPAK
■ In compliance with the 2002/95/ec european
directive
Application
Figure 1.
Internal schematic diagram
■ Switching applications
Description
This series of products utilizes the latest
advanced design rules of ST’s proprietary
STripFET™ technology. This is suitable for the
most demanding DC-DC converter application
where high efficiency is to be achieved.
Table 1.
Device summary
Order codes
Marking
Package
Packaging
STD90N02L-1
STD90N02L
D90N02L
D90N02L
IPAK
Tube
DPAK
Tape & reel
November 2007
Rev 4
1/17
www.st.com
17
Contents
STD90N02L - STD90N02L-1
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
6
Test circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
STD90N02L - STD90N02L-1
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
(1)
Drain-source voltage rating
30
25
V
V
V
V
A
A
A
Vspike
VDS
VDGR
VGS
Drain-source voltage (VGS = 0)
Drain-gate voltage (RGS = 20kΩ)
Gate-source voltage
25
20
(2)
Drain current (continuous) at TC = 25°C
Drain current (continuous) at TC = 100°C
60
ID
ID
42
(3)
Drain current (pulsed)
240
IDM
PTOT
Total dissipation at TC = 25°C
Derating factor
70
W
W/°C
mJ
0.47
360
(4)
Single pulse avalanche energy
EAS
Tj
Operating junction temperature
Storage temperature
-55 to 175
°C
Tstg
1. Guaranteed when external Rg=4.7Ω and Tf<Tfmax
2. Value limited by wire bonding
3. Pulse width limited by safe operating area
4. Starting Tj = 25°C, ID = 30A, VDD = 15V
Table 3.
Symbol
Thermal data
Parameter
Value
Unit
Rthj-case Thermal resistance junction-case max.
Rthj-amb Thermal resistance junction-amb max.
2.14
100
275
°C/W
°C/W
°C
Tl
Maximum lead temperature for soldering purpose
3/17
Electrical characteristics
STD90N02L - STD90N02L-1
2
Electrical characteristics
(Tcase =25°C unless otherwise specified)
Table 4.
Symbol
On /off states
Parameter
Test conditions
Min.
Typ.
Max. Unit
Drain-source breakdown
voltage
V(BR)DSS
ID = 25mA, VGS= 0
25
V
V
DS = 20V,
1
µA
µA
Zero gate voltage drain
current (VGS = 0)
IDSS
VDS = 20V,Tc = 125°C
10
Gate body leakage
current (VDS = 0)
IGSS
VGS = 20V
±100
nA
V
VGS(th)
V
DS= VGS, ID = 250µA
VGS= 10V, ID= 30A
GS= 5V, ID= 15A
Gate threshold voltage
1
1.8
0.0052 0.006
0.007 0.011
Ω
Ω
Static drain-source on
resistance
RDS(on)
V
Table 5.
Symbol
Dynamic
Parameter
Test conditions
DS =10V, ID = 18A
Min.
Typ.
Max. Unit
Forward
transconductance
(1)
V
27
S
gfs
Input capacitance
Ciss
Coss
Crss
2050
545
70
pF
pF
pF
Output capacitance
VDS =16V, f=1MHz, VGS=0
Reverse transfer
capacitance
Qg
Qgs
Qgd
VDD=10V, ID = 60A
VGS =5V
Total gate charge
Gate-source charge
Gate-drain charge
17
7.7
3.5
22
3
nC
nC
nC
(see Figure 17)
f=1MHz Gate DC Bias =0
test signal level =20mV
open drain
RG
Gate input resistance
Output charge
0.5
1.5
14
Ω
(2)
VDS =10V, VGS =0V
nC
QOSS
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
2. Qoss.= Coss * D Vin, Coss = Cgd + Cgd. (see Buck converter)
4/17
STD90N02L - STD90N02L-1
Electrical characteristics
Min. Typ. Max Unit
Table 6.
Symbol
Switching times
Parameter
Test conditions
VDD=10V, ID=30A,
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
12
110
18
8
ns
ns
ns
ns
RG=4.7Ω, VGS=5V
(see Figure 16)
Turn-off delay time
Fall time
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
Min. Typ. Max. Unit
ISD
Source-drain current
60
A
A
ISDM
Source-drain current (pulsed)
240
(1)
ISD=30A, VGS=0
Forward on voltage
1.3
V
VSD
trr
ISD=60A, di/dt = 100A/µs,
VDD=15V, Tj=150°C
Reverse recovery time
Reverse recovery charge
Reverse recovery current
36
65
ns
nC
A
Qrr
3.6
(see Figure 18)
IRRM
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
5/17
Electrical characteristics
STD90N02L - STD90N02L-1
2.1
Electrical characteristics (curves)
Figure 2. Safe operating area
Figure 3. Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6. Transconductance
Figure 7. Static drain-source on resistance
6/17
STD90N02L - STD90N02L-1
Electrical characteristics
Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations
Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs
vs temperature
temperature
Figure 12. Source-drain diode forward
characteristics
Figure 13. Normalized B
vs temperature
VDSS
7/17
Electrical characteristics
STD90N02L - STD90N02L-1
Figure 14. Allowable I vs time in avalanche
AV
The previous curve gives the single pulse safe operating area for unclamped inductive
loads, under the following conditions:
P
E
=0.5*(1.3*B
*I
)
D(AVE)
AS(AR)
VDSS AV
=P
*t
D(AVE) AV
Where:
is the allowable current in avalanche
I
AV
P
is the average power dissipation in avalanche (single pulse)
D(AVE)
t
is the time in avalanche
AV
8/17
STD90N02L - STD90N02L-1
Buck converter
3
Buck converter
Figure 15. Synchronous buck converter
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
The low side (SW2) device requires:
Very low R
to reduce conduction losses
DS(on)
Small Q
Small C
to reduce the gate charge losses
GLS
OSS
to reduce losses due to output capacitance
Small Q to reduce losses on SW1 during its turn-on
rr
The C /C ratio lower than Vth/Vgg ratio especially with low drain to source voltage to
gd gs
avoid the cross conduction phenomenon.
The high side (SW1) device requires:
Small R and L to allow higher gate current peak and to limit the voltage feedback on the
G
G
gate
Small Q to have a faster commutation and to reduce gate charge losses
G
Low R
to reduce the conduction losses
DS(on)
9/17
Buck converter
STD90N02L - STD90N02L-1
Low side switch (SW2)
Table 8.
Power losses
High side switch (SW1)
DS(on) • IL2 • δ
R
DS(on) • IL2 • (1 – δ)
R
Pconduction
I
-
I
Pswitching
Zero voltage switching
in • (Qgsth(SW1) + Qgd(SW1)) • f •
1Vin • Qrr(SW2) • f
recovery
Not applicable
Not applicable
Pdiode
conduction
V
f(SW2) • IL • tdeadtime • f
Q
gls(SW2) • Vgg • f
Pgate(Qg)
Q
g(SW1) • Vgg • f
Vin • Qoss(SW2) • f
-------------------------------------------------
2
Vin • Qoss(SW1) • f
-------------------------------------------------
2
PQoss
Table 9.
Power losses parameters
Parameter
Meaning
d
Duty-cycle
Qgsth
Post threshold gate charge
Qgls
Third quadrant gate charge
On state losses
Pconduction
Pswitching
Pdiode
Pgate
On-off transition losses
Conduction and reverse recovery diode losses
Gate driver losses
PQoss
Output capacitance losses
10/17
STD90N02L - STD90N02L-1
Test circuits
4
Test circuits
Figure 16. Switching times test circuit for
resistive load
Figure 17. Gate charge test circuit
Figure 18. Test circuit for inductive load
switching and diode recovery times
Figure 19. Unclamped inductive load test
circuit
Figure 20. Unclamped inductive waveform
Figure 21. Switching time waveform
11/17
Package mechanical data
STD90N02L - STD90N02L-1
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at:www.st.com
12/17
STD90N02L - STD90N02L-1
Package mechanical data
TO-251 (IPAK) MECHANICAL DATA
mm
inch
DIM.
MIN.
2.2
TYP.
MAX.
2.4
MIN.
0.086
0.035
0.027
0.025
0.204
TYP.
MAX.
0.094
0.043
0.051
0.031
0.212
0.033
A
A1
A3
B
0.9
1.1
0.7
1.3
0.64
5.2
0.9
B2
B3
B5
B6
C
5.4
0.85
0.3
0.012
0.95
0.6
0.6
6.2
6.6
4.6
16.3
9.4
1.2
1
0.037
0.023
0.023
0.244
0.260
0.181
0.641
0.370
0.047
0.039
0.45
0.48
6
0.017
0.019
0.236
0.252
0.173
0.626
0.354
0.031
C2
D
E
6.4
4.4
15.9
9
G
H
L
L1
L2
0.8
0.8
0.031
H
L
D
L2
L1
0068771-E
13/17
Package mechanical data
STD90N02L - STD90N02L-1
DPAK MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
A1
A2
B
2.2
0.9
2.4
1.1
0.23
0.9
5.4
0.6
0.6
6.2
0.086
0.035
0.001
0.025
0.204
0.017
0.019
0.236
0.094
0.043
0.009
0.035
0.212
0.023
0.023
0.244
0.03
0.64
5.2
b4
C
0.45
0.48
6
C2
D
D1
E
5.1
0.200
6.4
6.6
0.252
0.260
E1
e
4.7
0.185
0.090
2.28
e1
H
4.4
9.35
1
4.6
0.173
0.368
0.039
0.181
0.397
10.1
L
(L1)
L2
L4
R
2.8
0.8
0.110
0.031
0.6
0°
1
0.023
0°
0.039
8°
0.2
0.008
V2
8°
0068772-F
14/17
STD90N02L - STD90N02L-1
Package mechanical data
6
Package mechanical data
DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
mm
MIN. MAX. MIN. MAX.
330 12.992
inch
DIM.
A
B
C
D
G
N
T
1.5
12.8
20.2
16.4
50
0.059
13.2 0.504 0.520
0.795
18.4 0.645 0.724
1.968
22.4
0.881
BASE QTY
BULK QTY
2500
TAPE MECHANICAL DATA
2500
mm
MIN. MAX. MIN. MAX.
6.8 0.267 0.275
10.4 10.6 0.409 0.417
12.1 0.476
inch
DIM.
A0
B0
B1
D
7
1.5
1.5
1.6 0.059 0.063
0.059
D1
E
1.65 1.85 0.065 0.073
7.4 7.6 0.291 0.299
2.55 2.75 0.100 0.108
F
K0
P0
P1
P2
R
3.9
7.9
1.9
40
4.1 0.153 0.161
8.1 0.311 0.319
2.1 0.075 0.082
1.574
W
15.7
16.3 0.618 0.641
15/17
Revision history
STD90N02L - STD90N02L-1
7
Revision history
Table 10. Document revision history
Date
Revision
Changes
29-Aug-2005
07-Apr-2006
03-May-2006
24-Oct-2007
1
2
3
4
First release
New template
New value on Table 4, new curve (see Figure 14)
Corrected value on Table 6, Updated BVdss value
16/17
STD90N02L - STD90N02L-1
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17/17
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