STE2004S [STMICROELECTRONICS]
102 x 65 single-chip LCD controller/driver; 102 ×65的单芯片LCD控制器/驱动器
| 型号： | STE2004S |
| 厂家： | 
ST |
| 描述： | 102 x 65 single-chip LCD controller/driver |
| 文件： | 总79页 (文件大小：1233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STE2004S
102 x 65 single-chip LCD controller/driver
Description
Features
■ 102 x 65 bits display data RAM
■ Programmable MUX rate
■ Programmable frame rate
■ X,Y programmable carriage return
■ Dual partial display mode
■ Row by row scrolling
The STE2004S is a low power CMOS LCD
controller driver. Designed to drive a 65 rows by
102 columns graphic display, it provides all
necessary functions in a single chip, including
on-chip LCD supply and bias voltages generators,
resulting in a minimum of externals components
and in a very low power consumption.
STE2004S features six standard interfaces
(3-lines Serial, 3-lines SPI, 4-lines SPI, 68000
■ N-line inversion
Parallel, 8080 parallel and I2C) for interfacing with
the host micro-controller.
■ Automatic data RAM blanking procedure
■ Selectable input interface:
– I2C Bus Fast and Hs-mode (read and write)
– 8000 and 8080 Parallel Interfaces (read
and write)
– 3-lines and 4-lines SPI Interface (read and
write)
CO to C101
R0 to R64
OSC_IN
OSC_OUT
FR_IN
TIMING
GENERATOR
OSC
COLUMN
DRIVERS
ROW
DRIVERS
MASTER
SLAVE SYNC
CLOCK
FR_OUT
BIAS VOLTAGE
GENERATOR
DATA
LATCHES
SHIFT
REGISTER
– 3-lines 9 bit Serial Interface (read and
write)
VSENSE SLAVE
VLCD
HIGH VOLTAGE
GENERATOR
VLCDSENSE
65 x 102
RAM
SCROLL
LOGIC
RES
RESET
TEST_MODE
TEST_VREF
TEST
VSSAUX
VDD1,2
■ Fully integrated configurable LCD bias voltage
DISPLAY
CONTROL
LOGIC
DATA
REGISTER
INSTRUCTION
REGISTER
ICON_MODE
EXT
generator with:
VSS
– Selectable multiplication factor (up to 5 )
X
SEL 3
SEL 2
SEL 1
3 & 4 Line SPI
Parallel 8080 Parallel 68K
I2C BUS
9 Bit SERIAL
– Effective sensing for high precision output
– Eight selectable temperature compensation
coefficients
SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0 E/WR R/W- RD D/C
CS
LR0047
to
DB7
■ CMOS compatible inputs
■ Fully integrated oscillator requires no external
components
■ Designed for chip-on-glass (COG)
applications.
■ Low power consumption, suitable for battery
operated systems
■ Logic supply voltage range from 1.7 to 3.6V
■ High voltage generator supply voltage range
from 1.75 to 4.5V
■ Display supply voltage range from 4.5 to 14.5V
■ Backward compatibility with STE2001/2/4
January 2007
Rev 3
1/7979
www.st.com
79
Contents
STE2004S
Contents
1
2
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Supplies voltages and grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal supply voltage generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Master/slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bias levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
LCD voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Temperature coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Display data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2
4.2.1
4.2.2
4.2.3
4-lines SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3-lines SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3-lines 9 bits serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3
Parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3.1
4.3.2
68000-series parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8080-series parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.1
5.2
5.3
5.4
5.5
5.6
Reset (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Power down (PD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Memory blanking procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Checker board procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Scrolling function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Dual partial display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2/79
STE2004S
Contents
ID-number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6
7
7.1
7.2
7.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8
Pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9
10
3/79
Block diagram
STE2004S
1
Block diagram
Figure 1.
STE2004S block diagram
CO to C101
R0 to R64
OSC_IN
OSC
OSC_OUT
TIMING
GENERATOR
COLUMN
DRIVERS
ROW
DRIVERS
FR_IN
MASTER
SLAVE SYNC
CLOCK
FR_OUT
BIAS VOLTAGE
GENERATOR
DATA
LATCHES
SHIFT
REGISTER
VSENSE SLAVE
VLCD
HIGH VOLTAGE
GENERATOR
VLCDSENSE
65 x 102
RAM
SCROLL
LOGIC
RES
RESET
TEST_MODE
TEST_VREF
TEST
VSSAUX
VDD1,2
DISPLAY
CONTROL
LOGIC
DATA
REGISTER
INSTRUCTION
REGISTER
ICON_MODE
EXT
VSS
SEL 3
SEL 2
SEL 1
3 & 4 Line SPI
Parallel 68K
I2C BUS
Parallel 8080
9 Bit SERIAL
SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT
E/WR R/W- RD D/C
CS
DB0
to
LR0047
DB7
4/79
STE2004S
Pin description
2
Pin description
Table 1. Pin description
N°
Pad
Type
Function
1-6
109-141
R0 to R64
O
O
LCD row driver output
C0 to C101
VSS
6-107
LCD column driver output
192-203
156-163
164-171
205-209
GND Ground pads.
VDD1
Supply IC positive power supply
VDD2
Supply Internal generator supply voltages.
Supply Voltage multiplier output
VLCD
Voltage multiplier regulation input. VLCDOUT sensing for output voltage fine
tuning
VLCDSENSE
204
Supply
VSENSE_SLAVE
VSSAUX
145
190-177-147
142
Supply Voltage reference for slave charge pump
O
O
Ground reference for pins configuration
VDD1 reference for pins configuration
Interface mode selection - cannot be left floating
VDD1AUX
SEL3
SEL2
SEL1
Interface
GND/VSSAUX GND/VSSAUX GND/VSSAUX
I2C
152
153
154
GND/VSSAUX GND/VSSAUX
VDD1
GND/VSSAUX
VDD1
SPI 4-Lines 8 bit
SPI 3-Lines 8 bit
Serial 3-Lines 9 bit
SEL1,2,3
I
GND/VSSAUX
GND/VSSAUX
VDD1
VDD1
VDD1
GND/VSSAUX GND/VSSAUX Parallel 8080-series
GND/VSSAUX VDD1 Parallel 68000-series
VDD1
Extended instruction set selection - cannot be left floating
Ext pad config
Instruction set selected
EXT_SET
151
155
I
I
GND or VSSAUX
VDD1
BASIC
EXTENDED
Extended instruction set selection - cannot be left floating
Icon mode pad config
Icon mode status
ICON_MODE
GND or VSSAUX
VDD1
DISBLED
ENABLED
SDOUT
180
179
O
I
Serial and SPI data output - if unused must be left floating
SDIN - Serial and SPI interface data input - cannot be left floating
SDAIN - I2C bus data in - cannot be left floating
SDIN - SDAIN
I
5/79
Pin description
STE2004S
Table 1. Pin description (continued)
N°
Pad
Type
Function
I
I
SCLK - Serial and SPI interface clock - cannot be left floating
SCL - I2C bus clock - cannot be left floating
SCLK - SCL
181
SDA_OUT
SA0
178
149
O
I
I2C Bus data out - if unused must be left floating
I2C slave address BIT 0 - cannot be left floating
I2C slave address BIT 1- cannot be left floating
Parallel interface 8 bit data bus - cannot be left floating
SA1
148
I
DB0 to DB7
182-189
I/O
R/W - 68000 Series Parallel interface read and write control input
- cannot be left floating
I
I
I
I
R/W - RD
175
RD - 8080 Series Parallel interface read enable clock input
- cannot be left floating
E - 68000 Series Parallel interface read and write clock input
- cannot be left floating
E / WR
E / WR
176
176
WR - 8080 Series Parallel interface - write enable clock input
- cannot be left floating
RES
D/C
172
174
I
I
Reset input. Active Low.
Interface data/command selector- cannot be left floating
Serial and Parallel interfaces ENABLE. When Low the incoming data are
clocked In. Cannot be left floating
CS
173
I
TEST_MODE
TEST_VREF
191
146
I
Test Pad - 50 kohm internal pull-down must be connected to VSS/VSSAUX
Test Pad - must be left floating
O
Oscillator Input:
OSC_IN
Configuration
High
Low
Internal oscillator enabled
Internal oscillator disabled
Internal oscillator disabled
OSCIN
144
I
External Oscillator
OSCOUT
FR_OUT
FR_IN
210
211
143
O
O
I
Internal/external oscillator out - if unused must be left floating
Master slave frame inversion synchronization - f unused must be left floating
Master slave frame inversion synchronization - cannot be left floating
Master/slave configuration bit:- cannot be left floating
M/S PIN OSC_OUT FR_OUT
FR_IN
Charge Pump
M/S
100
I
High
Low
ENABLED Enabled
ENABLED Enabled
Disabled AuxVsense disabled
Charge pump in slave
Enabled
mode or ext power
6/79
STE2004S
Pin description
Figure 2.
Chip mechanical drawing
MARK_1
ROW
5
ROW28
ROW31
ROW
COL
0
0
FR_OUT
OSC_OUT
MARK_3
VLCD
STE2004S
VLCDSENSE
VSS
TEST_MODE
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK - SCL
SDOUT
SDIN - SDAIN
SDAOUT
COL 50
COL 51
VSSAUX
E - WR
(0,0)
X
R/W - RD
D/C
Y
CS
RES
MARK_4
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
COL 101
ROW 32
ROW64/ICON
ROW63
ROW 37
ROW60
MARK_2
LR0048
7/79
Pin description
Figure 3.
STE2004S
Improved ALTH and PLESKO driving method
V
LCD
V
V
2
3
∆V (t)
∆V (t)
2
1
ROW 0
R0 (t)
V
V
4
5
V
SS
V
LCD
V
V
2
3
ROW 1
R1 (t)
V
V
4
5
V
SS
V
LCD
V
V
2
3
COL 0
C0 (t)
V
V
4
5
V
SS
V
LCD
V
V
2
3
COL 1
C1 (t)
V
V
4
5
V
SS
SS
SS
V
LCD
- V
- V
V
3
V
LCD
- V
2
V - V
4 5
V (t)
state1
0V
0V
V
3
- V
SS
V - V
SS 5
V
V
- V
LCD
4
V
- V
- V
LCD
SS
- V
LCD
SS
V
3
SS
V
LCD
- V
2
V
4
- V
5
V (t)
state2
0V
0V
V
3
- V
SS
V
SS
- V
5
V
V
- V
LCD
4
- V
LCD
SS
.......
.......
0
..... 64
1
2
3
4
5
6
7
8
9
..... 64
0
1
2
3
4
5
6
7
8
9
FRAME n
FRAME n + 1
D00IN1154
∆V (t) = C1(t) - R0(t)
1
∆V (t) = C1(t) - R1(t)
2
8/79
STE2004S
Circuit description
3
Circuit description
3.1
3.2
Supplies voltages and grounds
VDD2 supplies voltages to the internal voltage generator (see below). If the internal voltage
generator is not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the
IC. VDD1 supply voltage could be different form VDD2
.
2 ⋅ VLCD
V
≥ --------------------------- + 200mV
(n + 4)
DD2
Internal supply voltage generator
The IC has a fully integrated (no external capacitors required) charge pump for the liquid
crystal display (LCD) supply voltage generation. The multiplying factor can be programmed
to be: Auto, X5, X4, X3, X2, using the ’set CP multiplication’ command. If auto is set, the
multiplying factor is automatically selected to have the lowest current consumption in every
condition, allowing an input voltage that changes over time and a constant VLCD voltage.
The output voltage (VLCD) is tightly controlled through the VLCDSENSE pad. For this voltage,
eight different temperature coefficients (TC, rate of change with temperature) can be
programmed using the bits TC1, TC0, T2, T1, T0, to ensure there is no contrast degradation
over the LCD operating range.
An external supply could be connected to VLCD to supply the LCD without using the internal
generator. In such event the internal voltage generator must be programmed to zero (PRS =
[0;0], Vop = 0 - reset condition) and the charge pump (CP[0;0]) set to 5x or quto mode.
3.3
3.4
Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock
for the display system. When used the OSC pad must be connected to VDD1 pad. An
external oscillator could be used and fed into the OSC pin. If an external oscillator is used, it
must be always present when STE2004S is not in power down mode. An oscillator out is
provided on the OSCOUT Pad to cascade two or more drivers.
Master/slave mode
STE2004S supports the master slave working mode for both control logic and charge pump.
This function allows to drive matrix such as 204x65 or 102x130 using two synchronized
STE2004S and the internal charge pump of both devices.
If M/S is connected to VDD1, the driver is configured to work in master mode. When
STE2004S is in master mode, the Vsense_Slave pin is disabled and the VLCD value can be
controlled using Vop bits. The master time generator outputs the relevant timing references
on FR_OUT and OSC_OUT.
If M/S is connected to GND, the driver is configured to work in slave mode. When
STE2004S is in slave mode, the VLCD configuration set by Vop registers and the thermal
compensation slope set by TC register, are neglected. The VLCD value generated is equal
to the voltage value present on the Vsense_Slave pin so the slave configuration can follow
9/79
Circuit description
STE2004S
the master configuration. The only recognized configuration is Vop=0 that forces the charge
pump to be in off state whatever is the value of Vsense_aux.
To synchronize the master and slave timing circuits, the slave driver FR_IN pad must be
connected to master driver FR_OUT pad, and slave driver OSC_IN pad must be connected
to the master driver OSC_OUT Pad (Figure 4.). This connection ensures a synchronization
at both frame level (R0 on the master is driven together with the Slave R0 driver) and at
oscillator level (same frame frequency on the master and on the slave). If the
synchronization at frame level is not required, FR_IN pin must be connected toVDD1 or to
VDD1_aux (Figure 5.).
During the power up procesure, the master device must be forced to exit from power down
before the slave device. To enter into PowerDown mode, the slave device must be forced
into power down state before master device.
Figure 4.
Master slave logic connection with frame synchronization
STE2004S
STE2004S
OSCOUT FROUT
VDD1AUX OSCIN FRIN
OSCOUT FROUT
FRIN OSCIN
LR0219
Figure 5.
Master slave logic connection without frame synchronization
STE2004S
STE2004S
OSCIN
OSCOUT FROUT
VDD1AUX OSCIN FRIN
OSCOUT FROUT
LR0220
VDD1AUX
FRIN
3.5
Bias levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are
generated. The ratios among these levels and VLCD, should be selected according to the
MUX ratio (m). They are established according to the following (Figure 6.)
n + 3
n + 4
n + 2
n + 4
2
n + 4
1
n + 4
------------
------------
------------
------------
V
,
V
,
V
,
V
,
V
,V
LCD SS
LCD
LCD
LCD
LCD
10/79
STE2004S
Circuit description
Figure 6.
Bias level generator
VLCD
R
R
n + 3
n + 4
·VLCD
n + 2
n + 4
·VLCD
nR
R
2
·VLCD
n + 4
1
·VLCD
n + 4
R
VSS
D00IN1150
providing an 1/(n+4) ratio, with n calculated from:
n= m – 3
For m = 65, n = 5, a 1/9 ratio is set.
For m = 49, n =4, a 1/8 ratio is set.
The STE2004S provides three bits (BS0, BS1, BS2) for programming the bias ratio as shown
below:
Table 2. Bias ratio programmable bits
BS2
BS1
BS0
n
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
6
5
4
3
2
1
0
The following table shows the bias level for m = 65 and m = 49:
11/79
Circuit description
STE2004S
Table 3. Bias level m=65 and m=49
Symbol
m = 65 (1/9)
m = 49 (1/8)
V1
V2
V3
V4
V5
V6
VLCD
8/9*VLCD
7/9*VLCD
2/9*V VLCD
1/9 *VLCD
VSS
VLCD
7/8*VLCD
6/8*VLCD
2/8*VLCD
1/8*VLCD
VSS
3.6
LCD voltage generation
The LCD voltage at reference temperature (To = 27°C) can be set using the VOP register content
according to the following formula:
VLCD(T=To) = VLCDo = (Ai+VOP · B)
with the following values:
(i=0,1,2)
Table 4. LCD voltage generation
Symbol
Value
Unit
Note
Ao
A1
A2
B
2.95
6.83
V
V
PRS = [0;0]
PRS = [0;1]
PRS = [1;0]
10.71
0.0303
27
V
V
To
°C
Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register
and PRS bits are set to zero the internal voltage generator is switched off.
The proper value for the VLCD is a function of the liquid crystal threshold voltage (Vth) and
of the multiplexing rate. A general expression for this is:
1 +
--------------------------------------
⋅ V
m
V
=
LCD
th
1
⎛
⎞
2 ⋅ 1 – --------
⎝
⎠
m
For MUX Rate m = 65 the ideal VLCD is:
V
LCD(to) = 6.85 · Vth
than:
(6.85 ⋅ V – A )
th
i
V
= --------------------------------------------
op
0.03
12/79
STE2004S
Circuit description
3.7
Temperature coefficients
As the viscosity, and therefore the contrast, of the LCD are subject to change with
temperature, the LCD voltage must be varied with temperature. STE2004S provides eight
different temperature coefficients to change the VLCD in a linear fashion against
temperature. selectable through T2, T1 and T0 bits. Only four of the temperature coefficients
are available through the basic instruction set.
Table 5. Temperature coefficients with basic instruction set
NAME
TC1
TC0
Value
Unit
TC0
TC2
TC3
TC6
0
0
1
1
0
1
0
1
-0.0· 10-3
-0.7 · 10-3
-1.05· 10-3
-2.1 · 10-3
1/ °C
1/°C
1/°C
1/°C
Table 6. Temperature coefficients
NAME
T2
T1
T0
Value
Unit
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-0.0· 10-3
-0.35 · 10-3
-0.7 · 10-3
-1.05· 10-3
-1.4 · 10-3
-1.75· 10-3
-2.1 · 10-3
-2.3· 10-3
1/ °C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
Figure 7.
Temperature coefficients
LCD
V
B
2
A
1
A
0
A + B
1
A
00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh
O
V
PRS = [0;0]
PRS = [0;1]
PRS = [1;0]
Finally, the V
voltage at a given (T) temperature can be calculated as:
VLCD(T) = VLCDo · [1 + (T-To) · TC]
LCD
13/79
Circuit description
STE2004S
3.8
Display data RAM
The STE2004S, provides an 102X65 bits static RAM to store display data. This is organized
into 9 (Bank0 to Bank8) banks with 102 bytes. One of these banks can be used for icons.
RAM access is accomplished in either one of the bus interfaces provided (see below).
Allowed addresses are X0 to X101 (Horizontal) and Y0 to Y8 (Vertical).
There are four address mode provided to write to RAM:
●
●
●
●
Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on
the left of the memory map. The X pointer is increased after each byte written. After the
last column address (X=X-Carriage), Y address pointer jumps to the following bank and
X restarts from X=0. (Figure 8.)
Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the
left of the memory map. The Y pointer is increased after each byte written. After the last
Y bank address (Y=Y-Carriage), X address pointer jumps to next column and Y restarts
from Y=0 (Figure 9).
Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on
the right of the memory map. The X pointer is increased after each byte written. After
the last column address (X=X-Carriage), Y address pointer jumps to the next bank and
X restarts from X=0 (Figure 10.).
Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the
right of the memory map. The Y pointer is increased after each byte written. After the
last Y bank address (Y=Y-Carriage), the X pointer jumps to next column and Y restarts
from Y=0 (Figure 11.).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always
jumps to the cell with address (X;Y) = (0;0) (Figure 12. Figure 13. Figure 14. Figure 15.).
Data bytes in the memory could have the MSB either on top (D0 = 0, Figure 16.) or on the
bottom (D0=1, Figure 17.).
The STE2004S also allows the normal output address to be altered. The display is mirrored
along the X axis if a logic one MY bit is set. Only the memory read process is altered, the
content is not affected in memory.
When ICON MODE=1 the icon row is not mirrored with MY and is not scrolled.
When ICON MODE=0 the icon row is like an other graphic line and is mirrored and scrolled.
When the partial display mode is disabled, there are three multiplex ratios available (MUX
33, MUX 49 and MUX 65). Only a subset of writable rows are output on row drivers in MUX
33,49 and 65 modes.
When Y-Carriage<MUX/8, if MUX 49 is selected only the first 49 memory rows are
visualized; if MUX 33 selected, only the first 33 memory rows. The unused output row and
column drivers must be left floating.
When Y-Carriage<=MUX/8 the icon bank is located to BANK 8 in MUX 65 Mode, to BANK6
in MUX 49 Mode, and to BANK 4 in MUX 33 Mode.
In MUX 33 and MUX 49 modes and Y-Carriage>MUX/8, only lines 33 and 49 are
visualized.
The lines of DDRAM connected on the output drivers using the scrolling function (Range: 0-
Y-Carriage*8) are selectable. When Y-Carriage>MUX/8 lines, the icon row is moved in
DDRAM to the first row of the bank, corresponding to the Y-CARRIAGE Return value, being
always connected on the same output Driver.
14/79
STE2004S
Circuit description
When MY=0, the icon Row is output on R64 in MUX 65 mode, on R56 in MUX 49, and on
R48 in MUX33.
When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever the MUX rate.
Figure 8.
Automatic data RAM writing sequence with V=0 and data RAM normal
format (MX=0)(a)
0
1
2
3
98
99 100 101
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
LR0049
Figure 9.
Automatic data RAM writing sequence with V=1 and data RAM normal
format (MX=0)(a)
0
1
2
3
98
99 100 101
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
LR0050
a. X Carriage=101; Y-Carriage = 8
15/79
Circuit description
STE2004S
Figure 10. Automatic data RAM writing sequence with V=0 and data RAM mirrored
format (MX=1)(a)
101 100 99
98
3
2
1
0
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
LR0051
Figure 11. Automatic data RAM writing sequence with V=1 and data RAM mirrored
format (MX=1)(a)
101 100 99
98
3
2
1
0
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
LR0052
Figure 12. Automatic data RAM writing sequence with X-Y carriage return
(V=0; MX=0)
X CARR
0
1
2
3
98
99 100 101
BANK
BANK
BANK
0
1
2
Y CARR
BANK 7
BANK 8
LR0053
16/79
STE2004S
Circuit description
Figure 13. Automatic data RAM writing sequence with X-Y carriage return
(V=1; MX=0)
X CARR
0
1
2
3
98
99 100 101
BANK
BANK
BANK
0
1
2
Y CARR
BANK 7
BANK 8
LR0054
Figure 14. Automatic data RAM writing sequence with X-Y carriage return
(V=0; MX=1)
X CARR
101 100 99
98
3
2
1
0
BANK
BANK
BANK
0
1
2
Y CARR
BANK 7
BANK 8
LR0055
Figure 15. Automatic data RAM writing sequence with X-Y carriage return (V=1;
MX=1)
X CARR
101 100 99
98
3
2
1
0
BANK
BANK
BANK
0
1
2
Y CARR
BANK 7
BANK 8
LR0056
17/79
Circuit description
Figure 16. Data RAM Byte organization with D0 = 0
STE2004S
MSB
0
1
2
3
98
99 100 101
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
LSB
LR0057
Figure 17. Data RAM byte organization with D0 = 1
LSB
0
1
2
3
98
99 100 101
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
MSB
LR0058
18/79
STE2004S
Circuit description
Figure 18. Memory rows vs. row drivers mapping ICON_MODE=1 and MUX 65
D
a
t
Y Address
ROW Output
Normal Reverse
direction direction
Line
D3 D2 D1 D0
Address
a
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R63
R62
R61
R60
R59
R58
R57
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
R25
R24
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
R1
R2
R3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
Y-CARRIAGE
R8
R7
R6
R5
R4
Page 7
Page 8
0
1
1
0
1
0
1
0
R3
R2
R1
R0
R64
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
lr0268
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
5
C
O
L
4
C
O
L
3
C
O
L
2
C
O
L
1
C
O
L
0
C
O
L
Reverse
Direction
O
L
98 97 96 95
101
100 99
6
19/79
Circuit description
STE2004S
Figure 19. Memory rows vs. row drivers mapping ICON_MODE=0 and MUX 65
D
a
t
Y Address
ROW Output
Normal Reverse
direction direction
Line
D3 D2 D1 D0
Address
a
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
R0
R64
R63
R62
R61
R60
R59
R58
R57
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
R25
R24
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
R1
R2
R3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
Y-CARRIAGE
R8
R7
R6
Page 7
Page 8
R5
0
1
1
0
1
0
1
0
R4
R3
R2
R1
R0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
5
C
O
L
4
C
O
L
3
C
O
L
2
C
O
L
1
C
O
L
0
C
O
L
Reverse
Direction
lr0269
98 97 96 95
100 99
6
20/79
STE2004S
Circuit description
Figure 20. Memory rows vs. Row drivers mapping ICON_MODE=1, Y-Carriage<=6 and
MUX 49
D
a
t
Y Address
ROW Output
Normal Reverse
direction direction
Line
D3 D2 D1 D0
Address
a
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
R1
R2
R3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
R8
R7
R6
R5
R4
R3
R2
R1
R0
R56
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
4
C
O
L
3
C
O
L
2
C
O
L
1
C
O
L
0
C
O
L
5
C
O
L
Reverse
Direction
lr0270
98 97 96 95
100 99
6
21/79
Circuit description
STE2004S
Figure 21. Memory rows vs. row drivers ;apping ICON_MODE=0, Y-Carriage<=6 and
MUX 49
D
a
t
Y Address
ROW Output
Normal Reverse
direction direction
Line
D3 D2 D1 D0
Address
a
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
R1
R2
R3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
R8
R7
R6
R5
R4
R3
R2
R1
R0
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
4
C
O
L
3
C
O
L
2
C
O
L
1
C
O
L
0
C
O
L
5
C
O
L
lr0271
Reverse
Direction
98 97 96 95
100 99
6
22/79
STE2004S
Circuit description
Figure 22. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage=7,
scrolling pointer>07h and MUX 49
D
a
a
Y Address
ROW Output
Normal Reverse
direction direction
Line
t
D3 D2 D1 D0
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
R1
R2
R3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
R8
R7
R6
R5
R4
R3
R2
R1
R0
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
3
C
O
L
2
C
O
L
1
C
O
L
0
lr0275
C
O
L
C
O
L
Reverse
Direction
96
98 97
95
5
4
101 100 99
6
23/79
Circuit description
STE2004S
Figure 23. Memory rows vs. row drivers mapping ICON_MODE=1, Y-Carriage=7,
scrolling pointer>07h and MUX 4
9
D
a
a
Y Address
ROW Output
Normal Reverse
direction direction
Line
t
D3 D2 D1 D0
Address
R0
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
R1
R2
R3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
R8
R7
R6
R5
R4
R3
R2
R1
R0
R56
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
3
C
O
L
2
C
O
L
1
C
O
L
0
lr0276
C
O
L
C
O
L
Reverse
Direction
96
98 97
95
5
4
101 100 99
6
24/79
STE2004S
Circuit description
Figure 24. Memory rows vs. row drivers mapping ICON_MODE=1, Y-carriage=8,
Scrolling pointer<10h and MUX 49
D
a
a
Y Address
ROW Output
Normal Reverse
direction direction
Line
t
D3 D2 D1 D0
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
R1
R2
R3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R4
R5
R6
R7
R8
R9
Scrolling Pointer
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
R8
R7
R6
R5
R4
R3
R2
R1
R0
R56
Page 7
Page 8
0
1
1
0
1
0
1
0
Y-CARRIAGE
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
LR0273
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
3
C
O
L
2
C
O
L
1
C
O
L
0
C
O
L
C
O
L
Reverse
Direction
96
98 97
95
5
4
101 100 99
6
25/79
Circuit description
STE2004S
Figure 25. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage=8,
Scrolling pointer<10h and MUX 49
D
ROW Output
Normal Reverse
direction direction
Y Address
a
t
Line
D3 D2 D1 D0
a
Address
R0
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
D0
D1
D2
R1
R2
R3
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R4
R5
R6
R7
R8
R9
Scrolling Pointer
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
R8
R7
R6
R5
R4
R3
R2
R1
R0
Page 7
Page 8
0
1
1
0
1
0
1
0
Y-CARRIAGE
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
LR0274
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
3
C
O
L
2
C
O
L
1
C
O
L
0
C
O
L
C
O
L
Reverse
Direction
96
98 97
95
5
4
101 100 99
6
26/79
STE2004S
Circuit description
Figure 26. Memory rows vs. row drivers mapping ICON_MODE=1, Y-carriage<=4 and
MUX33
D
a
a
Y Address
ROW Output
Normal Reverse
direction direction
Line
t
D3 D2 D1 D0
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R15
R14
R13
R12
R11
R10
R9
R1
R2
R3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
Scrolling Pointer
Page 2
Page 3
Page 4
Page 5
Page 6
R8
R7
R6
R5
R4
R3
R2
R1
R0
R48
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
3
C
O
L
2
C
O
L
1
C
O
L
0
C
O
L
C
O
L
Reverse
Direction
LR0272
96
98 97
95
5
4
101 100 99
6
27/79
Circuit description
STE2004S
Figure 27. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage<=4 and
MUX 33
D
a
a
Y Address
ROW Output
Normal Reverse
direction direction
Line
t
D3 D2 D1 D0
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
R1
R2
R3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
Scrolling Pointer
Page 2
Page 3
Page 4
Page 5
Page 6
R8
R7
R6
R5
R4
R3
R2
R1
R0
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
3
C
O
L
2
C
O
L
1
C
O
L
0
C
O
L
C
O
L
Reverse
Direction
LR0272
96
98 97
95
5
4
101 100 99
6
28/79
STE2004S
Circuit description
Figure 28. Row drivers vs. LCD panel interconnection in MUX65 mode
ICON
MUX 65
COLUMN DRIVERS
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R
R
R
R
R
R
R
R
R
R
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
0
1
2
3
4
5
6
7
8
9
ROW DRIVERS
ROW DRIVERS
STE2004S
R30
R31
LR0109
Figure 29. Row drivers vs. LCD panel interconnection in MUX49 mode
ICON
MUX 49
COLUMN DRIVERS
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R
R
R
R
R
R
R
R
R
R
0
1
2
3
4
5
6
7
8
9
R10
R11
R12
ROW DRIVERS
ROW DRIVERS
R13
R14
R15
R16
R17
STE2004S R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
LR0108
29/79
Circuit description
Figure 30. Row drivers vs. LCD panel interconnection in MUX33 mode
STE2004S
ICON
MUX 33
COLUMN DRIVERS
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R
R
R
R
R
R
R
R
R
R
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
0
1
2
3
4
5
6
7
8
9
ROW DRIVERS
ROW DRIVERS
R50 STE2004S
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R30
R31
LR0107
30/79
STE2004S
Bus interfaces
4
Bus interfaces
To provide the widest flexibility and ease of use the STE2004S features six different
methods for interfacing the host controller. To select the desired interface the SEL1, SEL2
and SEL3 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH
(connect to VDD). All the I/O pins of the unused interfaces must be connected to GND.
All interfaces work while the STE2004S is in power down.
Table 7. Bus interfaces
SEL3
SEL2
SEL1
Interface
Note
Read and write; fast and
high speed mode
0
0
0
I2C
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
SPI 4 lines 8 bit
SPI 3 lines 8 bit
Read and write
Read and write
Read and write
Read and write
Read and write
Serial 3 lines 9 bit
Parallel 8080-series
Parallel 68000-series
2
4.1
I C Interface
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast
(400kHz Clock) and High Speed Mode (3.4MHz).
This bus is intended for communication between different LCs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL
lines must be connected to a positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
–
–
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is
high. Changes in the data line while the clock line is high are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock
is High, define the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock
signal is High, defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the
data line is stable for the duration of the High period of the clock signal. The data on the line
may be changed during the Low period of the clock signal. There is one clock pulse per bit
of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and the stop conditions is not
31/79
Bus interfaces
STE2004S
limited. The information is transmitted byte-wide and each receiver acknowledges with the
ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device
that gets the signals is called "receiver". The device that controls the message is called
"master". The devices that are controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This
acknowledge bit is a low level put on the bus by the receiver, whereas the master generates
an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master receiver must generate an acknowledge after the reception of
each byte that has been clocked out of the slave transmitter. The device that acknowledges
has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and
hold time must be taken into account. A master receiver must signal an end-of-data to the
slave transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this case, the transmitter must leave the data line High to enable the
master to generate the STOP condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line.
Having the acknowledge output (SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track
resistance from the SDAOUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. It is possible that during the acknowledge cycle the STE2004S will not be able to
create a valid logic 0 level. By splitting the SDA input from the output the device could be
used in a mode that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid LOW level.
To be compliant with the I2C-bus Hs-mode specification the STE2004S is able to detect the
special sequence "S00001xxx". After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in
Hs-mode without detecting the master code.
Figure 31. Bit transfer and start,stop conditions definition
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CHANGE OF
STOP
CONDITION
DATA ALLOWED
CONDITION
LR0069
32/79
STE2004S
Bus interfaces
2
Figure 32. Acknowledgment on the I C-bus
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
MSB
LSB
DATA OUTPUT
BY RECEIVER
LR0070
4.1.1
Communication protocol
The STE2004S is an I2C slave. The access to the device is bi-directional as data write and
status read are allowed.
The STE2004S has four device addresses. All have the first 5 bits (01111) in common. The
two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs
to a logic 0 or logic 1.
To start the communication between the bus master and the slave LCD driver, the master
must initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA
bus line (most significant bit first). This consists of the 7-bit device select code, and the 1-bit
read/write designator (R/W).
All slaves with the corresponding address acknowledge in parallel, while the rest ignore the
I2C-bus transfer.
Writing mode
When the R/W bit is set to logic 0, the STE2004S is set to be a receiver. After the slaves
acknowledge, one or more command word follows to define the status of the device.
A command word is composed of three bytes. The first is a control byte which defines the
Co and D/C values, the second and third are data bytes. The Co bit is the command MSB
and defines whether this command is followed by two data bytes and and another command
word, or if a stream of data follows (Co = 1 Command word, Co = 0 Stream of data). The
D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/C
= 0 Command).
If Co =1 and D/C = 0, the incoming data byte is decoded as a command, and if Co =1 and
D/C =1, the following data byte is stored in the data RAM at the location specified by the
data pointer.
Every byte of a command word must be acknowledged by all addressed units.
After the last control byte, if D/C is set to a logic 1, the incoming data bytes are stored inside
the STE2004S display RAM starting at the address specified by the data pointer. The data
pointer is automatically updated after every byte written and in the end points to the last
RAM location written.
Every byte must be acknowledged by all addressed units.
33/79
Bus interfaces
Reading mode
STE2004S
If the R/W bit is set to logic 1 the chip outputs data immediately after the slave address. If
the D/C bit during the last write access is set to a logic 0, the byte read is the status byte.
Figure 33. Communication protocol
WRITE MODE
DRIVER ACK
DRIVER ACK
DRIVER ACK
DRIVER ACK
DRIVER ACK
S S
A A
S
0
1
1
1
1
0
A
1
DC Control Byte
A
DATA Byte
A
0
DC Control Byte
A
DATA Byte A P
1
0
R/W Co
SLAVE ADDRESS
Co
LAST
CONTROL BYTE
N> 0 BYTE
MSB........LSB
COMMAND WORD
READ MODE
DRIVER ACK
MASTER ACK
P
S S
A A
S S R
H H H
E [1][0]
C D
o C
S
0
1
1
1
1
1
A
0
1
1
1
1
A A
/
0
0
0
A
1
0
1
0 W
DRIVER
SLAVE ADDRESS
R/W
CONTROL BYTE
LR0008
4.2
Serial interfaces
STE2004S can feature three different serial synchronized interfaces with the host controller. It is
possible to select a 3-lines SPI, a 4-lines SPI or 3-line 9 bits serial interface.
4.2.1
4-lines SPI interface
The STE2004S 4-lines serial interface is a bidirectional link between the display driver and the
application supervisor. It consists of four lines: one/two for data signals (SDIN, SOUT), one for
clock signals (SCLK), one for the peripheral enable (CS) and one for mode selection (SD/C).
The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial
peripheral power consumption is zero. While CS pin is high the serial interface is kept in reset.
The STE2004S is always a slave on the bus and receives the communication clock on the SCLK
pin from the master.
Information is exchanged byte-wide. During data transfer, the data line is sampled on the positive
SCLK edge.
SD/C line status indicates whether the byte is a command (SD/C =0) or a data (SD/C =1); SD/C
line is read on the eighth SCLK clock pulse during every byte transfer.
If CS stays low after the last bit of a command/data byte, the serial interface expects the MSB of
the next byte at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all
the internal registers are cleared.
If CS is low after the positive edge of RES, the serial interface is ready to receive data.
2
Throughout SDOUT, the driver I C slave address or the status byte can be read. The command
2
sequence to read the I C slave address or the status byte is shown in Figure 34., Figure 35.,
34/79
STE2004S
Bus interfaces
Figure 36.. SDOUT is in high impedance in steady state and during data write. It is possible to
short circuit SDOUT and SDIN and read the I2C address or status byte without any additional
lines.
Figure 34. 4-lines serial bus protocol - one byte transmission
CS
D/C
SCLK
SDIN
MSB
LSB
LR0071
Figure 35. 4-lines serial bus protocol - several byte transmission
CS
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
LR0072
Figure 36. 4-lines serial bus protocol - I2C address or status byte read
CS
SCLK
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
SDIN
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
High-Z
High-Z
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ID Number
SDOUT
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
STATUS BYTE
DATA Read
LR00076
Command Write
35/79
Bus interfaces
Figure 37. 4-lines SPI reading sequence
STE2004S
READING SEQUENCE
Write a "00000000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 8 pulses on SCLK and
Read the ID Number or the Status Byte On SDOUT1
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
.
LR0078
4.2.2
3-lines SPI interface
The STE2004S 3-lines serial interface is a bidirectional link between the display driver and
the application supervisor.
It consists of three lines: one/two for data signals (SDIN,SDOUT), one for clock signals
(SCLK) and one for peripheral enable (CS).
If the R/W bit is set to logic 0 the STE2004S is set to be a receiver. One or more command
words follow to define the status of the device.
A command word is composed by two bytes. The first is a control byte which defines Co,
D/C, R/W H[1;0] and HE values, the second is a data byte (Figure 38.). The Co bit is the
command MSB and defines whether the command is followed by one data byte and an
other command word, or if it is followed by a stream of commands, or a steam of DDRAM
data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines whether the data
byte is a command or DDRAM data (D/C = 1 RAM Data, D/C = 0 Command). The H[1;0] bits
define the instruction Set Page if HE bit =1. If HE bit is set to 0, H[1;0] values are neglected
and it is possible to update the instruction set page number using only the related instruction
in the instruction set.
If Co =1 and D/C = 0, the incoming data byte is decoded as a command, and if Co =1 and
D/C =1, the following data byte is stored in the data RAM at the location specified by the
data pointer.
After the last control byte, if D/C is set to a logic 1, the incoming data bytes are stored inside
the STE2004S display data RAM starting at the address specified by the data pointer. The
data pointer is automatically updated after every byte written and in the end points to the last
RAM location written.
36/79
STE2004S
Bus interfaces
Throughout SDOUT can be read the driver I2C slave address or the status byte. The
command sequence that allows to read I2C slave address or the status byte is shown in
Figure 39. and Figure 40..
If the R bit is set to logic 0 and D/C=0, the I2C slave address is read. If the R bit is set to logic
1 and D/C=0, the the I2C slave address is read. SDOUT is in high impedance in steady state
and during data write.
It is possible to short circuit SDOUT and SDIN and read the I2C address or status byte
without any additional line.
Figure 38. 3-lines serial interface protocol in writing mode
WRITE MODE
R
/
W
H H H
E [1][0]
C D
o C
1
Control Byte
DATA Byte
0
Control Byte
LAST
DATA Byte
0 0
CONTROL BYTE
Co
N> 0 BYTE
MSB........LSB
Co
COMMAND WORD
Control Byte
CONTROL BYTE
TRANSFERRED
ONLY COMMANDS
0
0
DATA Byte
DATA Byte
DATA Byte = Command
if D/C=0
LAST
CONTROL BYTE
N> 0 BYTE
MSB........LSB
DATA Byte = DDRAM Data if D/C=1
Control Byte
TRANSFERRED
ONLY DDRAM DATA
0
1
DATA Byte
DATA Byte
LAST
CONTROL BYTE
N> 0 BYTE
MSB........LSB
LR0002
Figure 39. 3-lines SPI interface protocol in reading mode
CS
SCLK
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
SDIN
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Co=1
D/C=0
R/W=1
"Command" "Read"
High-Z
High-Z
High-Z
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ID-Number
SDOUT
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
STATUS BYTE
DATA Read
LR0077
Command Write
37/79
Bus interfaces
Figure 40. 3-lines SPI reading sequence
STE2004S
READING SEQUENCE
Set Co bit =1, D/C Bit =0 R/W Bit =1
SDOUT Buffer become active (Low Impedence)
Source 8 pulses on SCLK and
1
Read the ID-Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
.
LR0079
4.2.3
3-lines 9 bits serial interface
The STE2004S 3-lines serial interface is a bidirectional link between the display driver and
the application supervisor.
It consists of three lines: one/two for data signals (SDIN, SDOUT), one for clock signals
(SCLK) and one for peripheral enable (CS).
The serial interface is active only if the CS line is set to a logic 0. When CS line is high the
serial peripheral power consumption is zero. While CS pin is high the serial interface is kept
in reset.
The STE2004S is always a slave on the bus and receives the communication clock on the
SCLK pin from the master.
Information is exchanged word-wide. The word is composed of 9 bits. The first bit is named
SD/C and indicates whether the following byte is a command (SD/C =0) or data byte (SD/C
=1). During data transfer, the data line is sampled on the positive SCLK edge.
If CS stays low after the last bit of a command/data byte, the serial interface expects the
SD/C bit of the next word at the next SCLK positive edge. A reset pulse on RES pin
interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared. If CS is low after the positive edge of RES, the serial interface is ready
to receive data.
Throughout SDOUT, only the driver I2C slave address or the status byte can be read. The
command sequence that the I2C slave address or status byte to be read is shown in Figure
43. and Figure 44.. SDOUT is in high impedance in steady state and during data write.
38/79
STE2004S
Bus interfaces
It is possible to short circuit SDOUT and SDIN, and read the I2C address or status byte
without any additional line.
Figure 41. 3-lines serial bus protocol - one byte transmission
CS
SCLK
SDIN
SD/C
MSB
LSB
LR0073
Figure 42. 3-lines serial bus protocol - several byte transmission
CS
SCLK
SDIN
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D/C
DB7
DB6
LR0074
Figure 43. 3-lines serial interface protocol in Reading Mode
CS
SCLK
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
SDIN
SD/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
High-Z
High-Z
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ID-Number
SDOUT
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
STATUS BYTE
LR0075
DATA Read
Command Write
39/79
Bus interfaces
Figure 44. 3-lines serial reading sequence
STE2004S
READING SEQUENCE
Write a "00000000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 9 pulses on SCLK and
Read the ID Number or the Status Byte On SDOUT1
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
.
LR0080
4.3
Parallel interface
The STE2004S selectable parallel interfaces are 68000-series and 8080-series. They are
both an 8-bits bi-directional link between the display driver and the application supervisor.
Both parallel interfaces can be read the I2C driver slave address or the status byte.
4.3.1
68000-series parallel interface
If CS is low after the positive edge of RES, the 68000 parallel interface is ready to receive or
transmit data.
While CS pin is high the 68000 parallel interface is kept in reset.
Write mode
If R/W line is set to 0, data is latched on the E falling edge.
Read mode
When R/W line is set to 1, data is output on the D0-D7 bus on the E rising edge. The data
bus is set in high impedance mode when E is set to logic 0.
The I2C address or status byte is output on D0-D7 bus, according to R bit value.
40/79
STE2004S
Bus interfaces
Figure 45. 68000-series parallel interface protocol - one byte transmission
CS
R/W
D/C
E
D0
to
D7
LR0004
Figure 46. 68000-series parallel interface bus protocol - several bytes transmission
CS
R/W
D/C
E
D0
to
D7
LR0081
Figure 47. 68000-series parallel interface protocol in reading mode
CS
D/C
R/W
E
D0
to
D7
LR0082
41/79
Bus interfaces
STE2004S
Figure 48. 68000-series parallel interface protocol in reading mode (several bytes)
CS
D/C
R/W
E
D0
to
D7
Note 1) Data Bus is configured in high impedence mode after evry RD rising edge
2) Always the same data is output on D0-D7
LR0046
4.3.2
8080-series parallel interface
If CS is low after the positive edge of RES, the 8080 parallel interface is ready to receive or
transmit data. While CS pin is high the 8080 parallel interface is kept in reset.
Write mode
Data are latched on WR rising edge.
Read mode
Data is output on the D0-D7 bus on the RD rising edge. The data bus is set in high impedance
mode when RD is set to logic 1.
The I2C address or status byte is output on D0-D7 bus, accordingly to R bit value.
Figure 49. 8080-series parallel bus protocol - one byte transmission
CS
D/C
RD
WR
D0
to
D7
LR0083
42/79
STE2004S
Bus interfaces
Figure 50. 8080-series parallel bus protocol - several bytes transmission
CS
D/C
RD
WR
D0
to
D7
LR0084
Figure 51. 8080-series parallel interface protocol in reading mode
CS
D/C
RD
WR
D0
to
D7
LR0085
Figure 52. 8080-series parallel interface protocol in reading mode (several bytes)
CS
D/C
RD
WR
D0
to
D7
LR0045
Note 1) Data Bus is configured in high impedence mode after every RD rising edge
2) Always the same data is output on D0-D7
43/79
Instruction set
STE2004S
5
Instruction set
Two different instructions formats are provided:
–
–
With D/C set to LOW : commands are sent to the control circuitry.
With D/C set to HIGH : the data RAM is addressed.
Two different instruction sets are embedded: the STE2001-like instruction set and the
extended instruction set. To select the STE2001-like instruction set, the EXT pad must be
connected to a logic LOW (connect to GND). To select the extended instruction set, the EXT
pad must be connected to a logic HIGH (connect to VDD1).
The instruction syntax is summarized in Table 8. (basic-set) and Table 9. (extended set).
Table 8. STE2001/2-like instruction set
Instruction
H=0 or H=1
D/C R/W
B7
B6
B5
B4
B3
B2
B1
B0
Description
Read I2C address or
status byte
(with 3-lines serial and
4-lines SPI only)
Read command
Function set
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Power down
H[0] management; entry
mode;
MX
MY
PD
V
Status byte
ID code
0
0
1
1
1
0
PD BSY
0
1
D
1
E
1
MX
1
MY
ID1
D1
DO (I2C interface only)
0
0
ID0
Write data
D7
D6
D5
D4
D3
D2
D0 Writes data to RAM
H=0
Starts memory blank
procedure
Memory blank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
Scrolls by one row up
or down
Scroll
DIR
PRS[ VLDC programming
0] range selection
VLCD range setting
Display control
Set CP factor
Set RAM Y
0
0
0
0
1
0
Select display
E
0
0
0
1
D
0
configuration
Charge pump
S0
0
0
1
0
S2
Y2
X2
S1
Y1
X1
multiplication factor
Set horizontal (Y)
Y0
1
0
0
Y3
X3
RAM address
Set vertical (X) RAM
address
Set RAM X
X6
X5
X4
X0
44/79
STE2004S
Instruction set
Description
Table 8. STE2001/2-like instruction set
Instruction
H=1
D/C R/W
B7
B6
B5
B4
B3
B2
B1
B0
Starts checker board
procedure
Checker board
Duty
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
MUX Selects duty factor
Set temperature
coefficient for VLDC
TC select
1
TC1 TC0
Data order
Bias ratios
Reserved
0
0
0
0
0
0
0
0
0
0
0
1
0
0
X
0
1
X
1
0
X
DO
0
0
BS2 BS1 BS0 Set desired bias ratios
X
X
X
Not to be used
VOP register write
instruction
Set VOP
0
0
1
OP6 OP5 OP4 OP3 OP2 OP1 OP0
Table 9. Extended instruction set
Instruction
D/C R/W
B7
B6
B5
B4
B3
B2
B1
B0
Description
H independent instructions
Read I2C address or
status byte
(with 3-lines serial and
4-lines SPI only)
Read command
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Page selector, power
H[1] H[0] down management;
entry mode
MX
MY
PD
Status byte
ID code
0
0
1
1
1
0
PD BSY
0
1
D
1
E
1
MX
1
MY
ID1
D1
DO
0
0
ID0
Write data
D7
D6
D5
D4
D3
D2
D0 Writes data to RAM
H=[0;0] RAM commands
Starts memory blank
procedure
Memory blank
Scroll
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
Scrolls by one row up
or down
DIR
PRS[ PRS[ VLDC programming
VLCD range setting
Display control
Set CP factor
Set RAM Y
0
0
0
0
1
1]
0] range selection
Select display
E
0
0
0
1
D
0
configuration
Charge pump
S0
0
0
1
0
S2
Y2
X2
S1
Y1
X1
multiplication factor
Set horizontal (Y)
Y0
1
0
0
Y3
X3
RAM address
Set vertical (X) RAM
address
Set RAM X
X6
X5
X4
X0
45/79
Instruction set
STE2004S
Table 9. Extended instruction set
Instruction
H=[0;1]
D/C R/W
B7
B6
B5
B4
B3
B2
B1
B0
Description
Starts checker board
procedure
Checker board
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Vertical addressing
mode
V
Set temperature
coefficient for VLDC
TC select
1
TC1 TC0
Data order
Bias ratios
Read mode,
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
DO
0
0
MSB position
BS2 BS1 BS0 Set desired bias ratios
R
0
0
0
VOP register write
instruction
Set VOP
0
0
1
OP6 OP5 OP4 OP3 OP2 OP1 OP0
H=[1;0]
Driver control
Display control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
Software reset
PE Partial enable
1
FR1 FR0 Frame rate control
M[1] M[0] MUX ratio
0
Partial mode
PDC
2
PDC
1
1
PDC0 Partial display config
1
st Sector start
address
0
0
0
0
0
1
1
PDY
5
5
PDY
4
4
PDY
PDY
3
3
PDY
PDY
2
PDY
PDY
0
0
2
nd Sector start
PDY
6
PDY
PDY
2
PDY
1
PDY
address
H=[1;1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
X
1
X
X
Scrolling pointer reset
Not used
Not used
Set temperature
coefficient for VLDC
0
0
0
0
0
0
1
T2
T1
T0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
NW3 NW2 NW1 NW0 N-Line inversion
YC-3 YC-2 YC-1 YC-0 Y carriage return
XC-6 XC-5 XC-4 XC-3 XC-2 XC-1 XC-0 X carriage return
46/79
STE2004S
Instruction set
Reset state
Table 10. Explanations of Table 8 and Table 9 symbols
Bit
DIR
0
1
Scroll by one down
Select page 0
Scroll by one up
Select page 1
H[0]
PD
V
0
1
0
0
Device fully working
Horizontal addressing
Normal X axis addressing
Device in power down
Vertical addressing
MX
X axis address is mirrored.
Image is displayed not vertically
mirrored
Image is displayed vertically
mirrored
MY
0
DO
PE
MUX
R
MSB on TOP
MSB on BOTTOM
Partial Display enabled
MUX 33 mode
0
0
0
0
Partial Display disabled
MUX 65 mode
Read ID-Number / I2C address
Read status byte
Table 11. Page selection
H[1]
H[0]
Description
Reset state
0
0
1
1
0
1
0
1
Page 0
Page 1
Page 2
Page 3
Page 0
Table 12. Display mode
D
E
Description
Reset state
0
0
1
1
0
1
0
1
Display blank
Qll display segments on
Normal mode
E=0
D=0
Inverse video mode
Table 13. Frame rate control
FR[1]
FR[0]
Description
Reset state
0
0
1
1
0
1
0
1
65Hz
70Hz
75Hz
80Hz
75Hz
47/79
Instruction set
STE2004S
Table 14. Vlcd range selection
PRS[1]
PRS[0]
Description
Reset state
0
0
1
1
0
1
0
1
2.94
6.78
10.62
10.62
Table 15. Multiplexing ratio
M[1]
M[0]
Description
Reset state
0
0
1
1
0
1
0
1
49
65
33
01
Not Allowed
Table 16. Temperature coefficient (T0, T1, T2)
T2
T1
T0
Description
Reset state
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VLCD temperature coefficient 0
VLCD temperature coefficient 1
VLCD temperature coefficient 2
VLCD temperature coefficient 3
VLCD temperature coefficient 4
VLCD temperature coefficient 5
VLCD temperature coefficient 6
VLCD temperature coefficient 7
000
Table 17. Temperature coefficient (TC0, TC1)
TC1
TC0
Description
Reset state
0
0
0
1
0
1
1
1
VLCD temperature coefficient 0
VLCD temperature coefficient 2
VLCD temperature coefficient 3
VLCD temperature coefficient 6
00
48/79
STE2004S
Instruction set
Table 18. Charge pump multiplication factor
CP2
CP1
CP0
Description
Reset state
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Multiplication factor X2
Multiplication factor X3
Multiplication factor X4
Multiplication factor X5
Not used
000
Not used
Not used
Automatic
Table 19. Bias ratio
BS2
BS1
BS0
Description
Reset state
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bias ratio equal to 7
Bias ratio equal to 6
Bias ratio equal to 5
Bias ratio equal to 4
Bias ratio equal to 3
Bias ratio equal to 2
Bias ratio equal to 1
Bias ratio equal to 0
000
Table 20. Y Carriage return register
Y-C[3]
Y-C[2]
Y-C[1]
Y-C[0]
Description
Y-CARRIAGE =0
Reset state
0
0
0
0
0
.
0
0
0
0
1
.
0
0
1
1
0
.
0
1
0
1
0
.
Y-CARRIAGE =1
Y-CARRIAGE =2
Y-CARRIAGE =3
Y-CARRIAGE =4
1000
0
0
1
1
1
0
1
1
0
0
1
0
Y-CARRIAGE =6
Y-CARRIAGE =7
Y-CARRIAGE =8
49/79
Instruction set
STE2004S
Table 21. Partial display configuration
PD2
PD1
PD0
Section 1
Section 2
Reset state
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
8
8 + Icon row
0 + Icon row
8 + Icon row
16 + Icon row
0 + Icon row
16 + Icon row
8 + Icon row
16 + Icon row
8
0
000
16
8
16
16
Table 22. N-Line inversion
NW3
NW2
NW1
NW0
Description
0-Line inversion
(Frame inversion)
Reset state
0
0
0
0
0
0
0
:
0
0
0
:
0
1
1
:
1
0
1
:
2-Line inversion
3-Line inversion
4-Line inversion
:
0000
1
1
1
1
1
1
0
1
15-Line inversion
16-Line inversion
5.1
Reset (RES)
At power-on, all internal registers are configured with the default value. The RAM content is
not defined. A reset pulse on the RES pad (active low) re-initializes the internal registers
content see Table 10. All on-going communication with the host controller is interrupted if a
reset pulse is applied. After the power-on, the software reset instruction can be used to re-
load the reset configuration into the internal registers.
The default configuration is:
– Horizontal addressing (V = 0)
– Normal instruction set (H[1:0] = 0)
– Normal display (MX = MY = 0)
– Display blank (E = D = 0)
– Multiplexing ratio (M[1:0]=0 - MUX 65)
– Frame rate (FR[1:0]=”75Hz”)
– Power down (PD = 1)
– Dual partial display disabled (PE=0)
– VOP=0
– Address counter X[6: 0] = 0 and Y[4: 0] = 0
– Temperature coefficient (TC[1: 0] = 0)
– Bias system (BS[2: 0] = 0)
– Y-CARRIAGE=8
– X-CARRIAGE=101
A memory blank instruction can be used to clear the DDRAM content.
50/79
STE2004S
Instruction set
5.2
Power down (PD = 1)
At power down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD
generator are off (VLCDOUT output is discharged to VSS, and then VLCDOUT can be
disconnected). The internal oscillator is in off state. An external clock can be provided. The
RAM contents is not cleared.
5.3
Memory blanking procedure
This instruction fills the memory with "blank" patterns, in order to delete patterns randomly
generated in memory when starting up the device. It substitutes (102X8) single "write"
instructions. The procedure can only be programmed if:
PD bit = 0
No instruction can be programmed for a period equivalent to 102X8 internal write cycles
(102X8X1/fclock). The start of the memory blanking procedure is between one and two
fclock cycles from the last active edge (E falling edge for the parallel interface, last SCLK
rising edge for the serial and SPI interfaces, last SCL rising edge for the I2C interface).
5.4
5.5
Checker board procedure
This instruction fills the memory with "checker-board" pattern, allowing developers to create
a complex module test configuration using one instruction. It can only be programmed if:
PD bit = 0
No instruction can be programmed for a period equivalent to 102X8 internal write cycles
(102X8X1/fclock). The start of checker-board procedure is between one and two fclock
cycles from the last active edge (E falling edge for the parallel interface, last SCLK rising
edge for the serial and SPI interfaces, last SCL rising edge for the I2C interface).
Scrolling function
The STE2004S can scroll the graphics display in units of raster-rows. The scrolling function
changes the correspondence between the rows of the logical memory map and the output
row drivers. The scroll function does not affect the data ram contentm it is only related to the
visualization process. The information output on the drivers is related to the row reading
sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling means
reading the matrix starting from a row that is sequentially increased or decreased. After
every scrolling command the offset between the memory address and the memory scanning
pointer is increased or decreased by one. The offset range changes in accordance with
MUX Rate. After 64th/65th scrolling commands in MUX 65 mode, or after the 48th/49th
scrolling commands in MUX 49 mode, or after 32nd/33rd scrolling command in MUX 33
mode, the offset between the memory address and the memory scanning pointer is again
zero (Cyclic Scrolling).
A Reset Scrolling Pointer instruction can be executed to force the offset between the
memory address and the memory scanning pointer to zero.
If ICON MODE =1, the Icon Row is not scrolled. If ICON MODE=0 the last row is like a
general purpose row and it is scrolled as other lines.
51/79
Instruction set
STE2004S
If the DIR bit is set to a logic 0, the offset register is increased by one and the raster is
scrolled from top down. If the DIR bit is set to a logic 1, the offset register is decreased by
one and the raster is scrolled from bottom-up.
Table 23. Scrolling function
MUX Rate
Icon mode
Description
Icon row driver with MY=0
MUX 33
MUX 33
MUX 49
MUX 49
MUX 65
MUX 65
1
0
1
0
1
0
Icon row not scrooled
33 line graphic matrix
Icon row not scrooled
49 line graphic matrix
Icon row not scrooled
65 line graphic matrix
R48
R48
R56
R56
R64
R64
5.6
Dual partial display
If the PE bit is set to a logic one the dual partial display mode is enabled. There are eight
partial display modes available. The offset of the two partial display zones is row by row
programmable. The icon row is accessed last in each partial display frame.
Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0],
BS[2:0], CP[2:0]), allowing normal mode and partial display mode to be switched using one
instruction. The HV generator is automatically reconfigured using the parameters related to
the enabled mode. The parameters of the two sets of registers with the same function are
located in the same position of the instruction set. The registers related to the normal mode
are accessible when normal mode (PE=0) is selected, the others are accessible when the
partial display mode is enabled (PE=1). To setup the PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]
values, follow the instruction flow proposed in Figure 54. To setup partial display sectors
start qddress and partial display mode no particular instruction flow has to be followed.
Figure 53. Dual partial display enabling instruction flow
ENABLE DUAL PARTIAL DISPLAY
SET 1st Sector Start Address
OPTIONAL1
SET 2nd Sector Start Address
SET PE=1
END OF ENABLING DUAL PARTIAL DISPLAY
52/79
STE2004S
Instruction set
Figure 54. Dual partial display mode configuration or duty change
SETUP PARTIAL DISPLAY CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Partial Display Mode (PE=1)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]
for Partial Display Operation
SET Partial Display Configuration (PDC[2:0])
SET 1st Sector Start Address
SET 2nd Sector Start Address
OPTIONAL
SET Driver in Normal Mode (PE=0)
END OF PARTIAL DISPLAY CONFIG.
Table 24. Partial display configurations
PDC2 PDC1 PDC0 Section 1
Section2
Reset state
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
8
8 + Icon Row
0 + Icon Row
8 + Icon Row
16 + Icon Row
0 + Icon Row
16 + Icon Row
8 + Icon Row
16 + Icon Row
8
0
000
16
8
16
16
53/79
ID-number
STE2004S
6
ID-number
The STE2004S lets you program a driver identification number (ID-Number), so more than
one LCD module with different configuration parameters can be managed on one platform.
There are four programmable device ID-numbers: 00111100, 00111101, 0011110 and
0011111. All have the first 6 bits (001111) in common. The two least significant bits can be
used to connect the SA0 and SA1 inputs to a VSS or VDD1.
The driver ID-number can be read through all communication interfaces. The way to read
the ID-number changes according the interface selected. The readout protocol for each
interface is described in Chapter 4.
Figure 55. I2C interface interconnection in master/ slave mode
STE2004S
STE2004S
SDAOUT SDAIN
RES
SCL
SDAOUT SDAIN
RES
SCL
LR0214
NOTE:
MASTER and SLAVE I2C AADDRESS
MUST BE DIFFERENT
RES
SCL
SDA
Figure 56. I3-lines SPI and 3-lines serial interfaces interconnection in master slave
mode
STE2004S
STE2004S
CS SCLK SDIN SDOUT
RES
RES
CS
SCLK SDIN
SDOUT
LR0215
RES MASTER SCLK
CS
SD
SLAVE
CS
54/79
STE2004S
ID-number
Figure 57. 4-lines SPI interface interconnection in master slave mode
STE2004S
STE2004S
SDIN SDOUT
RES
D/C
CS
SCLK
RES
CS
D/C
SCLK
SDIN
SDOUT
LR0216
RES MASTER D/C
CS
SCLK
SD
SLAVE
CS
Figure 58. 8080-series and 68000-series interface interconnection in master slave
mode
STE2004S
D7-D0
STE2004S
D7-D0
CS
D/C RW-RD
E-WR
RES
D/C
RW-RD
RES
CS
E-WR
LR0217
8 LINES
8 LINES
RES MASTER D/C
CS
RW-RD E-WR D7-D0
SLAVE
CS
55/79
ID-number
STE2004S
Figure 59. Host processor interconnection with I2C interface
VSS
TEST_MODE
µP
VSSAUX
D0
D1
D2
STE2004S
D3
D4
D5
D6
D7
SCLK -SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON
ANALOG VDD
DIGITAL VDD
VDD1 / VSSAUX
VSSAUX
SEL1
SEL2
SEL3
EXT_SET
M/S
VDD1 / VSSAUX
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0110
Figure 60. Host processor interconnection with 4-line SPI interface
VSS
TEST_MODE
µP
VSSAUX
D0
D1
D2
STE2004S
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
ANALOG VDD
VDD1
ICON
DIGITAL VDD
VDD1 / VSSAUX
SEL1
SEL2
VDD1
VSSAUX
SEL3
EXT_SET
M/S
VDD1 / VSSAUX
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0111
56/79
STE2004S
ID-number
Figure 61. Host processor interconnection with 3-line SPI interface
VSS
TEST_MODE
µP
VSSAUX
D0
D1
D2
STE2004S
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
ANALOG VDD
VDD1
ICON
DIGITAL VDD
VDD1 / VSSAUX
SEL1
SEL2
VSSAUX
VDD1
SEL3
VSSAUX
EXT_SET
VDD1 / VSSAUX
M/S
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0112
Figure 62. Host processor interconnection with 3-line serial interface
VSS
TEST_MODE
µP
VSSAUX
D0
D1
D2
STE2004S
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
ANALOG VDD
VDD1
ICON
DIGITAL VDD
VDD1 / VSSAUX
SEL1
SEL2
VDD1
VDD1
SEL3
VSSAUX
EXT_SET
VDD1 / VSSAUX
M/S
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0113
57/79
ID-number
STE2004S
Figure 63. Host processor interconnection with 8080-series parallel interface
VSS
TEST_MODE
µP
VSSAUX
D0
D1
D2
STE2004S
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
ANALOG VDD
VDD1
ICON
DIGITAL VDD
VDD1 / VSSAUX
VSSAUX
SEL1
SEL2
VSSAUX
SEL3
VDD1
EXT_SET
M/S
VDD1 / VSSAUX
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0114
Figure 64. Host processor interconnection with 6800
VSS
TEST_MODE
µP
VSSAUX
D0
D1
D2
D3
STE2004S
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
ANALOG VDD
VDD1
ICON
DIGITAL VDD
VDD1 / VSSAUX
SEL1
SEL2
VDD1
VSSAUX
SEL3
VDD1
EXT_SET
M/S
VDD1 / VSSAUX
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0115
58/79
STE2004S
ID-number
Figure 65. Application schematic using the internal LCD voltage generator and two
separate supplies
I/O
VDD2
VDD2
VDD1
32
102
33
VDD1
1µF
1µF
VSS
VSS
65 x 102
DISPLAY
1µF
VLCDSENSE
VLCD
Figure 66. Application schematic using the internal LCD voltage generator and a
single supply
I/O
VDD
VDD2
VDD1
32
102
33
1µF
65 x 102
DISPLAY
VSS
VSS
1µF
VLCDSENSE
VLCD
59/79
ID-number
STE2004S
Figure 67. Power-ON timing diagram
T
vdd
Tw(res)
Tlogic(res)
VDD2
VDD1
RES
CS
SCLK
SDIN
D/C
E
R/W
D0 - D7
HOST
D0 - D7
DRIVER
Hi-Z
Hi-Z
SCL- SDAIN
SDOUT -
SDA OUT
OSCIN, FR_IN
(HOST)
OSC OUT, FR_OUT
(DRIVER)
POWER ON
INTERNAL
RESET
RESET
Acceptance
Time
BOOSTER
OFF
LR0208
60/79
STE2004S
ID-number
Figure 68. Power-OFF timing diagram
TVDD
VDD2
VDD1
RES
CLK-SCL
SDIN-SDAIN
D/C
E
CS
R/W
D0 - D7
HOST
D0 - D7
DRIVER
Hi-Z
Hi-Z
SDOUT
SDA-OUT
OSCIN
(HOST)
OSC OUT
FR_OUT
(DRIVER)
FR_IN
RESET
TABLE
LOADED
LR0207
61/79
ID-number
STE2004S
Figure 69. Initialization with built-in booster
SETUP NORMAL DISPLAY MODE CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Normal Display Mode (PE=0)
SET Operative Voltage for Normal Display Operation
( Vop[6:0] - PRS[1;0])
SET Bias Raio for Normal Display Operation
(BS[2:0])
SET Temperature Compensation for
Normal Display Operation (T[2:0] or TC[1:0])
SET Multiplexing Rate
M[1:0)
SET Charge Pump for
Normal Display Operation (CP[1:0])
Switch "ON" Booster and Display Control Logic
(PD=0)
END OF NORMAL DISPLAY MODE CONFIG.
LR0218
62/79
STE2004S
ID-number
Figure 70. Data RAM to display mapping
DISPLAY DATA RAM
bank
0
GLASS
TOP VIEW
bank
1
DISPLAY DATA RAM = "1"
DISPLAY DATA RAM = "0"
bank
2
LCD
bank
3
bank
7
bank
8
ICOR ROW
D00IN1155
Table 25. Test pin configuration
Test Pin
Pin Configuration
TEST_VREF
TEST_MODE
OPEN
GND
63/79
Electrical characteristics
STE2004S
7
Electrical characteristics
7.1
Absolute maximum ratings
Table 26. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD1
VDD2
VLCD
ISS
Supply voltage range
- 0.5 to + 5
- 0.5 to + 7
- 0.5 to + 15
- 50 to +50
-0.5 to VDD1 + 0.5
- 10 to + 10
- 10 to + 10
300
V
V
Supply voltage range
LCD supply voltage range
Supply current
V
mA
V
Vi
Input voltage (all input pads)
DC input current
Iin
mA
mA
mW
mW
°C
°C
Iout
Ptot
Po
DC output current
Total power dissipation (Tj = 85°C)
Power dissipation per output
Operating junction temperature(1)
Storage temperature
30
Tj
-25 to + 85
- 65 to 150
Tstg
1. Device behavior and characterization are measured over this temperature range during internal qualification of the product.
During production testing, however, device performance is measured at a fixed ambient temperature - typically 25°C.
7.2
DC operation
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =25°C;
unless otherwise specified.
Table 27. DC operation
Symbol
Parameter
Test condition
Min.
1.7
Typ.
Max.
Unit
Supply voltages
3.6
V
V
VDD1
Supply voltage(1)
VDD2
LCD voltage internally
generated
VDD2
Supply voltage
1.75
4.5
V
LCD voltage supplied
externally
LCD supply voltage
LCD supply voltage
4.5
4.5
14.5
14.5
V
V
VLCD
Internally generated(2)
VDD1 = 2.8V;
Supply current
V
LCD = 10V; fsclk = 0;
15
20
40
µA
µA
Parallel Port (3) (5)
I(VDD1
)
VDD2 = 2.8V;
Supply current write
mode
V
LCD = 10V; fsclk = 1Mhz;
100
200
OSC_IN=GND(3)
64/79
STE2004S
Electrical characteristics
Table 27. DC operation (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
with VOP = 0 and
PRS = [0:0] with external
VLCD
5
µA
(4)
Voltage generator supply
current
I(VDD2
)
VDD2 = 2.8V;
VLCD = 10V; fsclk=0;
no display load;
60
150
µA
5x charge pump(5)(3) (6)
VDD2 = 2.8V; VLCD
=
10V; 5x charge pump;
80
3
190
15
µA
µA
µA
f
sclk = 0;
no display load(5) (3) (6)
I(VDD1,2
)
Total supply current
Power down mode with
internal or external
VLCD(7)
VDD =2.8V;
VLCD =10V;
no display load;
fsclk = 0;(3)
External LCD supply
voltage current
I(VLDCIN
)
25
Logic outputs
High logic level output
voltage
V0H
IOH=-500µA
IOL=+500µA
0.8VDD1
VSS
VDD1
V
V
Low logic level output
voltage
VOL
0.2VDD1
Logic inputs
VIL
VIH
Iin
Logic low voltage level
Logic high voltage level
Input current
VSS
0.7 VDD1
-1
0.3 VDD1
VDD2
1
V
V
Vin = VSS1 or VDD1
µA
Logic inputs/outputs
VIL
VIH
Logic low voltage level
Logic high voltage level
VSS
0.3 VDD1
V
V
0.7 VDD1
VDD1 + 0.5
65/79
Electrical characteristics
STE2004S
Unit
Table 27. DC operation (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Column and row driver
Rrow
Rcol
ROW output resistance
3K
5K
5K
kohm
kohm
Column output
resistance
10K
Column bias voltage
accuracy
Vcol
No load
-50
-50
+50
+50
mV
mV
Row bias voltage
accuracy
Vrow
LCD supply voltage
VDD = 2.8V; VLCD = 10V;
fsclk=0;
LCD supply voltage
accuracy; internally
generated
VLCD
-2
+2
%
no display load(5)(3) (6) (8)
VOP=69h, PRS=2Hex(9)
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
-0.0· 10-3
-0.35 · 10-3
-0.7 · 10-3
-1.05· 10-3
-1.4 · 10-3
-1.75· 10-3
-2.1 · 10-3
-2.3· 10-3
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
Temperature coefficient
1. VDD1<=VDD2
2. The maximum possible V
voltage that can be generated is dependent on voltage, temperature and (display) load.
LCD
3. When f
= 0 there is no interface clock.
sclk
4. If external V
, the display load current is not transmitted to I
DD
LCD
5. Internal clock
6. Tolerance depends on the temperature; (typically zero at T
temperature range limit.
= 25°C), maximum tolerance values are measured at the
amb
7. Power-down mode. During power-down all static currents are switched-off.
8. For TC0 to TC7
9. Data byte writing mode
66/79
STE2004S
Electrical characteristics
7.3
AC operation
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =25°C;
unless otherwise specified.
Table 28. AC operation
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Internal oscillator (Figure 71)
Internal oscillator
frequency
FOSC
VDD = 2.8V
61
20
72
83
kHz
kHz
External oscillator
frequency
FEXT
100
FFRAME Frame frequency
fosc or fext = 72 kHz(1)
75
Hz
µs
µs
RES LOW pulse width
Tw(RES)
5
Reset pulse rejection
1
5
TLOGIC
Internal logic reset time
µs
µs
(RES)
TVDD
VDD1 vs. VDD2 Delay
0
I2C bus interface (Figure 72)(2) (3)
Fast mode
DC
DC
400
3.4
kHz
High speed mode;
Cb=100pF (max);(4)
VDD1=2
MHz
FSCL
SCL clock frequency
High speed mode;
Cb=400pF (max)(4)
VDD1=2
;
DC
1.7
MHz
Fast Mode (4);VDD1=1.7V
400
KHz
ns
Set-up time (repeated)
START condition
TSU;STA
THD;STA
TLOW
Cb = 100pF(5) (6)
160
160
160
160
Hold time (repeated)
START condition
Cb = 100pF(5) (6)
Cb = 100pF(5) (6)
Cb = 100pF(5) (6)
ns
ns
ns
Low period of SCLH
clock
High period of SCLH
clock
THIGH
TSU;DAT Data set-up time
THD;DAT Data hold time
Cb = 100pF(5) (6)
Cb = 100pF(5) (6)
60
10
10
ns
ns
ns
T
Rise time of SCLH signal Cb = 100pF(5) (6)
r;CL
Rise time of SCLH signal
after a repeated START
condition and aftyer an
acknowledge bit
T
Cb = 100pF(5) (6)
10
10
ns
ns
r;CL1
Tf;CL
Fall time of SCLH signal Cb = 100pF(5) (6)
67/79
Electrical characteristics
Table 28. AC operation
STE2004S
Unit
Symbol
Parameter
Test condition
Min.
Typ.
Max.
T
Rise time of SCLH signal Cb = 100pF(5) (6)
Fall time of SDAH signal Cb = 100pF(5) (6)
Rise time of SDAH signal Cb = 400pF(5) (6)
Fall time of SDAH signal Cb = 400pF(5) (6)
10
10
20
20
ns
ns
ns
ns
r;DA
Tf;DA
80
T
r;DA
Tf;DA
160
Setup time for STOP
Cb = 100pF(5) (6)
condition
TSU;STO
160
100
ns
pF
Capacitive load for SDAH
and SCLH
Cb
Cb
400
400
Capacitive load for SDAH
+SDA line and SCLH
+SCL line
pF
Parallel interface (Figure 73, Figure 74)
VDD1 = 1.7V;
read and write
TCYC
TCLW
TCHW
TCLR
System cycle time
125
20
75
40
55
60
60
60
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control low pulse width
(WR)
Control high pulse width
(WR)
Control low pulse width
(RD)
Control high pulse width
(RD)
TCHR
Enable high pulse width
(Write)
TEWHW
TEWLW
TEWHR
TEWLR
Enable low pulse width
(Write)
Enable high pulse width
(Read)
Enable low pulse width
(Read)
TSU(A)
TH(A)
TSU1
TH1
Address set-up time
Address hold time
Data set-up time
Data hold time
10
10
30
30
ns
ns
ns
ns
ns
ns
TSU2
TH2
Read access time
Output disable time
40
30
0
68/79
STE2004S
Electrical characteristics
Table 28. AC operation
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Serial interface (Figure 75)
FSCLK
TCYC
TPWH1
TPWL1
TS2
Clock frequency
VDD1 = 1.7V;
8
125
60
60
40
50
50
30
30
30
40
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycle SCLK
SCLK pulse width HIGH
SCLK pulse width LOW
CS setup time
VDD1 = 1.7V
VDD1 = 1.7V
VDD1 = 1.7V
TH2
CS hold time
TPWH2
TS3
CS minimum high time
SD/C setup time
SD/C hold time
TH3
TS4
SDIN setup time
SDIN hold time
TH4
TS5
SDOUT access time
30
20
SDOUT disable time vs.
SCLK
TH5
TH6
0
0
ns
ns
SDOUT disable time vs.
CS
20
fosc
1.
Fframe = ---------
960
2. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
3. Trise and Tfall (30%-70%) -10ns
4.
C
is the filtering capacitor on VLCD
VLCD
5. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V and
IL
V
with an input voltage swing of V to V
SS DD
IH
6. Cb is the capacitive load for each bus line.
69/79
Electrical characteristics
Figure 71. Reset timing diagram
STE2004S
Tw(res)
Tlogic(res)
VDD2
VDD1
RES
INPUTS
I/O
(HOST)
I/O
(DRIVER)
Hi-Z
Hi-Z
INTERFACE
OUTPUT
OSCIN
FR_IN
(HOST)
OSC OUT
FR_OUT
(DRIVER)
RESET
TABLE
LOADED
LR0209
Figure 72. I2C-bus timings
Sr
Sr P
t
t
rDA
fDA
SDAH
SCLH
t
HD;DAT
t
HD;STA
t
SU;DAT
t
SU;STA
t
fCL
t
t
t
rCL1
rCL
rCL1
(1)
(1)
t
t
t
t
LOW HIGH
HIGH LOW
LR0093
= MCS current source pull-up
= Rp resistor pull-up
70/79
STE2004S
Electrical characteristics
Figure 73. 68000-series parallel interface timing
D/C
R/W
t
SU(A)
tH(A)
CS
E
t
CYC
t
EWHR, tEWHW
t
EWLR
,
t
EWLW
t
SU1
t
H1
D0 to D7
(Write)
t
SU2
tH2
D0 to D7
(Read)
Figure 74. 8080-series parallel interface timing
D/C
tSU(A)
tH (A)
CS
tCYC
tCLR , tCLW
WR, RD
tCHR , tCHW
tH1
tSU1
D0 to D7
(Write)
tSU2
tH2
D0 to D7
(Read)
71/79
Pad coordinates
Figure 75. Serial interface timing
STE2004S
t
S2
t
H2
t
PWH2
CS
t
t
H3
S3
D/C
t
CYC
t
t
WH1
PWL1
t
S2
SCLK
SDIN
SOUT
t
t
H4
S4
t
H6
t
t
H5
S5
LR0096
8
Pad coordinates
See Table 29: Pad coordinates and Table 30: Alignment marks coordinates.
72/79
STE2004S
Pad coordinates
Pad placements
Table 29. Pad coordinates
Pad placements
No
Name
No
Name
X
Y
X
Y
1
R5
R4
-2632.5
-2587.5
-2542.5
-2497.5
-2452.5
-2407.5
-2362.5
-2317.5
-2272.5
-2227.5
-2182.5
-2137.5
-2092.5
-2047.5
-2002.5
-1957.5
-1912.5
-1867.5
-1822.5
-1777.5
-1732.5
-1687.5
-1642.5
-1597.5
-1552.5
-1507.5
-1462.5
-1417.5
-1372.5
-1327.5
-1282.5
-1237.5
-1192.5
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
-1147.5
-1102.5
-1057.5
-1012.5
-967.5
-922.5
-877.5
-832.5
-787.5
-742.5
-697.5
-652.5
-607.5
-562.5
-517.5
-472.5
-427.5
-382.5
-337.5
-292.5
-247.5
-202.5
-157.5
-112.5
112.5
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
2
3
R3
4
R2
5
R1
6
R0
7
C0
8
C1
9
C2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
157.5
202.5
247.5
292.5
337.5
382.5
427.5
472.5
73/79
Pad coordinates
STE2004S
Table 29. Pad coordinates
Pad placements
Pad placements
No
Name
No
Name
X
Y
X
Y
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
517.5
562.5
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
C93
C94
C95
C96
C97
C98
C99
C100
C101
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
2002.5
2047.5
2092.5
2137.5
2182.5
2227.5
2272.5
2317.5
2362.5
2407.5
2452.5
2497.5
2542.5
2587.5
2632.5
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
2773.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-532.8
-472.5
-427.5
-382.5
-337.5
-292.5
-247.5
-202.5
-157.5
-112.5
-67.5
607.5
652.5
697.5
742.5
787.5
832.5
877.5
922.5
967.5
1012.5
1057.5
1102.5
1147.5
1192.5
1237.5
1282.5
1327.5
1372.5
1417.5
1462.5
1507.5
1552.5
1597.5
1642.5
1687.5
1732.5
1777.5
1822.5
1867.5
1912.5
1957.5
-22.5
22.5
67.5
112.5
157.5
202.5
247.5
292.5
74/79
STE2004S
Pad coordinates
Pad placements
Table 29. Pad coordinates
Pad placements
No
Name
No
Name
X
Y
X
Y
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
R56
R57
2773.8
2773.8
2773.8
2773.8
2632.5
2587.5
2542.5
2497.5
2452.5
2227.5
2182.5
2137.5
2092.5
1777.5
1732.5
1687.5
1642.5
1597.5
1552.5
1507.5
1462.5
1417.5
1372.5
1327.5
1282.5
1237.5
1192.5
1147.5
1102.5
1057.5
1012.5
967.5
337.5
382.5
427.5
472.5
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
_RES
-CS
877.5
832.5
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
R58
787.5
R59
742.5
R60
697.5
R61
652.5
R62
337.5
R63
247.5
R64/ICON
VDD1 AUX
FR IN
OSC IN
Vsns_Slave
TEST_VREF
VSSAUX
SA1
D/C
157.5
RW-RD
E-WR
VSSAUX
SDA_OUT
SDIN_SDAIN
SDOUT
SCLK_SCL
D7
67.5
-22.5
-67.5
-157.5
-202.5
-247.5
-337.5
-382.5
-427.5
-472.5
-517.5
-562.5
-607.5
-652.5
-697.5
-742.5
-1102.5
-1147.5
-1192.5
-1237.5
-1282.5
-1327.5
-1372.5
-1417.5
SA0
M/S
D6
EXT_SET
SEL3
D5
D4
SEL2
D3
SEL1
D2
ICON
D1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
D0
VSSAUX
TEST_MODE
VSS
VSS
VSS
VSS
VSS
VSS
922.5
VSS
75/79
Pad coordinates
STE2004S
Table 29. Pad coordinates
Pad placements
Pad placements
No
Name
No
Name
X
Y
X
Y
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
2
VSS
VSS
-1462.5
-1507.5
-1552.5
-1597.5
-1642.5
-1867.5
-1912.5
-1957.5
-2002.5
-2047.5
-2092.5
-2227.5
-2272.5
-2497.5
-2542.5
-2587.5
-2632.5
-2773.8
-2773.8
-2773.8
-2773.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
532.8
472.5
427.5
382.5
337.5
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
-2773.8
292.5
247.5
202.5
157.5
112.5
67.5
VSS
VSS
VSS
VLCD_SNS
VLCD
VLCD
VLCD
VLCD
VLCD
OSC_OUT
FR_OUT
R31
22.5
-22.5
-67.5
-112.5
-157.5
-202.5
-247.5
-292.5
-337.5
-382.5
-427.5
-472.5
R30
R29
R8
R28
R7
R27
R6
R26
R25
R24
1. I C bus AC characteristics are tested by correlation
Table 30. Alignment marks coordinates
Marks
X
Y
mark1
mark2
mark3
mark4
-2780.55
2780.55
-2160.0
484.89
-539.55
-539.55
539.55
539.55
76/79
STE2004S
Pad coordinates
Figure 76. Alignment marks dimensions
35 µm
85 µm
Table 31. Bumps
Dimensions
Bumps size
28µmX97µmX17.5µm
35µm X 104µm
45µm
Pad size
Pad pitch
Spacing between bumps
17µm
Table 32. Die mechanical dimensions
Die Size (X x Y)
5.815mm x 1.333mm
Wafers thickness
500µm
77/79
Ordering information
STE2004S
9
Ordering information
Table 33. Ordering information
Part numbers
Type
STE2004S DIE2
Bumped dice on waffle pack
10
Revision history
Table 34. Document revision history
Date
Revision
Changes
24-Jan-2006
1
Initial release.
– Junction temperature range in Table 26: Absolute maximum
ratings set to: -25 to + 85 and added a footnote.
– Globally set Tamb = 25°C
12-Dec-2006
31-Jan-2007
2
3
– Moved Table 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 from
Chapter 6: ID-number to Chapter 5: Instruction set where Table 8
and Table 9 are referenced.
– Ordering information moved from cover page to Chapter 9.
Added Chapter 1: Block diagram and corrected the document title.
78/79
STE2004S
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